fix(dcache): bankoffset及时更新
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Liphen
parent
fa41d30146
commit
277c3d31ad
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@ -74,7 +74,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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})
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// * fsm * //
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val s_idle :: s_uncached :: s_writeback :: s_replace :: s_wait :: Nil = Enum(5)
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val s_idle :: s_uncached :: s_fence :: s_replace :: s_wait :: Nil = Enum(5)
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val state = RegInit(s_idle)
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// ==========================================================
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@ -107,10 +107,21 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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val dirty = RegInit(VecInit(Seq.fill(nindex)(VecInit(Seq.fill(nway)(false.B)))))
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val lru = RegInit(VecInit(Seq.fill(nindex)(false.B))) // TODO:支持更多路数，目前只支持2路
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val dirty_table = Wire(Vec(nindex, UInt(log2Ceil(nway).W)))
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val dirty_index = Wire(UInt(indexWidth.W))
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val dirty_way = dirty_table(dirty_index) // 用于指示哪个路的脏位为真
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val writeback_index = RegInit(0.U(indexWidth.W))
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for (i <- 0 until nindex) {
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dirty_table(i) := PriorityEncoder(dirty(i))
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}
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dirty_index := PriorityEncoder(dirty_table.map(w => w =/= 0.U))
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// 对于uncached段使用writeFifo进行写回
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val writeFifo = Module(new Queue(new WriteBufferUnit(), writeFifoDepth))
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val writeFifo_axi_busy = RegInit(false.B)
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val writeFifo_busy = (writeFifo.io.deq.valid || writeFifo_axi_busy)
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val writeFifo_busy = writeFifo.io.deq.valid // || writeFifo_axi_busy 应该不需要这个判断
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writeFifo.io.enq.valid := false.B
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writeFifo.io.enq.bits := 0.U.asTypeOf(new WriteBufferUnit())
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@ -141,6 +152,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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val tag_wdata = RegInit(0.U(tagWidth.W))
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val data = Wire(Vec(nbank, Vec(nway, UInt(XLEN.W))))
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// 使用寄存器类型才能防止idle时tag出现无法hit的错误
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val tag = RegInit(VecInit(Seq.fill(nway)(0.U(tagWidth.W))))
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val tag_compare_valid = Wire(Vec(nway, Bool()))
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@ -164,6 +176,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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io.cpu.rdata := Mux(state === s_wait, saved_rdata, data(bank_index)(select_way))
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// bank tagv ram
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val tagRam = Seq.fill(nway)(Module(new LUTRam(nindex, tagWidth)))
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for { i <- 0 until nway } {
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val bank = Seq.fill(nbank)(Module(new SimpleDualPortRam(nindex, AXI_DATA_WID, byteAddressable = true)))
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for { j <- 0 until nbank } {
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@ -176,13 +189,12 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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bank(j).io.wdata := replace_wdata
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bank(j).io.wstrb := replace_wstrb(j)(i)
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val tagRam = Module(new LUTRam(nindex, tagWidth))
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tagRam.io.raddr := tag_rindex
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tag(i) := tagRam.io.rdata
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tagRam(i).io.raddr := tag_rindex
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tag(i) := tagRam(i).io.rdata
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tagRam.io.wen := tag_wstrb(i)
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tagRam.io.waddr := replace_index
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tagRam.io.wdata := tag_wdata
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tagRam(i).io.wen := tag_wstrb(i)
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tagRam(i).io.waddr := replace_index
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tagRam(i).io.wdata := tag_wdata
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tag_compare_valid(i) := tag(i) === io.cpu.tlb.ptag && valid(replace_index)(i) && io.cpu.tlb.translation_ok
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@ -219,7 +231,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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io.cpu.acc_err := acc_err
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// write buffer
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when(writeFifo_axi_busy) { // To implement SC memory ordering, when store buffer busy, axi is unseable.
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when(writeFifo_axi_busy) {
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when(io.axi.aw.fire) {
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awvalid := false.B
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}
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@ -304,27 +316,27 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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}
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}
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}.elsewhen(io.cpu.fence) {
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assert(false.B, "fence not implemented")
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// when(dirty(replace_index).contains(true.B)) {
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// // fence.i 需要将所有脏位为true的行写回
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// when(dirty.asUInt.orR) {
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// when(!writeFifo_busy) {
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// state := s_writeback
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// write_offset := 0.U // 从第一块bank开始写回
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// state := s_fence
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// writeback_index := dirty_index // 从第一个脏行开始写回
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// bank_woffset := 0.U // 从第一块bank开始写回
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// // for axi write
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// aw.addr := Cat(tag(dirty(replace_index)(1)), replace_index, 0.U(offsetWidth.W))
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// tagRam.map(_.io.raddr := writeback_index)
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// val writeback_tag = Mux(dirty_way === 0.U, tagRam(0).io.rdata, tagRam(1).io.rdata)
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// aw.addr := Cat(writeback_tag, writeback_index, 0.U(offsetWidth.W))
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// aw.len := cached_len.U
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// aw.size := cached_size.U
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// awvalid := true.B
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// w.data := data(dirty(replace_index)(1))(bank_index)
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// w.data := data(writeback_index)(0)
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// w.strb := ~0.U(AXI_STRB_WID.W)
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// w.last := false.B
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// wvalid := true.B
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// }
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// }.otherwise {
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// when(valid(replace_index).contains(true.B)) {
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// valid(replace_index)(0) := false.B
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// valid(replace_index)(1) := false.B
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// }
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// // 当所有脏位为fault时，fence.i可以直接完成
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// state := s_wait
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// }
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}
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@ -339,14 +351,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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state := s_wait
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}
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}
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is(s_writeback) {
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assert(false.B, "writeback not implemented")
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// when(burst_cnt.value =/= (cached_len).U) {
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// burst_cnt.inc()
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// }
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// read_ready_cnt := burst_cnt.value
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// read_buffer(read_ready_cnt) := data(dirty(index)(1))
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is(s_fence) {
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// when(io.axi.aw.fire) {
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// awvalid := false.B
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// }
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@ -354,22 +359,17 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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// when(w.last) {
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// wvalid := false.B
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// }.otherwise {
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// w.data := Mux(
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// ((axi_cnt.value + 1.U) === read_ready_cnt),
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// data(dirty(index)(1)),
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// read_buffer(axi_cnt.value + 1.U)
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// )
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// axi_cnt.inc()
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// when(axi_cnt.value + 1.U === (cached_len).U) {
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// bank_woffset := bank_woffset + 1.U
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// w.data := bank_replication(bank_woffset)
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// when(bank_woffset + 1.U === (cached_len).U) {
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// w.last := true.B
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// }
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// }
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// }
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// when(io.axi.b.valid) {
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// dirty(index)(dirty(index)(1)) := false.B
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// burst.valid := false.B
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// acc_err := io.axi.b.bits.resp =/= RESP_OKEY.U
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// state := s_idle
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// // TODO: 增加此处的错误处理
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// // acc_err := io.axi.b.bits.resp =/= RESP_OKEY.U
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// replace_dirty := false.B // 写回完成，清除脏位
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// }
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}
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is(s_replace) {
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@ -439,6 +439,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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w.strb := ~0.U(AXI_STRB_WID.W)
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w.last := false.B
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wvalid := true.B
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bank_woffset := bank_woffset + 1.U // TODO:这里应该需要更新offset
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}
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}
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}
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