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可以实现差分测试

This commit is contained in:
Liphen 2023-11-23 16:17:15 +08:00
parent 6fbb02fffc
commit 24baf95dd7
3 changed files with 3 additions and 2 deletions
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2
chisel/Makefile
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@ -10,7 +10,7 @@ verilog:
mill -i __.test.runMain Elaborate -td $(BUILD_DIR) mill -i __.test.runMain Elaborate -td $(BUILD_DIR)
func: func:
# cp $(BUILD_DIR)/PuaCpu.v $(DIFF_DIR) cp $(BUILD_DIR)/PuaCpu.v $(DIFF_DIR)
cd $(DIFF_WORK_DIR) && make func cd $(DIFF_WORK_DIR) && make func
test: test:

2
chisel/difftest

@ -1 +1 @@
Subproject commit 1f6c6a632c18a0fd1daf6b1c09a8fa56717b7679 Subproject commit 219f3b97c692c2b0c16aca7769487e3ab4fbe0a5

1
chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
View File

@ -64,4 +64,5 @@ class WriteBackUnit(implicit val config: CpuConfig) extends Module {
io.regfile(1).wdata io.regfile(1).wdata
) )
} }
io.debug.wb_rf_wen := io.ctrl.allow_to_go
} }