fix: ret相关指令只进行单发射

chisel/playground/src/defines/Bundles.scala

@@ -42,6 +42,7 @@ class InstInfo extends Bundle {
   val reg_waddr  = UInt(REG_ADDR_WID.W)
   val imm        = UInt(XLEN.W)
   val inst       = UInt(XLEN.W)
+  val ret        = Vec(RetType.num, Bool())
 }
 
 class MemRead extends Bundle {

chisel/playground/src/defines/isa/Instructions.scala

@@ -170,6 +170,13 @@ object CSROpType {
   def clri = "b111".U
 }
 
+object RetType {
+  def uret = 0.U
+  def sret = 1.U
+  def mret = 2.U
+  def num  = 3
+}
+
 trait HasCSRConst {
   // User Trap Setup
   val Ustatus = 0x000

chisel/playground/src/pipeline/decode/Decoder.scala

@@ -5,7 +5,7 @@ import chisel3.util._
 import cpu.defines._
 import cpu.defines.Const._
 
-class Decoder extends Module with HasInstrType {
+class Decoder extends Module with HasInstrType with HasCSRConst {
   val io = IO(new Bundle {
     // inputs
     val in = Input(new Bundle {
@@ -37,6 +37,7 @@ class Decoder extends Module with HasInstrType {
   val (rs, rt, rd) = (inst(19, 15), inst(24, 20), inst(11, 7))
 
   io.out.info.valid      := false.B
+  io.out.info.inst       := inst
   io.out.info.inst_legal := instrType =/= InstrN
   io.out.info.src1_ren   := src1Type === SrcType.reg
   io.out.info.src1_raddr := Mux(io.out.info.src1_ren, rs, 0.U)
@@ -57,5 +58,7 @@ class Decoder extends Module with HasInstrType {
       InstrJ  -> SignedExtend(Cat(inst(31), inst(19, 12), inst(20), inst(30, 21), 0.U(1.W)), XLEN)
     )
   )
-  io.out.info.inst := inst
+  io.out.info.ret(RetType.uret) := inst(31, 20) === privUret && fuOpType === CSROpType.jmp && fuType === FuType.csr
+  io.out.info.ret(RetType.sret) := inst(31, 20) === privSret && fuOpType === CSROpType.jmp && fuType === FuType.csr
+  io.out.info.ret(RetType.mret) := inst(31, 20) === privMret && fuOpType === CSROpType.jmp && fuType === FuType.csr
 }

chisel/playground/src/pipeline/decode/Issue.scala

@@ -68,8 +68,14 @@ class Issue(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
       inst1.fusel === FuType.csr && inst1.op =/= CSROpType.jmp && inst1.inst(31, 20) === Satp.U
     ).asUInt.orR
 
+    // uret、sret、mret指令会导致流水线清空
+    val ret = inst0.ret.asUInt.orR || inst1.ret.asUInt.orR
+
+    // 这些csr相关指令会导致流水线清空
+    val is_some_csr_inst = write_satp || ret
+
     // 下面的情况只进行单发射
-    val single_issue = is_mou || is_bru || write_satp
+    val single_issue = is_mou || is_bru || is_some_csr_inst
 
     // 指令1是否允许执行
     io.inst1.allow_to_go :=

chisel/playground/src/pipeline/execute/fu/Csr.scala

@@ -309,13 +309,10 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
   MaskedRegMap.generate(ipMapping, addr, rdataDummy, wen, wdata)
 
   // CSR inst decode
-  val ret = Wire(Bool())
+  val ret    = Wire(Bool())
-  val isMret =
+  val isMret = mem_inst_info.ret(RetType.mret) && mem_valid
-    mem_addr === privMret && mem_inst_info.op === CSROpType.jmp && mem_inst_info.fusel === FuType.csr && mem_valid
+  val isSret = mem_inst_info.ret(RetType.sret) && mem_valid
-  val isSret =
+  val isUret = mem_inst_info.ret(RetType.uret) && mem_valid
-    mem_addr === privSret && mem_inst_info.op === CSROpType.jmp && mem_inst_info.fusel === FuType.csr && mem_valid
-  val isUret =
-    mem_addr === privUret && mem_inst_info.op === CSROpType.jmp && mem_inst_info.fusel === FuType.csr && mem_valid
   ret := isMret || isSret || isUret
 
   val exceptionNO = ExcPriority.foldRight(0.U)((i: Int, sum: UInt) => Mux(mem_ex.exception(i), i.U, sum))