fix(dcache): 修复replace时写回逻辑问题

This commit is contained in:
Liphen 2024-01-20 13:36:25 +08:00
parent a99cf13f87
commit 1ce49a39b3
1 changed files with 34 additions and 30 deletions

View File

@ -177,6 +177,7 @@ class DCache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Mo
// 是否使用exe的地址进行提前访存
val use_next_addr = (state === s_idle) || (state === s_wait)
val do_replace = RegInit(false.B)
val readbank = RegInit(false.B)
// replace index 表示行的索引
val replace_index = Wire(UInt(indexWidth.W))
replace_index := io.cpu.addr(indexWidth + offsetWidth - 1, offsetWidth)
@ -504,9 +505,11 @@ class DCache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Mo
}
}
}.otherwise {
// 这里相当于增加了一拍用于发射读写控制信号
// 增加了一拍用于sram读取数据
readbank := true.B
when(readbank) {
readbank := false.B
do_replace := true.B
ar.len := cached_len.U
ar.size := cached_size.U // 8 字节
arvalid := true.B
@ -528,7 +531,7 @@ class DCache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Mo
aw.len := cached_len.U
aw.size := cached_size.U
awvalid := true.B
w.data := data(0)(replace_way)
w.data := bank_replication(0)
w.strb := ~0.U(AXI_STRB_WID.W)
w.last := false.B
wvalid := true.B
@ -537,6 +540,7 @@ class DCache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Mo
}
}
}
}
is(s_wait) {
// 等待流水线的allow_to_go信号防止多次发出读写请求
io.cpu.tlb.ptw.vpn.ready := !ptw_working