修改if级逻辑

chisel/playground/src/pipeline/fetch/FetchUnit.scala

@@ -4,55 +4,41 @@ import chisel3._
 import chisel3.util._
 import cpu.defines.Const._
 import cpu.CpuConfig
+import cpu.defines._
+import cpu.pipeline.decode.FetchUnitDecodeUnit
 
-class FetchUnit(
-  implicit
-  val cpuConfig: CpuConfig)
-    extends Module {
+class ExecuteUnitFetchUnit extends Bundle {
+  val flush  = Output(Bool())
+  val target = Output(UInt(XLEN.W))
+}
+
+class FetchUnit extends Module {
   val io = IO(new Bundle {
-    val memory = new Bundle {
-      val flush  = Input(Bool())
-      val target = Input(UInt(XLEN.W))
-    }
-    val decode = new Bundle {
-      val branch = Input(Bool())
-      val target = Input(UInt(XLEN.W))
-    }
-    val execute = new Bundle {
-      val flush  = Input(Bool())
-      val target = Input(UInt(XLEN.W))
-    }
-    val instFifo = new Bundle {
-      val full = Input(Bool())
-    }
-    val iCache = new Bundle {
-      val inst_valid = Input(Vec(cpuConfig.instFetchNum, Bool()))
-      val pc         = Output(UInt(XLEN.W))
-      val pc_next    = Output(UInt(XLEN.W))
-    }
-
+    val ctrl        = new FetchUnitCtrl()
+    val execute     = Flipped(new ExecuteUnitFetchUnit())
+    val decodeStage = Output(new FetchUnitDecodeUnit())
+    val instSram    = new InstSram()
   })
-  val pc = RegNext(io.iCache.pc_next, PC_INIT)
-  io.iCache.pc := pc
-
-  // when inst_valid(1) is true, inst_valid(0) must be true
+  val pc = RegNext(io.instSram.addr, PC_INIT)
 
   val pc_next_temp = Wire(UInt(XLEN.W))
 
   pc_next_temp := pc
-  for (i <- 0 until cpuConfig.instFetchNum) {
-    when(io.iCache.inst_valid(i)) {
-      pc_next_temp := pc + ((i + 1) * 4).U
-    }
-  }
 
-  io.iCache.pc_next := MuxCase(
-    pc_next_temp,
+  io.instSram.addr := MuxCase(
+    pc + 4.U,
     Seq(
-      io.memory.flush  -> io.memory.target,
       io.execute.flush     -> io.execute.target,
-      io.decode.branch -> io.decode.target,
-      io.instFifo.full -> pc
+      !io.ctrl.allow_to_go -> pc
     )
   )
+
+  io.decodeStage.data.valid           := RegNext(!reset.asBool, false.B) & !reset.asBool
+  io.decodeStage.data.pc              := pc
+  io.decodeStage.data.inst            := io.instSram.rdata
+  io.decodeStage.data.addr_misaligned := pc(1, 0) =/= 0.U
+
+  io.instSram.en    := !reset.asBool & !io.decodeStage.data.addr_misaligned
+  io.instSram.wen   := 0.U
+  io.instSram.wdata := 0.U
 }