From 160daec1e2abf940d5b6dfa4be842de2ba430fdc Mon Sep 17 00:00:00 2001 From: Liphen Date: Wed, 29 Nov 2023 21:31:54 +0800 Subject: [PATCH] =?UTF-8?q?fix(icache):=20=E4=BF=AE=E5=A4=8D=E6=97=A0cache?= =?UTF-8?q?=E6=97=B6=E7=9A=84=E5=8F=96=E6=8C=87=E9=97=AE=E9=A2=98?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/cache/ICache.scala | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/chisel/playground/src/cache/ICache.scala b/chisel/playground/src/cache/ICache.scala index e31daed..8f36330 100644 --- a/chisel/playground/src/cache/ICache.scala +++ b/chisel/playground/src/cache/ICache.scala @@ -17,12 +17,11 @@ class ICache(implicit config: CpuConfig) extends Module { val s_idle :: s_uncached :: s_save :: Nil = Enum(3) val status = RegInit(s_idle) - val read_next_addr = (status === s_idle || status === s_save) - val pc = Cat(io.cpu.addr(read_next_addr)(31, 2), 0.U(2.W)) + val read_next_addr = true.B // 未接入cache时默认使用下一个地址 + val araddr = Cat(io.cpu.addr(read_next_addr)(31, 2), 0.U(2.W)) // default val arvalid = RegInit(false.B) - val araddr = RegInit(0.U(AXI_ADDR_WID.W)) io.axi.ar.id := 0.U io.axi.ar.addr := araddr io.axi.ar.len := 0.U @@ -61,7 +60,6 @@ class ICache(implicit config: CpuConfig) extends Module { saved(0).valid := true.B status := s_save }.otherwise { - araddr := pc arvalid := true.B io.axi.ar.len := 0.U io.axi.ar.size := 2.U