From 10cca9929b39d7fb0248f378e5286a7572b0a001 Mon Sep 17 00:00:00 2001 From: Liphen Date: Sun, 26 Nov 2023 15:06:51 +0800 Subject: [PATCH] =?UTF-8?q?fix(id):=20=E4=BF=AE=E5=A4=8Dlui=E8=AF=91?= =?UTF-8?q?=E7=A0=81=E4=BF=A1=E5=8F=B7=E9=94=99?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/pipeline/decoder/Decoder.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chisel/playground/src/pipeline/decoder/Decoder.scala b/chisel/playground/src/pipeline/decoder/Decoder.scala index 52bf3bd..969abc5 100644 --- a/chisel/playground/src/pipeline/decoder/Decoder.scala +++ b/chisel/playground/src/pipeline/decoder/Decoder.scala @@ -38,7 +38,7 @@ class Decoder extends Module with HasInstrType { io.out.inst_info.valid := false.B io.out.inst_info.inst_legal := instrType =/= InstrN - io.out.inst_info.reg1_ren := src1Type === SrcType.reg + io.out.inst_info.reg1_ren := src1Type === SrcType.reg || inst(6, 0) === "b0110111".U // fix LUI io.out.inst_info.reg1_raddr := Mux(src1Type === SrcType.reg, rs, 0.U) io.out.inst_info.reg2_ren := src2Type === SrcType.reg io.out.inst_info.reg2_raddr := Mux(src2Type === SrcType.reg, rt, 0.U)