diff --git a/chisel/playground/src/pipeline/execute/fu/Csr.scala b/chisel/playground/src/pipeline/execute/fu/Csr.scala
index e90878b..a79363e 100644
--- a/chisel/playground/src/pipeline/execute/fu/Csr.scala
+++ b/chisel/playground/src/pipeline/execute/fu/Csr.scala
@@ -398,7 +398,7 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
     mstatusNew.mpp   := ModeU
     mstatus          := mstatusNew.asUInt
     lr               := false.B
-    ret_target       := mepc(VADDR_WID - 1, 0)
+    ret_target       := mepc
   }
 
   when(isSret) {
@@ -411,7 +411,7 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
     mstatusNew.spp   := ModeU
     mstatus          := mstatusNew.asUInt
     lr               := false.B
-    ret_target       := sepc(VADDR_WID - 1, 0)
+    ret_target       := sepc
   }
 
   io.tlb.imode          := mode
diff --git a/chisel/playground/src/pipeline/memory/lsu/LsExecute.scala b/chisel/playground/src/pipeline/memory/lsu/LsExecute.scala
index 095b0f0..582e42e 100644
--- a/chisel/playground/src/pipeline/memory/lsu/LsExecute.scala
+++ b/chisel/playground/src/pipeline/memory/lsu/LsExecute.scala
@@ -78,10 +78,8 @@ class LsExecute extends Module {
   val isStore     = valid && LSUOpType.isStore(op)
   val partialLoad = !isStore && (op =/= LSUOpType.ld)
 
-  val has_acc_err = addr(XLEN - 1, VADDR_WID).orR
-
   val size     = op(1, 0)
-  val reqAddr  = if (XLEN == 32) SignedExtend(addr, VADDR_WID) else addr(VADDR_WID - 1, 0)
+  val reqAddr  = if (XLEN == 32) SignedExtend(addr, XLEN) else addr
   val reqWdata = if (XLEN == 32) genWdata32(io.in.wdata, size) else genWdata(io.in.wdata, size)
   val reqWmask = if (XLEN == 32) genWmask32(addr, size) else genWmask(addr, size)
 
@@ -133,7 +131,7 @@ class LsExecute extends Module {
     )
   )
 
-  io.dataMemory.out.en    := valid && !io.out.storeAddrMisaligned && !io.out.loadAddrMisaligned && !has_acc_err
+  io.dataMemory.out.en    := valid && !io.out.storeAddrMisaligned && !io.out.loadAddrMisaligned
   io.dataMemory.out.rlen  := size
   io.dataMemory.out.wen   := isStore
   io.dataMemory.out.wstrb := reqWmask
@@ -144,9 +142,9 @@ class LsExecute extends Module {
   io.out.ready               := io.dataMemory.in.ready && io.dataMemory.out.en
   io.out.rdata               := Mux(partialLoad, rdataPartialLoad, rdataSel)
   io.out.loadAddrMisaligned  := valid && !isStore && !is_amo && !addrAligned
-  io.out.loadAccessFault     := valid && !isStore && !is_amo && (access_fault || has_acc_err)
+  io.out.loadAccessFault     := valid && !isStore && !is_amo && access_fault
   io.out.loadPageFault       := valid && !isStore && !is_amo && page_fault
   io.out.storeAddrMisaligned := valid && (isStore || is_amo) && !addrAligned
-  io.out.storeAccessFault    := valid && (isStore || is_amo) && (access_fault || has_acc_err)
+  io.out.storeAccessFault    := valid && (isStore || is_amo) && access_fault
   io.out.storePageFault      := valid && (isStore || is_amo) && page_fault
 }