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修改顶层接口

This commit is contained in:
Liphen 2024-05-27 15:40:25 +08:00
parent d2bc851cf7
commit 0797cd651e
2 changed files with 4 additions and 4 deletions
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6
chisel/playground/src/defines/Bundles.scala
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@ -7,9 +7,9 @@ import cpu.defines.Const._
import cpu.CpuConfig import cpu.CpuConfig
class ExtInterrupt extends Bundle { class ExtInterrupt extends Bundle {
val ei = Bool() val mei = Bool()
val ti = Bool() val mti = Bool()
val si = Bool() val msi = Bool()
} }
class SrcInfo extends Bundle { class SrcInfo extends Bundle {

2
difftest

@ -1 +1 @@
Subproject commit e2b04f50f1fa43f0153bac2a21f1bbcc98f050be Subproject commit 8fb9d90b00e02be2baa7536ffa43fe0a6d6dc7f6