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zhangdengyu 81c25c6d54 refactor: 优化csky/xtensa/riscv架构中断管理框架 
方案描述：
1、在最外层arch/include/los_interrupt.h中定义数据结构、声明对外接口；
2、在arch/xxx/common实现xxx架构中断通用的接口定义与声明；
3、在arch/xxx/yyy中实现针对xxx架构的差异化实现;
4、修改宏数值，适配整个中断管理框架

BREAKING CHANGE:
优化csky/xtensa/riscv架构中断管理框架对外变更描述：
1、宏OS_ERRNO_HWI_OPS_FUNC_NULL数值改为0x0200090c

Close: #I7DRTP

Signed-off-by: zhangdengyu <zhangdengyu2@huawei.com>
Change-Id: Ic7cab8222ceab846b2557ff9047f7c6cd34b2b44
 		2023-06-15 21:37:31 +08:00
..
arm9/gcc refactor: 优化csky/xtensa/riscv架构中断管理框架 2023-06-15 21:37:31 +08:00
common refactor：重构ARM架构下的中断管理框架 2023-06-14 16:15:37 +08:00
cortex-m3/keil refactor: 优化csky/xtensa/riscv架构中断管理框架 2023-06-15 21:37:31 +08:00
cortex-m4 refactor: 优化csky/xtensa/riscv架构中断管理框架 2023-06-15 21:37:31 +08:00
cortex-m7 refactor: 优化csky/xtensa/riscv架构中断管理框架 2023-06-15 21:37:31 +08:00
cortex-m33 refactor: 优化csky/xtensa/riscv架构中断管理框架 2023-06-15 21:37:31 +08:00
cortex-m55 refactor: 优化csky/xtensa/riscv架构中断管理框架 2023-06-15 21:37:31 +08:00
include chore: move kernel/arch to arch 2021-11-16 00:45:24 +08:00
BUILD.gn refactor：重构ARM架构下的中断管理框架 2023-06-14 16:15:37 +08:00
Kconfig feature: 编译框架支持iccarm 2022-07-12 14:54:15 +08:00