133 lines
3.8 KiB
ArmAsm
133 lines
3.8 KiB
ArmAsm
/*
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* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
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* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this list of
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* conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice, this list
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* of conditions and the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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.equ OS_PSR_INT_DIS, 0xC0
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.equ OS_PSR_FIQ_DIS, 0x40
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.equ OS_PSR_IRQ_DIS, 0x80
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.equ OS_PSR_MODE_MASK, 0x1F
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.equ OS_PSR_MODE_USR, 0x10
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.equ OS_PSR_MODE_FIQ, 0x11
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.equ OS_PSR_MODE_IRQ, 0x12
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.equ OS_PSR_MODE_SVC, 0x13
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.equ OS_PSR_MODE_ABT, 0x17
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.equ OS_PSR_MODE_UND, 0x1B
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.equ OS_PSR_MODE_SYS, 0x1F
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.equ OS_EXCEPT_RESET, 0x00
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.equ OS_EXCEPT_UNDEF_INSTR, 0x01
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.equ OS_EXCEPT_SWI, 0x02
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.equ OS_EXCEPT_PREFETCH_ABORT, 0x03
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.equ OS_EXCEPT_DATA_ABORT, 0x04
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.equ OS_EXCEPT_FIQ, 0x05
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.equ OS_EXCEPT_ADDR_ABORT, 0x06
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.equ OS_EXCEPT_IRQ, 0x07
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.global HalExceptAddrAbortHdl
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.global HalExceptDataAbortHdl
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.global HalExceptPrefetchAbortHdl
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.global HalExceptUndefInstrHdl
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.extern HalExcHandleEntry
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.extern __exc_stack_top
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.code 32
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.text
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HalExceptUndefInstrHdl:
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STMFD SP!, {R0-R5}
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MOV R0, #OS_EXCEPT_UNDEF_INSTR
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B _osExceptDispatch
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HalExceptPrefetchAbortHdl:
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SUB LR, LR, #4
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STMFD SP!, {R0-R5}
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MOV R0, #OS_EXCEPT_PREFETCH_ABORT
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B _osExceptDispatch
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HalExceptDataAbortHdl:
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SUB LR, LR, #4
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STMFD SP!, {R0-R5}
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MOV R0, #OS_EXCEPT_DATA_ABORT
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B _osExceptDispatch
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HalExceptAddrAbortHdl:
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SUB LR, LR, #8
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STMFD SP!, {R0-R5}
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MOV R0, #OS_EXCEPT_ADDR_ABORT
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B _osExceptDispatch
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_osExceptDispatch:
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MRS R1, SPSR
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MOV R2, LR
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MOV R4, SP
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ADD SP, SP, #(6 * 4)
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MSR CPSR_c, #(OS_PSR_INT_DIS | OS_PSR_MODE_SVC)
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MOV R3, SP
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LDR SP, =__exc_stack_top
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STMFD SP!, {R2}
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STMFD SP!, {LR}
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STMFD SP!, {R3}
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STMFD SP!, {R6-R12}
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LDMFD R4!, {R6-R12}
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STMFD SP!, {R6-R11}
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STMFD SP!, {R1}
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MOV R3, SP
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_osExceptionGetSP:
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STMFD SP!, {R1}
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LDR R2, =HalExcHandleEntry
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MOV LR, PC
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BX R2
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LDMFD SP!, {R1}
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MOV SP, R1
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LDMFD SP!, {R1}
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MSR CPSR, R1
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LDMFD SP!, {R0-R12}
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ADD SP, SP, #(4 * 2)
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LDMFD SP!, {LR}
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SUB SP, SP, #(4 * 3)
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LDMFD SP, {SP}
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ADD LR, LR, #4
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MOV PC, LR
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.end
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