113 lines
4.5 KiB
C
113 lines
4.5 KiB
C
/*
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* Copyright (c) 2013-2020, Huawei Technologies Co., Ltd. All rights reserved.
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* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this list of
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* conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice, this list
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* of conditions and the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SOC_COMMON_H
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#define _SOC_COMMON_H
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#define LREG lw
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#define SREG sw
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#define REGBYTES 4
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#define EXC_SIZE_ON_STACK (36 * REGBYTES)
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#define INT_SIZE_ON_STACK (32 * REGBYTES)
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/* task TCB offset */
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#define TASK_CB_KERNEL_SP 0x0
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#define TASK_CB_STATUS 0x4
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#define UINT32_CUT_MASK 0xFFFFFFFF
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#define UINT8_CUT_MASK 0xFF
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#define OS_MV_32_BIT 32
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/************************ mstatus ************************/
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#define RISCV_MSTATUS_UIE 0x00000001
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#define RISCV_MSTATUS_MIE 0x00000008
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#define RISCV_MSTATUS_UPIE 0x00000010
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#define RISCV_MSTATUS_MPIE 0x00000080
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#define RISCV_MSTATUS_MPP 0x00001800
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/************************ mie ***************************/
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#define RISCV_MIE_USIE 0x000000001
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#define RISCV_MIE_MSIE 0x000000008
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#define RISCV_MIE_UTIE 0x000000010
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#define RISCV_MIE_MTIE 0x000000080
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#define RISCV_MIE_UEIE 0x000000100
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#define RISCV_MIE_MEIE 0x000000800
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/************************** mcause ***********************/
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#define RISCV_MCAUSE_ECALL_U 8
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#define RISCV_USER_SOFT_IRQ 0
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#define RISCV_MACH_SOFT_IRQ 3
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#define RISCV_USER_TIMER_IRQ 4
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#define RISCV_MACH_TIMER_IRQ 7
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#define RISCV_USER_EXT_IRQ 8
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#define RISCV_MACH_EXT_IRQ 11
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#define READ_CSR(reg) ({ \
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UINT32 _tmp; \
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__asm__ volatile("csrr %0, " #reg : "=r"(_tmp) : : "memory"); \
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_tmp; \
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})
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#define WRITE_CSR(reg, val) ({ \
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__asm__ volatile("csrw " #reg ", %0" : : "r"(val) : "memory"); \
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})
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#define SET_CSR(reg, val) ({ \
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__asm__ volatile("csrs " #reg ", %0" : : "r"(val) : "memory"); \
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})
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#define CLEAR_CSR(reg, val) ({ \
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__asm__ volatile("csrc " #reg ", %0" : : "r"(val) : "memory"); \
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})
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#define READ_CUSTOM_CSR(reg) ({ \
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UINT32 _tmp; \
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__asm__ volatile("csrr %0, %1" : "=r"(_tmp) : "i"(reg) : "memory"); \
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_tmp; \
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})
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#define WRITE_CUSTOM_CSR(reg, val) ({ \
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__asm__ volatile("csrw %0, %1" : : "i"(reg), "r"(val) : "memory"); \
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})
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#define SET_CUSTOM_CSR(reg, val) ({ \
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__asm__ volatile("csrs " #reg ", %0" : : "r"(val) : "memory"); \
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})
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#define CLEAR_CUSTOM_CSR(reg, val) ({ \
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__asm__ volatile("csrc " #reg ", %0" : : "r"(val) : "memory"); \
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})
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#endif
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