184 lines
5.1 KiB
ArmAsm
184 lines
5.1 KiB
ArmAsm
/*
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* Copyright (c) 2013-2020, Huawei Technologies Co., Ltd. All rights reserved.
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* Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this list of
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* conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice, this list
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* of conditions and the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "soc_common.h"
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.global HalEnableIRQ
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.global HalDisableIRQ
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.global ArchIntLock
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.global ArchIntUnLock
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.global ArchIntRestore
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.global HalStartToRun
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.global HalTaskContextSwitch
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.extern __irq_stack_top
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.section .interrupt.text
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.macro PUSH_ALL_REG
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addi sp, sp, -(32 * REGBYTES)
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SREG t6, 2 * REGBYTES(sp)
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SREG t5, 3 * REGBYTES(sp)
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SREG t4, 4 * REGBYTES(sp)
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SREG t3, 5 * REGBYTES(sp)
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SREG t2, 6 * REGBYTES(sp)
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SREG t1, 7 * REGBYTES(sp)
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SREG t0, 8 * REGBYTES(sp)
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SREG s11, 9 * REGBYTES(sp)
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SREG s10, 10 * REGBYTES(sp)
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SREG s9, 11 * REGBYTES(sp)
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SREG s8, 12 * REGBYTES(sp)
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SREG s7, 13 * REGBYTES(sp)
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SREG s6, 14 * REGBYTES(sp)
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SREG s5, 15 * REGBYTES(sp)
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SREG a7, 18 * REGBYTES(sp)
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SREG a6, 19 * REGBYTES(sp)
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SREG a5, 20 * REGBYTES(sp)
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SREG a4, 21 * REGBYTES(sp)
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SREG a3, 22 * REGBYTES(sp)
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SREG a2, 23 * REGBYTES(sp)
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SREG a1, 24 * REGBYTES(sp)
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SREG a0, 25 * REGBYTES(sp)
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SREG s4, 26 * REGBYTES(sp)
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SREG s3, 27 * REGBYTES(sp)
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SREG s2, 28 * REGBYTES(sp)
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SREG s1, 29 * REGBYTES(sp)
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SREG s0, 30 * REGBYTES(sp)
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SREG ra, 31 * REGBYTES(sp)
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.endm
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.macro POP_ALL_REG
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LREG t6, 2 * REGBYTES(sp)
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LREG t5, 3 * REGBYTES(sp)
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LREG t4, 4 * REGBYTES(sp)
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LREG t3, 5 * REGBYTES(sp)
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LREG t2, 6 * REGBYTES(sp)
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LREG t1, 7 * REGBYTES(sp)
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LREG t0, 8 * REGBYTES(sp)
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LREG s11, 9 * REGBYTES(sp)
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LREG s10, 10 * REGBYTES(sp)
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LREG s9, 11 * REGBYTES(sp)
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LREG s8, 12 * REGBYTES(sp)
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LREG s7, 13 * REGBYTES(sp)
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LREG s6, 14 * REGBYTES(sp)
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LREG s5, 15 * REGBYTES(sp)
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LREG a7, 18 * REGBYTES(sp)
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LREG a6, 19 * REGBYTES(sp)
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LREG a5, 20 * REGBYTES(sp)
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LREG a4, 21 * REGBYTES(sp)
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LREG a3, 22 * REGBYTES(sp)
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LREG a2, 23 * REGBYTES(sp)
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LREG a1, 24 * REGBYTES(sp)
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LREG a0, 25 * REGBYTES(sp)
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LREG s4, 26 * REGBYTES(sp)
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LREG s3, 27 * REGBYTES(sp)
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LREG s2, 28 * REGBYTES(sp)
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LREG s1, 29 * REGBYTES(sp)
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LREG s0, 30 * REGBYTES(sp)
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LREG ra, 31 * REGBYTES(sp)
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addi sp, sp, 32 * REGBYTES
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.endm
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HalTaskContextSwitch:
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PUSH_ALL_REG
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// clear mpie
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li a2, RISCV_MSTATUS_MPIE
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not a2, a2
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and a0, a0, a2
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// get mie
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andi a1, a0, RISCV_MSTATUS_MIE
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// must be in machine mode
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ori a1, a1, 0x180
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slli a1, a1, 0x4
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or a0, a0, a1
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// clear mie
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li a2, RISCV_MSTATUS_MIE
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not a2, a2
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and a0, a0, a2
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SREG a0, 16 * REGBYTES(sp)
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SREG ra, 17 * REGBYTES(sp)
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la a1, g_losTask
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lw a0, 0(a1)
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sw sp, TASK_CB_KERNEL_SP(a0)
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lw a0, 4(a1)
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sw a0, 0(a1)
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HalStartToRun:
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la a1, g_losTask
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lw a0, 4(a1)
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// retireve stack pointer
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lw sp, TASK_CB_KERNEL_SP(a0)
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// enable global interrupts
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lw t0, 16 * REGBYTES(sp)
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csrw mstatus, t0
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// retrieve the address at which exception happened
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lw t0, 17 * REGBYTES(sp)
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csrw mepc, t0
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// retrieve the registers
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POP_ALL_REG
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mret
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.section .text
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HalDisableIRQ:
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li t0, (RISCV_MSTATUS_MPIE | RISCV_MSTATUS_MIE) // mpie | mie
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csrrc zero, mstatus, t0
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ret
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HalEnableIRQ:
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csrsi mstatus, RISCV_MSTATUS_MIE
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ret
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ArchIntLock:
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csrr a0, mstatus // return value
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li t0, RISCV_MSTATUS_MIE // mie
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csrrc zero, mstatus, t0
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ret
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ArchIntUnLock:
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csrr a0, mstatus // return value
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li t0, RISCV_MSTATUS_MIE // mie
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csrrs zero, mstatus, t0
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ret
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ArchIntRestore:
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csrw mstatus, a0
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ret
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