diff --git a/arch/arm/cortex-m3/keil/los_timer.c b/arch/arm/cortex-m3/keil/los_timer.c
index 57254186..22105e22 100644
--- a/arch/arm/cortex-m3/keil/los_timer.c
+++ b/arch/arm/cortex-m3/keil/los_timer.c
@@ -86,7 +86,7 @@ STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
     SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
-    NVIC_ClearPendingIRQ(SysTick_IRQn);
+    SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 
     return nextResponseTime;
diff --git a/arch/arm/cortex-m33/gcc/NTZ/los_timer.c b/arch/arm/cortex-m33/gcc/NTZ/los_timer.c
index 229e7a51..701dfad5 100644
--- a/arch/arm/cortex-m33/gcc/NTZ/los_timer.c
+++ b/arch/arm/cortex-m33/gcc/NTZ/los_timer.c
@@ -85,7 +85,7 @@ STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
     SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
-    NVIC_ClearPendingIRQ(SysTick_IRQn);
+    SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
     return nextResponseTime;
 }
diff --git a/arch/arm/cortex-m33/gcc/TZ/non_secure/los_timer.c b/arch/arm/cortex-m33/gcc/TZ/non_secure/los_timer.c
index 6081ceb3..aa153d85 100644
--- a/arch/arm/cortex-m33/gcc/TZ/non_secure/los_timer.c
+++ b/arch/arm/cortex-m33/gcc/TZ/non_secure/los_timer.c
@@ -84,7 +84,7 @@ STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
     SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
-    NVIC_ClearPendingIRQ(SysTick_IRQn);
+    SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
     return nextResponseTime;
 }
diff --git a/arch/arm/cortex-m33/iar/NTZ/los_timer.c b/arch/arm/cortex-m33/iar/NTZ/los_timer.c
index d3eb9b21..b8448c2b 100644
--- a/arch/arm/cortex-m33/iar/NTZ/los_timer.c
+++ b/arch/arm/cortex-m33/iar/NTZ/los_timer.c
@@ -84,7 +84,7 @@ STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
     SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
-    NVIC_ClearPendingIRQ(SysTick_IRQn);
+    SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
     return nextResponseTime;
 }
diff --git a/arch/arm/cortex-m33/iar/TZ/non_secure/los_timer.c b/arch/arm/cortex-m33/iar/TZ/non_secure/los_timer.c
index 361ac086..ef108339 100644
--- a/arch/arm/cortex-m33/iar/TZ/non_secure/los_timer.c
+++ b/arch/arm/cortex-m33/iar/TZ/non_secure/los_timer.c
@@ -85,7 +85,7 @@ STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
     SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
-    NVIC_ClearPendingIRQ(SysTick_IRQn);
+    SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
     return nextResponseTime;
 }
diff --git a/arch/arm/cortex-m4/gcc/los_timer.c b/arch/arm/cortex-m4/gcc/los_timer.c
index 45ae62c5..f60ec28e 100644
--- a/arch/arm/cortex-m4/gcc/los_timer.c
+++ b/arch/arm/cortex-m4/gcc/los_timer.c
@@ -84,7 +84,7 @@ STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
     SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
-    NVIC_ClearPendingIRQ(SysTick_IRQn);
+    SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
     return nextResponseTime;
 }
diff --git a/arch/arm/cortex-m4/iar/los_timer.c b/arch/arm/cortex-m4/iar/los_timer.c
index 99721b87..6e1a5598 100644
--- a/arch/arm/cortex-m4/iar/los_timer.c
+++ b/arch/arm/cortex-m4/iar/los_timer.c
@@ -84,7 +84,7 @@ STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
     SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
-    NVIC_ClearPendingIRQ(SysTick_IRQn);
+    SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
     return nextResponseTime;
 }
diff --git a/arch/arm/cortex-m55/gcc/NTZ/los_timer.c b/arch/arm/cortex-m55/gcc/NTZ/los_timer.c
index b284544d..88abd259 100644
--- a/arch/arm/cortex-m55/gcc/NTZ/los_timer.c
+++ b/arch/arm/cortex-m55/gcc/NTZ/los_timer.c
@@ -84,7 +84,7 @@ STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
     SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
-    NVIC_ClearPendingIRQ(SysTick_IRQn);
+    SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
     return nextResponseTime;
 }
diff --git a/arch/arm/cortex-m55/gcc/TZ/non_secure/los_timer.c b/arch/arm/cortex-m55/gcc/TZ/non_secure/los_timer.c
index 6081ceb3..aa153d85 100644
--- a/arch/arm/cortex-m55/gcc/TZ/non_secure/los_timer.c
+++ b/arch/arm/cortex-m55/gcc/TZ/non_secure/los_timer.c
@@ -84,7 +84,7 @@ STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
     SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
-    NVIC_ClearPendingIRQ(SysTick_IRQn);
+    SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
     return nextResponseTime;
 }
diff --git a/arch/arm/cortex-m55/iar/NTZ/los_timer.c b/arch/arm/cortex-m55/iar/NTZ/los_timer.c
index d3eb9b21..b8448c2b 100644
--- a/arch/arm/cortex-m55/iar/NTZ/los_timer.c
+++ b/arch/arm/cortex-m55/iar/NTZ/los_timer.c
@@ -84,7 +84,7 @@ STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
     SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
-    NVIC_ClearPendingIRQ(SysTick_IRQn);
+    SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
     return nextResponseTime;
 }
diff --git a/arch/arm/cortex-m55/iar/TZ/non_secure/los_timer.c b/arch/arm/cortex-m55/iar/TZ/non_secure/los_timer.c
index 361ac086..ef108339 100644
--- a/arch/arm/cortex-m55/iar/TZ/non_secure/los_timer.c
+++ b/arch/arm/cortex-m55/iar/TZ/non_secure/los_timer.c
@@ -85,7 +85,7 @@ STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
     SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
-    NVIC_ClearPendingIRQ(SysTick_IRQn);
+    SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
     return nextResponseTime;
 }
diff --git a/arch/arm/cortex-m7/gcc/los_timer.c b/arch/arm/cortex-m7/gcc/los_timer.c
index 99721b87..6e1a5598 100644
--- a/arch/arm/cortex-m7/gcc/los_timer.c
+++ b/arch/arm/cortex-m7/gcc/los_timer.c
@@ -84,7 +84,7 @@ STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
     SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
-    NVIC_ClearPendingIRQ(SysTick_IRQn);
+    SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
     return nextResponseTime;
 }
diff --git a/arch/arm/cortex-m7/iar/los_timer.c b/arch/arm/cortex-m7/iar/los_timer.c
index 99721b87..6e1a5598 100644
--- a/arch/arm/cortex-m7/iar/los_timer.c
+++ b/arch/arm/cortex-m7/iar/los_timer.c
@@ -84,7 +84,7 @@ STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
     SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
-    NVIC_ClearPendingIRQ(SysTick_IRQn);
+    SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
     return nextResponseTime;
 }