fix: 修复内核目录不规范的问题
【背景】 内核中targets目录的位置不规范 【修改方案】 从内核仓库中删除targets目录 【影响】 对现有的产品编译不会有影响。 re #I5EFBF Signed-off-by: yinjiaming <yinjiaming@huawei.com> Change-Id: Ic77eac4583c4ce141050ed1fe661d837408413ac
This commit is contained in:
yinjiaming
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@ -59,7 +59,6 @@ The directory structure is as follows. For more details, see [arch_spec.md](arch
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├── kernel # Minimum kernel function set
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├── kernel # Minimum kernel function set
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│ ├── include # APIs exposed externally
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│ ├── include # APIs exposed externally
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│ └── src # Source code of the minimum kernel function set
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│ └── src # Source code of the minimum kernel function set
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├── targets # Board-level projects
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├── testsuites # Kernel testsuites
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├── testsuites # Kernel testsuites
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├── tools # Kernel tools
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├── tools # Kernel tools
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├── utils # Common directory
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├── utils # Common directory
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@ -107,12 +106,6 @@ The LiteOS-M kernel porting projects for specific development boards are provide
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This repository provides the project code for porting the OpenHarmony LiteOS-M kernel to support the STM32F429IGTb development board. The code supports build in Ninja, GCC, and IAR modes.
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This repository provides the project code for porting the OpenHarmony LiteOS-M kernel to support the STM32F429IGTb development board. The code supports build in Ninja, GCC, and IAR modes.
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- Cortex-M7:
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- Nucleo-F767ZI https://gitee.com/harylee/nucleo_f767zi
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This repository provides the project code for porting the OpenHarmony LiteOS-M kernel to support the Nucleo-F767ZI development board. The code supports build in Ninja, GCC, and IAR modes.
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## Contribution<a name="section1371123476307"></a>
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## Contribution<a name="section1371123476307"></a>
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[How to involve](https://gitee.com/openharmony/docs/blob/HEAD/en/contribute/contribution.md)
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[How to involve](https://gitee.com/openharmony/docs/blob/HEAD/en/contribute/contribution.md)
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@ -57,7 +57,6 @@ OpenHarmony LiteOS-M内核是面向IoT领域构建的轻量级物联网操作系
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├── kernel # 内核最小功能集支持
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├── kernel # 内核最小功能集支持
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│ ├── include # 对外接口存放目录
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│ ├── include # 对外接口存放目录
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│ └── src # 内核最小功能集源码
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│ └── src # 内核最小功能集源码
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├── targets # 板级工程目录
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├── testsuites # 内核测试用例
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├── testsuites # 内核测试用例
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├── tools # 内核工具
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├── tools # 内核工具
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├── utils # 通用公共目录
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├── utils # 通用公共目录
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@ -106,12 +105,6 @@ LiteOS-M内核移植的具体开发板的工程由社区开发者提供，可以
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该仓包含OpenHarmony LiteOS-M内核移植支持`野火挑战者STM32F429IGTb`开发板的工程代码，支持Ninja、GCC、IAR等方式进行编译。
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该仓包含OpenHarmony LiteOS-M内核移植支持`野火挑战者STM32F429IGTb`开发板的工程代码，支持Ninja、GCC、IAR等方式进行编译。
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- cortex-m7：
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- Nucleo-F767ZI https://gitee.com/harylee/nucleo_f767zi
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该仓包含OpenHarmony LiteOS-M内核移植支持`Nucleo-F767ZI`开发板的工程代码，支持Ninja、GCC、IAR等方式进行编译。
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## 贡献<a name="section1371123476307"></a>
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## 贡献<a name="section1371123476307"></a>
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[如何贡献](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/contribute/%E5%8F%82%E4%B8%8E%E8%B4%A1%E7%8C%AE.md)
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[如何贡献](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/contribute/%E5%8F%82%E4%B8%8E%E8%B4%A1%E7%8C%AE.md)
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@ -72,14 +72,6 @@
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│ │ ├── los_task.h --- Tasks
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│ │ ├── los_task.h --- Tasks
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│ │ └── los_tick.h --- Tick
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│ │ └── los_tick.h --- Tick
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│ └── src
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│ └── src
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├── targets
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│ └── riscv_nuclei_demo_soc_gcc
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│ │ ├── GCC --- Compilation config
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│ │ ├── OS_CONFIG --- Board config
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│ │ ├── SoC --- SOC codes
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│ │ └── Src --- Application codes
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│ └── riscv_nuclei_gd32vf103_soc_gcc
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│ └── riscv_sifive_fe310_gcc
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├── testsuites --- Kernel testsuites
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├── testsuites --- Kernel testsuites
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├── tools --- Kernel tools
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├── tools --- Kernel tools
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└── utils
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└── utils
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@ -70,15 +70,7 @@
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│ │ ├── los_swtmr.h --- 定时器
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│ │ ├── los_swtmr.h --- 定时器
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│ │ ├── los_task.h --- 任务
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│ │ ├── los_task.h --- 任务
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│ │ └── los_tick.h --- Tick时钟
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│ │ └── los_tick.h --- Tick时钟
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└── src
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│ └── src
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├── targets
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│ └── riscv_nuclei_demo_soc_gcc
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│ │ ├── GCC --- 编译相关
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│ │ ├── OS_CONFIG --- 开发板配置功能开关和配置参数
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│ │ ├── SoC --- SOC相关代码
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│ │ └── Src --- Application相关代码
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│ └── riscv_nuclei_gd32vf103_soc_gcc
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│ └── riscv_sifive_fe310_gcc
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├── testsuites --- 内核测试用例
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├── testsuites --- 内核测试用例
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├── tools --- 内核工具
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├── tools --- 内核工具
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└── utils
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└── utils
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@ -1,9 +0,0 @@
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# ignore openocd logfile and build folder
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targets/*/GCC/build/
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*.log
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*.lst
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*.bin
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*.dasm
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*.elf
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*.hex
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*.map
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@ -1,222 +0,0 @@
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# ------------------------------------------------
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# Generic Makefile (based on gcc)
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#
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# ChangeLog :
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# 2021-04-02 - first version
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# ------------------------------------------------
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######################################
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# target
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######################################
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TARGET = Nuclei-demo-soc
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######################################
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# building variables
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######################################
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# debug build?
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DEBUG = 1
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# optimization
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OPT = -O2
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#######################################
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# paths
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#######################################
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# Build path
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BUILD_DIR = build
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#######################################
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# Base directory
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#######################################
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# LiteOS top path
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LITEOSTOPDIR := ../../../
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######################################
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# source
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######################################
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# C sources
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C_SOURCES = \
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$(wildcard ../Src/*.c) \
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$(wildcard ../SoC/demosoc/Common/Source/*.c) \
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$(wildcard ../SoC/demosoc/Common/Source/Drivers/*.c) \
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$(wildcard ../SoC/demosoc/Common/Source/Stubs/*.c)
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# ASM sources
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ASMS_SOURCES = \
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$(wildcard ../SoC/demosoc/Common/Source/GCC/*.S)
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#######################################
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# binaries
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#######################################
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PREFIX = riscv-nuclei-elf-
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# The gcc compiler bin path can be either defined in make command via NUCLEI_TOOL_ROOT variable (> make NUCLEI_TOOL_ROOT=xxx)
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# either it can be added to the PATH environment variable.
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NUCLEI_RISCV_GCC_ROOT ?= $(NUCLEI_TOOL_ROOT)/gcc
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NUCLEI_OPENOCD_ROOT ?= $(NUCLEI_TOOL_ROOT)/openocd
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NUCLEI_TOOL_ROOT_EXIST = 0
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ifneq ($(wildcard $(NUCLEI_RISCV_GCC_ROOT)),)
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ifneq ($(wildcard $(NUCLEI_OPENOCD_ROOT)),)
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NUCLEI_TOOL_ROOT_EXIST = 1
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endif
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endif
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ifeq ($(NUCLEI_TOOL_ROOT_EXIST),1)
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CC = $(NUCLEI_RISCV_GCC_ROOT)/bin/$(PREFIX)gcc
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AS = $(NUCLEI_RISCV_GCC_ROOT)/bin/$(PREFIX)gcc -x assembler-with-cpp
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CP = $(NUCLEI_RISCV_GCC_ROOT)/bin/$(PREFIX)objcopy
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DP = $(NUCLEI_RISCV_GCC_ROOT)/bin/$(PREFIX)objdump
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SZ = $(NUCLEI_RISCV_GCC_ROOT)/bin/$(PREFIX)size
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GDB = $(NUCLEI_RISCV_GCC_ROOT)/bin/$(PREFIX)gdb
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OPENOCD := $(NUCLEI_OPENOCD_ROOT)/bin/openocd
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else
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CC = $(PREFIX)gcc
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AS = $(PREFIX)gcc -x assembler-with-cpp
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CP = $(PREFIX)objcopy
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DP = $(PREFIX)objdump
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SZ = $(PREFIX)size
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GDB = $(PREFIX)gdb
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OPENOCD := openocd
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endif
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HEX = $(CP) -O ihex
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BIN = $(CP) -O binary -S
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ECHO := echo
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OPENOCD_CFG := openocd_demosoc.cfg
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#######################################
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# CFLAGS
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#######################################
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#risc-v arch & abi
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CORE_ARCH_ABI = -march=rv32imafc -mabi=ilp32f
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#other flags
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OTHER_FLAGS += -g -mcmodel=medany -fno-common
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# macros for gcc
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# AS defines
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AS_DEFS = -DDOWNLOAD_MODE=DOWNLOAD_MODE_ILM
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# C defines
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C_DEFS = -DDOWNLOAD_MODE=DOWNLOAD_MODE_ILM
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# AS includes
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AS_INCLUDES =
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# C includes
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C_INCLUDES = \
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-I../OS_CONFIG \
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-I../Src \
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-I../SoC/demosoc/Board/nuclei_fpga_eval/Include \
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-I../SoC/demosoc/Common/Include \
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-I../SoC/demosoc/Common/Source/Stubs
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# compile gcc flags
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ASFLAGS = $(AS_DEFS) $(OPT) $(CORE_ARCH_ABI) $(OTHER_FLAGS) $(AS_INCLUDES) -Wall -fdata-sections -ffunction-sections
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CFLAGS = $(C_DEFS) $(C_INCLUDES) $(OPT) $(CORE_ARCH_ABI) $(OTHER_FLAGS) -Wall -fdata-sections -ffunction-sections
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# Generate dependency information
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CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)"
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# Set your GDB port using variable GDB_PORT
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GDB_PORT ?= 3333
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## Makefile Variable GDBREMOTE
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## You can change GDBREMOTE to other gdb remotes
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## eg. if you have started openocd server with (bindto 0.0.0.0 defined in openocd.cfg)
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## make sure your machine can connect to remote machine
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## in remote machine(ipaddr 192.168.43.199, port 3333) which connect the hardware board,
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## then you can change the GDBREMOTE to 192.168.43.199:3333
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## GDBREMOTE ?= 192.168.43.199:3333
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GDBREMOTE ?= | $(OPENOCD) --pipe -f $(OPENOCD_CFG)
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GDB_UPLOAD_ARGS ?= --batch
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GDB_UPLOAD_CMDS += -ex "monitor halt"
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GDB_UPLOAD_CMDS += -ex "monitor flash protect 0 0 last off"
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GDB_UPLOAD_CMDS += -ex "load"
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GDB_UPLOAD_CMDS += -ex "monitor resume"
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GDB_UPLOAD_CMDS += -ex "quit"
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OPENOCD_PORT_ARGS = -c "gdb_port $(GDB_PORT)"
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OPENOCD_ARGS += -f $(OPENOCD_CFG)
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GDB_CMDS += -ex "set remotetimeout 240"
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GDB_CMDS += -ex "target extended-remote localhost:$(GDB_PORT)"
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#######################################
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# LDFLAGS
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#######################################
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# link script
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LDSCRIPT = gcc_demosoc_ilm.ld
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# libraries
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LIBS = -lm
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LIBDIR =
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LDFLAGS = $(CORE_ARCH_ABI) $(OTHER_FLAGS) -specs=nano.specs -specs=nosys.specs -T $(LDSCRIPT) $(LIBDIR) $(LIBS) -nostartfiles -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections
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# default action: build all
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all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).dasm $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin
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include liteos_m.mk
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#######################################
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# build the application
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#######################################
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# list of objects
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OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o)))
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vpath %.c $(sort $(dir $(C_SOURCES)))
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# list of ASM program objects
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OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.S=.o)))
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vpath %.s $(sort $(dir $(ASM_SOURCES)))
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$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR)
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$(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@
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$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR)
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$(AS) -c $(CFLAGS) $(ASFLAGS) $< -o $@
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$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile $(LDSCRIPT)
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$(CC) $(OBJECTS) $(LDFLAGS) -o $@
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$(SZ) $@
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$(BUILD_DIR)/%.dasm: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
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$(DP) -D -S $< > $@
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$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
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$(HEX) $< $@
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$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
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$(BIN) $< $@
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$(BUILD_DIR):
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mkdir $@
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#######################################
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# clean up
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#######################################
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clean:
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-rm -fR $(BUILD_DIR)
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#######################################
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# upload & debug
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#######################################
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upload: $(BUILD_DIR)/$(TARGET).elf
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@$(ECHO) "Download and run $<"
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$(GDB) $< -ex "set remotetimeout 240" \
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-ex "target remote $(GDBREMOTE)" \
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$(GDB_UPLOAD_ARGS) $(GDB_UPLOAD_CMDS)
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debug: $(BUILD_DIR)/$(TARGET).elf
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@$(ECHO) "Download and debug $<"
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$(GDB) $< -ex "set remotetimeout 240" \
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-ex "target remote $(GDBREMOTE)"
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#######################################
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# dependencies
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#######################################
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-include $(wildcard $(BUILD_DIR)/*.d)
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# *** EOF ***
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@ -1,222 +0,0 @@
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/*
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* Copyright (c) 2019 Nuclei Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
|
|
||||||
* www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
|
||||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*/
|
|
||||||
/******************************************************************************
|
|
||||||
* @file gcc_demosoc_ilm.ld
|
|
||||||
* @brief GNU Linker Script for Nuclei N/NX based device in ilm Download Mode
|
|
||||||
* @version V1.0.0
|
|
||||||
* @date 17. Dec 2019
|
|
||||||
******************************************************************************/
|
|
||||||
OUTPUT_ARCH( "riscv" )
|
|
||||||
|
|
||||||
ENTRY( _start )
|
|
||||||
|
|
||||||
MEMORY
|
|
||||||
{
|
|
||||||
|
|
||||||
ilm (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64K
|
|
||||||
ram (wxa!ri) : ORIGIN = 0x90000000, LENGTH = 64K
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
SECTIONS
|
|
||||||
{
|
|
||||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 10K;
|
|
||||||
__heap_size = DEFINED(__heap_size) ? __heap_size : 10K;
|
|
||||||
|
|
||||||
.init :
|
|
||||||
{
|
|
||||||
*(.vtable)
|
|
||||||
KEEP (*(SORT_NONE(.init)))
|
|
||||||
} >ilm AT>ilm
|
|
||||||
|
|
||||||
.ilalign :
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
PROVIDE( _ilm_lma = . );
|
|
||||||
} >ilm AT>ilm
|
|
||||||
|
|
||||||
.ialign :
|
|
||||||
{
|
|
||||||
PROVIDE( _ilm = . );
|
|
||||||
} >ilm AT>ilm
|
|
||||||
|
|
||||||
.text :
|
|
||||||
{
|
|
||||||
*(.text.unlikely .text.unlikely.*)
|
|
||||||
*(.text.startup .text.startup.*)
|
|
||||||
*(.text .text.*)
|
|
||||||
*(.gnu.linkonce.t.*)
|
|
||||||
} >ilm AT>ilm
|
|
||||||
|
|
||||||
.rodata : ALIGN(4)
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
*(.rdata)
|
|
||||||
*(.rodata .rodata.*)
|
|
||||||
/* section information for initial. */
|
|
||||||
. = ALIGN(4);
|
|
||||||
__rt_init_start = .;
|
|
||||||
KEEP(*(SORT(.rti_fn*)))
|
|
||||||
__rt_init_end = .;
|
|
||||||
/* section information for finsh shell */
|
|
||||||
. = ALIGN(4);
|
|
||||||
__fsymtab_start = .;
|
|
||||||
KEEP(*(FSymTab))
|
|
||||||
__fsymtab_end = .;
|
|
||||||
. = ALIGN(4);
|
|
||||||
__vsymtab_start = .;
|
|
||||||
KEEP(*(VSymTab))
|
|
||||||
__vsymtab_end = .;
|
|
||||||
*(.gnu.linkonce.r.*)
|
|
||||||
|
|
||||||
} >ilm AT>ilm
|
|
||||||
|
|
||||||
.fini :
|
|
||||||
{
|
|
||||||
KEEP (*(SORT_NONE(.fini)))
|
|
||||||
} >ilm AT>ilm
|
|
||||||
|
|
||||||
. = ALIGN(4);
|
|
||||||
|
|
||||||
PROVIDE (__etext = .);
|
|
||||||
PROVIDE (_etext = .);
|
|
||||||
PROVIDE (etext = .);
|
|
||||||
PROVIDE( _eilm = . );
|
|
||||||
|
|
||||||
|
|
||||||
.preinit_array :
|
|
||||||
{
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
|
||||||
KEEP (*(.preinit_array))
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
|
||||||
} >ilm AT>ilm
|
|
||||||
|
|
||||||
.init_array :
|
|
||||||
{
|
|
||||||
PROVIDE_HIDDEN (__init_array_start = .);
|
|
||||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
|
||||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
|
||||||
PROVIDE_HIDDEN (__init_array_end = .);
|
|
||||||
} >ilm AT>ilm
|
|
||||||
|
|
||||||
.fini_array :
|
|
||||||
{
|
|
||||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
|
||||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
|
||||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
|
||||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
|
||||||
} >ilm AT>ilm
|
|
||||||
|
|
||||||
.ctors :
|
|
||||||
{
|
|
||||||
/* gcc uses crtbegin.o to find the start of
|
|
||||||
the constructors, so we make sure it is
|
|
||||||
first. Because this is a wildcard, it
|
|
||||||
doesn't matter if the user does not
|
|
||||||
actually link against crtbegin.o; the
|
|
||||||
linker won't look for a file to match a
|
|
||||||
wildcard. The wildcard also means that it
|
|
||||||
doesn't matter which directory crtbegin.o
|
|
||||||
is in. */
|
|
||||||
KEEP (*crtbegin.o(.ctors))
|
|
||||||
KEEP (*crtbegin?.o(.ctors))
|
|
||||||
/* We don't want to include the .ctor section from
|
|
||||||
the crtend.o file until after the sorted ctors.
|
|
||||||
The .ctor section from the crtend file contains the
|
|
||||||
end of ctors marker and it must be last */
|
|
||||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
|
||||||
KEEP (*(SORT(.ctors.*)))
|
|
||||||
KEEP (*(.ctors))
|
|
||||||
} >ilm AT>ilm
|
|
||||||
|
|
||||||
.dtors :
|
|
||||||
{
|
|
||||||
KEEP (*crtbegin.o(.dtors))
|
|
||||||
KEEP (*crtbegin?.o(.dtors))
|
|
||||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
|
||||||
KEEP (*(SORT(.dtors.*)))
|
|
||||||
KEEP (*(.dtors))
|
|
||||||
} >ilm AT>ilm
|
|
||||||
|
|
||||||
|
|
||||||
.lalign :
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
PROVIDE( _data_lma = . );
|
|
||||||
} >ilm AT>ilm
|
|
||||||
|
|
||||||
.dalign :
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
PROVIDE( _data = . );
|
|
||||||
} >ram AT>ilm
|
|
||||||
|
|
||||||
.data :
|
|
||||||
{
|
|
||||||
*(.data .data.*)
|
|
||||||
*(.gnu.linkonce.d.*)
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
|
||||||
*(.sdata .sdata.* .sdata*)
|
|
||||||
*(.gnu.linkonce.s.*)
|
|
||||||
. = ALIGN(8);
|
|
||||||
*(.srodata.cst16)
|
|
||||||
*(.srodata.cst8)
|
|
||||||
*(.srodata.cst4)
|
|
||||||
*(.srodata.cst2)
|
|
||||||
*(.srodata .srodata.*)
|
|
||||||
. = ALIGN(4);
|
|
||||||
__osdriv_start = .;
|
|
||||||
KEEP (*(osdriv))
|
|
||||||
__osdriv_end = .;
|
|
||||||
} >ram AT>ilm
|
|
||||||
|
|
||||||
. = ALIGN(4);
|
|
||||||
PROVIDE( _edata = . );
|
|
||||||
PROVIDE( edata = . );
|
|
||||||
|
|
||||||
PROVIDE( _fbss = . );
|
|
||||||
PROVIDE( __bss_start = . );
|
|
||||||
.bss :
|
|
||||||
{
|
|
||||||
*(.sbss*)
|
|
||||||
*(.gnu.linkonce.sb.*)
|
|
||||||
*(.bss .bss.*)
|
|
||||||
*(.gnu.linkonce.b.*)
|
|
||||||
*(COMMON)
|
|
||||||
. = ALIGN(4);
|
|
||||||
} >ram AT>ram
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE( end = . );
|
|
||||||
|
|
||||||
.stack : ALIGN(0x10)
|
|
||||||
{
|
|
||||||
. = __stack_size;
|
|
||||||
PROVIDE( _sp = . );
|
|
||||||
} >ram AT>ram
|
|
||||||
PROVIDE( _end = . );
|
|
||||||
.heap : ALIGN(0x10)
|
|
||||||
{
|
|
||||||
. = __heap_size;
|
|
||||||
PROVIDE( _heap_end = . );
|
|
||||||
PROVIDE( __los_heap_addr_start__ = . );
|
|
||||||
. = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram);
|
|
||||||
PROVIDE( __los_heap_addr_end__ = . );
|
|
||||||
} >ram AT>ram
|
|
||||||
}
|
|
||||||
|
|
@ -1,46 +0,0 @@
|
||||||
LITEOSTOPDIR := ../../../
|
|
||||||
LITEOSTOPDIR := $(realpath $(LITEOSTOPDIR))
|
|
||||||
|
|
||||||
# Common
|
|
||||||
C_SOURCES += $(wildcard $(LITEOSTOPDIR)/kernel/src/*.c) \
|
|
||||||
$(wildcard $(LITEOSTOPDIR)/kernel/src/mm/*.c) \
|
|
||||||
$(wildcard $(LITEOSTOPDIR)/components/cpup/*.c) \
|
|
||||||
$(wildcard $(LITEOSTOPDIR)/components/los_backtrace/*.c) \
|
|
||||||
$(wildcard $(LITEOSTOPDIR)/components/power/*.c) \
|
|
||||||
$(wildcard $(LITEOSTOPDIR)/utils/*.c)
|
|
||||||
|
|
||||||
C_INCLUDES += -I$(LITEOSTOPDIR)/utils \
|
|
||||||
-I$(LITEOSTOPDIR)/kernel/include \
|
|
||||||
-I$(LITEOSTOPDIR)/components/cpup \
|
|
||||||
-I$(LITEOSTOPDIR)/components/los_backtrace \
|
|
||||||
-I$(LITEOSTOPDIR)/components/power
|
|
||||||
|
|
||||||
#third party related
|
|
||||||
C_INCLUDES += -I$(LITEOSTOPDIR)/../../third_party/bounds_checking_function/include \
|
|
||||||
-I$(LITEOSTOPDIR)/../../third_party/bounds_checking_function/src
|
|
||||||
|
|
||||||
C_SOURCES += $(wildcard $(LITEOSTOPDIR)/../../third_party/bounds_checking_function/src/*.c)
|
|
||||||
|
|
||||||
# NMSIS related
|
|
||||||
C_INCLUDES += -I$(LITEOSTOPDIR)/arch/risc-v/nuclei/gcc/nmsis/Core/Include \
|
|
||||||
-I$(LITEOSTOPDIR)/arch/risc-v/nuclei/gcc/nmsis/DSP/Include \
|
|
||||||
-I$(LITEOSTOPDIR)/arch/risc-v/nuclei/gcc/nmsis/NN/Include
|
|
||||||
|
|
||||||
ASM_SOURCES += $(wildcard $(LITEOSTOPDIR)/arch/risc-v/nuclei/gcc/*.s)
|
|
||||||
|
|
||||||
ASMS_SOURCES += $(wildcard $(LITEOSTOPDIR)/arch/risc-v/nuclei/gcc/*.S)
|
|
||||||
|
|
||||||
C_SOURCES += $(wildcard $(LITEOSTOPDIR)/arch/risc-v/nuclei/gcc/*.c)
|
|
||||||
|
|
||||||
C_INCLUDES += -I. \
|
|
||||||
-I$(LITEOSTOPDIR)/arch/include \
|
|
||||||
-I$(LITEOSTOPDIR)/arch/risc-v/nuclei/gcc
|
|
||||||
|
|
||||||
ASFLAGS += -imacros $(LITEOSTOPDIR)/kernel/include/los_config.h -DCLZ=CLZ
|
|
||||||
|
|
||||||
# list of ASM .S program objects
|
|
||||||
OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASMS_SOURCES:.S=.o)))
|
|
||||||
vpath %.S $(sort $(dir $(ASMS_SOURCES)))
|
|
||||||
|
|
||||||
$(BUILD_DIR)/%.o: %.S Makefile | $(BUILD_DIR)
|
|
||||||
$(CC) -c $(CFLAGS) $(ASFLAGS) $< -o $@
|
|
||||||
|
|
@ -1,54 +0,0 @@
|
||||||
adapter_khz 1000
|
|
||||||
|
|
||||||
interface ftdi
|
|
||||||
ftdi_vid_pid 0x0403 0x6010
|
|
||||||
ftdi_oscan1_mode off
|
|
||||||
|
|
||||||
## bindto 0.0.0.0 can be used to cover all available interfaces.
|
|
||||||
## Uncomment bindto line to enable remote machine debug
|
|
||||||
# bindto 0.0.0.0
|
|
||||||
|
|
||||||
## If ftdi_device_desc not specified, the device description is ignored during device selection.
|
|
||||||
## So if you want to specify a dedicated FTDI device, you can select following device description:
|
|
||||||
## "Dual RS232-HS" is for Nuclei HummingBird Debugger V1
|
|
||||||
## "USB <-> JTAG-DEBUGGER" is for Nuclei HummingBird Debugger V2
|
|
||||||
## Uncomment one which match your device description
|
|
||||||
# ftdi_device_desc "Dual RS232-HS"
|
|
||||||
# ftdi_device_desc "USB <-> JTAG-DEBUGGER"
|
|
||||||
|
|
||||||
transport select jtag
|
|
||||||
|
|
||||||
ftdi_layout_init 0x0008 0x001b
|
|
||||||
ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
|
|
||||||
ftdi_layout_signal TCK -data 0x0001
|
|
||||||
ftdi_layout_signal TDI -data 0x0002
|
|
||||||
ftdi_layout_signal TDO -input 0x0004
|
|
||||||
ftdi_layout_signal TMS -data 0x0008
|
|
||||||
ftdi_layout_signal JTAG_SEL -data 0x0100 -oe 0x0100
|
|
||||||
|
|
||||||
set _CHIPNAME riscv
|
|
||||||
jtag newtap $_CHIPNAME cpu -irlen 5
|
|
||||||
|
|
||||||
set _TARGETNAME $_CHIPNAME.cpu
|
|
||||||
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
|
|
||||||
$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
|
|
||||||
|
|
||||||
set _FLASHNAME $_CHIPNAME.flash
|
|
||||||
flash bank $_FLASHNAME fespi 0x20000000 0 0 0 $_TARGETNAME
|
|
||||||
# Set the ILM space also as flash, to make sure it can be add breakpoint with hardware trigger
|
|
||||||
#flash bank onboard_ilm fespi 0x80000000 0 0 0 $_TARGETNAME
|
|
||||||
|
|
||||||
# Expose Nuclei self-defined CSRS
|
|
||||||
# See https://github.com/riscv/riscv-gnu-toolchain/issues/319#issuecomment-358397306
|
|
||||||
# Then user can view the csr register value in gdb using: info reg csr775 for CSR MTVT(0x307)
|
|
||||||
riscv expose_csrs 416-496,770-800,835-850,1227-1231,1483-1486,1984-2032,2064-2070,2370-2380,2490-2500,4032-4040
|
|
||||||
|
|
||||||
init
|
|
||||||
|
|
||||||
if {[ info exists pulse_srst]} {
|
|
||||||
ftdi_set_signal nSRST 0
|
|
||||||
ftdi_set_signal nSRST z
|
|
||||||
}
|
|
||||||
halt
|
|
||||||
# We must turn on this because otherwise the IDE version debug cannot download the program into flash
|
|
||||||
flash protect 0 0 last off
|
|
||||||
|
|
@ -1,122 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
|
||||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
|
||||||
* Copyright (c) 2021 Nuclei Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
* are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
|
||||||
* conditions and the following disclaimer.
|
|
||||||
*
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
|
||||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
|
||||||
* provided with the distribution.
|
|
||||||
*
|
|
||||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
|
||||||
* to endorse or promote products derived from this software without specific prior written
|
|
||||||
* permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
||||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
|
||||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
|
||||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
|
||||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
|
||||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
|
||||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
|
||||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
|
||||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
|
||||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**@defgroup los_config System configuration items
|
|
||||||
* @ingroup kernel
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _TARGET_CONFIG_H
|
|
||||||
#define _TARGET_CONFIG_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
#if __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif /* __cplusplus */
|
|
||||||
#endif /* __cplusplus */
|
|
||||||
|
|
||||||
#include "nuclei_sdk_soc.h"
|
|
||||||
|
|
||||||
/*=============================================================================
|
|
||||||
System clock module configuration
|
|
||||||
=============================================================================*/
|
|
||||||
#define OS_SYS_CLOCK SOC_TIMER_FREQ
|
|
||||||
#define LOSCFG_BASE_CORE_TICK_PER_SECOND (1000UL)
|
|
||||||
#define LOSCFG_BASE_CORE_TICK_HW_TIME 0
|
|
||||||
#define LOSCFG_BASE_CORE_TICK_WTIMER 1
|
|
||||||
/*=============================================================================
|
|
||||||
Hardware interrupt module configuration
|
|
||||||
=============================================================================*/
|
|
||||||
#define LOSCFG_PLATFORM_HWI 1
|
|
||||||
#define LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT 0
|
|
||||||
#define LOSCFG_PLATFORM_HWI_LIMIT 32
|
|
||||||
/*=============================================================================
|
|
||||||
Task module configuration
|
|
||||||
=============================================================================*/
|
|
||||||
#define LOSCFG_BASE_CORE_TSK_LIMIT 12
|
|
||||||
#define LOSCFG_BASE_CORE_TSK_IDLE_STACK_SIZE (0x500U)
|
|
||||||
#define LOSCFG_BASE_CORE_TSK_DEFAULT_STACK_SIZE (0x2E0U)
|
|
||||||
#define LOSCFG_BASE_CORE_TSK_MIN_STACK_SIZE (0x130U)
|
|
||||||
#define LOSCFG_BASE_CORE_TIMESLICE 1
|
|
||||||
#define LOSCFG_BASE_CORE_TIMESLICE_TIMEOUT 20000
|
|
||||||
#define LOSCFG_BASE_CORE_TICK_RESPONSE_MAX 0xFFFFFF
|
|
||||||
/*=============================================================================
|
|
||||||
Semaphore module configuration
|
|
||||||
=============================================================================*/
|
|
||||||
#define LOSCFG_BASE_IPC_SEM 1
|
|
||||||
#define LOSCFG_BASE_IPC_SEM_LIMIT 48
|
|
||||||
/*=============================================================================
|
|
||||||
Mutex module configuration
|
|
||||||
=============================================================================*/
|
|
||||||
#define LOSCFG_BASE_IPC_MUX 1
|
|
||||||
#define LOSCFG_BASE_IPC_MUX_LIMIT 10
|
|
||||||
/*=============================================================================
|
|
||||||
Queue module configuration
|
|
||||||
=============================================================================*/
|
|
||||||
#define LOSCFG_BASE_IPC_QUEUE 1
|
|
||||||
#define LOSCFG_BASE_IPC_QUEUE_LIMIT 6
|
|
||||||
/*=============================================================================
|
|
||||||
Software timer module configuration
|
|
||||||
=============================================================================*/
|
|
||||||
#define LOSCFG_BASE_CORE_SWTMR 1
|
|
||||||
#define LOSCFG_BASE_CORE_SWTMR_ALIGN 1
|
|
||||||
#define LOSCFG_BASE_CORE_SWTMR_LIMIT 6
|
|
||||||
/*=============================================================================
|
|
||||||
Memory module configuration
|
|
||||||
=============================================================================*/
|
|
||||||
#define LOSCFG_SYS_HEAP_SIZE 0x9000UL
|
|
||||||
#define OS_SYS_MEM_SIZE 0x2000UL
|
|
||||||
#define LOSCFG_BASE_MEM_NODE_INTEGRITY_CHECK 0
|
|
||||||
#define LOSCFG_BASE_MEM_NODE_SIZE_CHECK 1
|
|
||||||
#define LOSCFG_MEM_MUL_POOL 0
|
|
||||||
#define OS_SYS_MEM_NUM 20
|
|
||||||
#define LOSCFG_KERNEL_MEM_SLAB 0
|
|
||||||
/*=============================================================================
|
|
||||||
Exception module configuration
|
|
||||||
=============================================================================*/
|
|
||||||
#define LOSCFG_PLATFORM_EXC 0
|
|
||||||
/* =============================================================================
|
|
||||||
printf module configuration
|
|
||||||
============================================================================= */
|
|
||||||
#define LOSCFG_KERNEL_PRINTF 1
|
|
||||||
/* =============================================================================
|
|
||||||
enable backtrace
|
|
||||||
============================================================================= */
|
|
||||||
#define LOSCFG_BACKTRACE_TYPE 0
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
#if __cplusplus
|
|
||||||
}
|
|
||||||
#endif /* __cplusplus */
|
|
||||||
#endif /* __cplusplus */
|
|
||||||
|
|
||||||
|
|
||||||
#endif /* _TARGET_CONFIG_H */
|
|
||||||
|
|
@ -1,196 +0,0 @@
|
||||||
# Nuclei DDR200T开发板LiteOS使用说明
|
|
||||||
|
|
||||||
## Nuclei DDR200T开发板简介
|
|
||||||
|
|
||||||
Nuclei DDR200T开发板是一款集成了FPGA和通用MCU的RISC-V评估开发板。其中FPGA子系统采用Xilinx XC7A200T-2 FPGA芯片，提供板载FPGA JTAG下载器、丰富的板载存储（Flash,DDR,eMMC,EEPROM)、丰富的接口资源（数字、模拟）以及蜂鸟调试器接口。MCU子系统采用GD32VF103 MCU芯片，提供板载调试器以及JTAG调试接口。
|
|
||||||
|
|
||||||
开发板资料链接：
|
|
||||||
|
|
||||||
- [Nuclei DDR200T开发板详细介绍](https://www.nucleisys.com/upload/files/fpga/doc/Nuclei_FPGA_DebugKit_Intro_20201220.pdf)
|
|
||||||
- [Nuclei DDR200T开发板原理图](https://www.nucleisys.com/upload/files/fpga/doc/Nuclei_DDR200T.pdf)
|
|
||||||
|
|
||||||
## 文件结构
|
|
||||||
|
|
||||||
```
|
|
||||||
├── components # 可选组件
|
|
||||||
│ ├── cppsupport # C++支持
|
|
||||||
│ └── cpup # CPUP功能
|
|
||||||
├── kal # 内核抽象层
|
|
||||||
│ └── posix # posix标准接口支持
|
|
||||||
├── arch # 内核指令架构层代码
|
|
||||||
│ ├── risc-v # risc-v架构的代码
|
|
||||||
│ │ └── nuclei # nuclei内核相关代码
|
|
||||||
│ │ └── gcc # gcc编译器相关代码
|
|
||||||
│ │ └── nmsis # nmsis内核标准
|
|
||||||
│ └── include # 对外接口存放目录
|
|
||||||
│ ├── los_atomic.h # 定义通用arch的原子操作
|
|
||||||
│ ├── los_context.h # 定义通用arch的上下文切换
|
|
||||||
│ ├── los_arch.h # 定义通用arch初始化
|
|
||||||
│ └── los_interrupt.h # 定义通用arch中断
|
|
||||||
├── kernel # 内核最小功能集支持
|
|
||||||
│ ├── include # 对外接口存放目录
|
|
||||||
│ │ ├── los_config.h # 功能开关和配置参数
|
|
||||||
│ │ ├── los_event.h # 事件
|
|
||||||
│ │ ├── los_liteos.h # liteos最小功能集对外提供的头文件
|
|
||||||
│ │ ├── los_memory.h # 堆内存管理
|
|
||||||
│ │ ├── los_mutex.h # 互斥锁
|
|
||||||
│ │ ├── los_queue.h # 队列
|
|
||||||
│ │ ├── los_scheduler.h # 调度算法
|
|
||||||
│ │ ├── los_sem.h # 信号量
|
|
||||||
│ │ ├── los_task.h # 任务
|
|
||||||
│ │ └── los_timer.h # 定时器
|
|
||||||
│ └── src # 内核最小功能集源码
|
|
||||||
├── targets # 板级工程目录
|
|
||||||
│ └── riscv_nuclei_demo_soc_gcc # Nuclei DDR200T开发板相关代码
|
|
||||||
│ ├── GCC # 编译相关
|
|
||||||
│ ├── OS_CONFIG # 开发板配置功能开关和配置参数
|
|
||||||
│ ├── SoC # SOC相关代码
|
|
||||||
│ └── Src # application相关代码
|
|
||||||
└── utils # 通用公共目录
|
|
||||||
├── include
|
|
||||||
│ ├── los_compiler.h # 编译工具配置，类型定义
|
|
||||||
│ ├── los_debug.h # debug，printf相关
|
|
||||||
│ ├── los_error.h # 错误定义
|
|
||||||
│ └── los_list.h
|
|
||||||
└── src
|
|
||||||
```
|
|
||||||
|
|
||||||
## 使用说明
|
|
||||||
|
|
||||||
软件需求：linux环境
|
|
||||||
|
|
||||||
硬件需求：Nuclei DDR200T开发板
|
|
||||||
|
|
||||||
[环境配置](#sectionb1)
|
|
||||||
|
|
||||||
[编译源码](#sectionb2)
|
|
||||||
|
|
||||||
[下载调试、运行](#sectionb3)
|
|
||||||
|
|
||||||
本示例将新建并运行两个任务，可以在控制台查看任务执行打印信息。
|
|
||||||
|
|
||||||
### 环境配置<a name="sectionb1"></a>
|
|
||||||
|
|
||||||
- **工具链配置**
|
|
||||||
|
|
||||||
请先确认您使用的是centos系统或Ubuntu 64bit。
|
|
||||||
|
|
||||||
1. 新建一个`Nuclei` 文件夹，比如`~/home/Nuclei`
|
|
||||||
2. 参考下图，从[Nuclei Download Center](https://nucleisys.com/download.php)下载工具链和OpenOCD。
|
|
||||||
- CentOS或Ubuntu系统请点击图中红框1下载RISC-V GNU工具链
|
|
||||||
- 点击图中蓝框2-1下载64bit的OpenOCD
|
|
||||||
- **确保Make工具版本不低于3.82**: ubuntu系统使用`sudo apt-get install make`指令安装`make`工具, CentOS系统使用`sudo yum install make`指令安装。
|
|
||||||
|
|
||||||
图1 Linux环境要下载的Nuclei Tools
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
3. 在之前新建的`Nuclei`文件夹中新建`gcc`文件夹和`openocd`文件夹。
|
|
||||||
- 解压缩之前下载的**gnu工具链**到任意文件夹中，复制其中`bin`文件件所在层级的所有内容到`gcc`文件夹中。
|
|
||||||
- 同样解压缩之前下载的**OpenOCD**到任意文件夹中，复制其中`bin`文件件所在层级的所有内容到`openocd`文件夹中。
|
|
||||||
|
|
||||||
> 注意：
|
|
||||||
>
|
|
||||||
> 请务必下载并解压缩Linux版本的工具，不要下载windows版本工具。
|
|
||||||
|
|
||||||
- **驱动配置**
|
|
||||||
|
|
||||||
驱动配置步骤如下：
|
|
||||||
|
|
||||||
1. 连接开发板到Linux中，确保USB被Linux识别出来。
|
|
||||||
|
|
||||||
2. 在控制台中使用lsusb指令查看信息，参考的打印信息如下：
|
|
||||||
|
|
||||||
```
|
|
||||||
Bus 001 Device 010: ID 0403:6010 Future Technology Devices International, Ltd FT2232xxxx
|
|
||||||
```
|
|
||||||
|
|
||||||
3. 将github（https://github.com/riscv-mcu/ses_nuclei_sdk_projects/blob/master/misc/99-openocd.rules）上misc文件夹内99-openocd.rules文件复制到当前路径下，控制台中输入sudo cp 99-openocd.rules /etc/udev/rules.d/99-openocd.rules指令复制文件到指定路径下。
|
|
||||||
|
|
||||||
4. 断开调试器再重新连接到Linux系统中。
|
|
||||||
|
|
||||||
5. 使用ls /dev/ttyUSB*命令查看ttyUSB信息，参考输出如下：
|
|
||||||
|
|
||||||
```
|
|
||||||
/dev/ttyUSB0 /dev/ttyUSB1
|
|
||||||
```
|
|
||||||
|
|
||||||
6. 使用ls -l /dev/ttyUSB1命令查看分组信息，参考输出如下:
|
|
||||||
|
|
||||||
```
|
|
||||||
crw-rw-r-- 1 root plugdev 188, 1 Nov 28 12:53 /dev/ttyUSB1
|
|
||||||
```
|
|
||||||
|
|
||||||
可以看到ttyUSB1已经加入plugdev组，接下来我们要将自己添加到plugdev组。使用whoami命令查看当前用户名，我们将其记录为\< your_user_name >。
|
|
||||||
|
|
||||||
7. 使用sudo usermod -a -G plugdev \<your_user_name>命令将自己添加进plugdev组。
|
|
||||||
|
|
||||||
8. 再次确认当前用户名已属于plugdev组，使用groups命令，可以看到打印信息中有plugdev即成功将当前用户添加至plugdev组。
|
|
||||||
|
|
||||||
### 编译源码<a name="sectionb2"></a>
|
|
||||||
|
|
||||||
使用`git clone`复制代码到任意目录下，打开进入到工程根目录下，输入`git submodule update --init --recursive`下载更新子模块。
|
|
||||||
|
|
||||||
编译前请在当前控制台中配置`NUCLEI_TOOL_ROOT`路径，假设`Nuclei`文件夹所在路径为`/home/Nuclei`，输入`export NUCLEI_TOOL_ROOT=/home/Nuclei` 。或者使用时make选项增加`NUCLEI_TOOL_ROOT=/home/Nuclei`。
|
|
||||||
|
|
||||||
配置路径后打开至代码根目录下的/target/riscv_nuclei_demo_soc_gcc/GCC位置，输入如下指令开始编译：
|
|
||||||
|
|
||||||
```
|
|
||||||
make all
|
|
||||||
```
|
|
||||||
|
|
||||||
编译结束后部分参考输出如下：
|
|
||||||
|
|
||||||
```
|
|
||||||
text data bss dec hex filename
|
|
||||||
21900 112 65426 87438 1558e build/Nuclei-demo-soc.elf
|
|
||||||
```
|
|
||||||
|
|
||||||
若编译前想清理工程，请使用如下指令：
|
|
||||||
|
|
||||||
```
|
|
||||||
make clean
|
|
||||||
```
|
|
||||||
|
|
||||||
### 下载调试、运行<a name="sectionb3"></a>
|
|
||||||
|
|
||||||
调试或运行前请先是用蜂鸟调试器连接Nuclei DDR200T开发板，确保已按照[环境配置](#sectionb1)中驱动配置部分配置完成。
|
|
||||||
|
|
||||||
同样配置好`NUCLEI_TOOL_ROOT`路径并打开至代码根目录下的/target/riscv_nuclei_demo_soc_gcc/GCC位置，输入如下指令进入GDB调试：
|
|
||||||
|
|
||||||
```
|
|
||||||
make debug
|
|
||||||
```
|
|
||||||
|
|
||||||
等待到进入GDB调试界面时，输入`load`指令下载编译好的elf文件，就可以开始调试。
|
|
||||||
|
|
||||||
若想直接运行，请在调试时所在位置输入如下指令：
|
|
||||||
|
|
||||||
```
|
|
||||||
make upload
|
|
||||||
```
|
|
||||||
|
|
||||||
运行时可以查看串口打印内容，使用串口查看工具，这里以`minicom`为例，若未安装此工具可自行安装或使用其他串口查看工具。打开控制台，输入`minicom -D /dev/ttyUSB1 -b 115200`指令打开串口查看工具。
|
|
||||||
|
|
||||||
运行时参考输出如下：
|
|
||||||
|
|
||||||
```
|
|
||||||
Nuclei SDK Build Time: Mar 31 2021, 03:29:57
|
|
||||||
Download Mode: ILM
|
|
||||||
CPU Frequency 7998996 Hz
|
|
||||||
entering kernel init...
|
|
||||||
TaskSampleEntry1 running...
|
|
||||||
TaskSampleEntry1 running...
|
|
||||||
TaskSampleEntry1 running...
|
|
||||||
TaskSampleEntry1 running...
|
|
||||||
TaskSampleEntry2 running...
|
|
||||||
TaskSampleEntry1 running...
|
|
||||||
TaskSampleEntry1 running...
|
|
||||||
TaskSampleEntry1 running...
|
|
||||||
TaskSampleEntry1 running...
|
|
||||||
TaskSampleEntry1 running...
|
|
||||||
TaskSampleEntry2 running...
|
|
||||||
TaskSampleEntry1 running...
|
|
||||||
```
|
|
||||||
|
|
@ -1,37 +0,0 @@
|
||||||
// See LICENSE for license details.
|
|
||||||
#ifndef _BOARD_NUCLEI_FPGA_EVAL_H_
|
|
||||||
#define _BOARD_NUCLEI_FPGA_EVAL_H_
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#include "nuclei_sdk_soc.h"
|
|
||||||
|
|
||||||
|
|
||||||
// Interrupt Numbers
|
|
||||||
#define SOC_BUTTON_1_IRQn SOC_INT49_IRQn
|
|
||||||
#define SOC_BUTTON_2_IRQn SOC_INT50_IRQn
|
|
||||||
// Interrupt Handler Definitions
|
|
||||||
#define SOC_BUTTON_1_HANDLER eclic_irq49_handler
|
|
||||||
#define SOC_BUTTON_2_HANDLER eclic_irq50_handler
|
|
||||||
// GPIO Bit Offset
|
|
||||||
#define SOC_LED_RED_GPIO_OFS 19
|
|
||||||
#define SOC_LED_GREEN_GPIO_OFS 21
|
|
||||||
#define SOC_LED_BLUE_GPIO_OFS 22
|
|
||||||
#define SOC_BUTTON_1_GPIO_OFS 30
|
|
||||||
#define SOC_BUTTON_2_GPIO_OFS 31
|
|
||||||
|
|
||||||
// GPIO Bit Mask
|
|
||||||
#define SOC_LED_RED_GPIO_MASK (1<<SOC_LED_RED_GPIO_OFS)
|
|
||||||
#define SOC_LED_GREEN_GPIO_MASK (1<<SOC_LED_GREEN_GPIO_OFS)
|
|
||||||
#define SOC_LED_BLUE_GPIO_MASK (1<<SOC_LED_BLUE_GPIO_OFS)
|
|
||||||
#define SOC_BUTTON_1_GPIO_MASK (1<<SOC_BUTTON_1_GPIO_OFS)
|
|
||||||
#define SOC_BUTTON_2_GPIO_MASK (1<<SOC_BUTTON_2_GPIO_OFS)
|
|
||||||
#define SOC_BUTTON_GPIO_MASK (SOC_BUTTON_1_GPIO_MASK | SOC_BUTTON_2_GPIO_MASK)
|
|
||||||
#define SOC_LED_GPIO_MASK (SOC_LED_RED_GPIO_MASK | SOC_LED_GREEN_GPIO_MASK | SOC_LED_BLUE_GPIO_MASK)
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,20 +0,0 @@
|
||||||
// See LICENSE for license details.
|
|
||||||
#ifndef _NUCLEI_SDK_HAL_H
|
|
||||||
#define _NUCLEI_SDK_HAL_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#include "board_nuclei_fpga_eval.h"
|
|
||||||
|
|
||||||
#define SOC_DEBUG_UART UART0
|
|
||||||
|
|
||||||
#ifndef NUCLEI_BANNER
|
|
||||||
#define NUCLEI_BANNER 1
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,211 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2019 Nuclei Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
|
||||||
* not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
|
||||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*/
|
|
||||||
/******************************************************************************
|
|
||||||
* @file gcc_demosoc_ddr.ld
|
|
||||||
* @brief GNU Linker Script for Nuclei N/NX based device in ddr Download Mode
|
|
||||||
* @version V1.0.0
|
|
||||||
* @date 20. Jul 2020
|
|
||||||
******************************************************************************/
|
|
||||||
OUTPUT_ARCH( "riscv" )
|
|
||||||
|
|
||||||
ENTRY( _start )
|
|
||||||
|
|
||||||
MEMORY
|
|
||||||
{
|
|
||||||
/* Emulate ROM using DDR */
|
|
||||||
rom (rxai!w) : ORIGIN = 0xA0000000, LENGTH = 32M
|
|
||||||
/* Emulate RAM using DDR */
|
|
||||||
ram (wxa!ri) : ORIGIN = 0xA2000000, LENGTH = 32M
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
SECTIONS
|
|
||||||
{
|
|
||||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
|
||||||
|
|
||||||
.init :
|
|
||||||
{
|
|
||||||
*(.vtable)
|
|
||||||
KEEP (*(SORT_NONE(.init)))
|
|
||||||
} >rom AT>rom
|
|
||||||
|
|
||||||
.ilalign :
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
PROVIDE( _ilm_lma = . );
|
|
||||||
} >rom AT>rom
|
|
||||||
|
|
||||||
.ialign :
|
|
||||||
{
|
|
||||||
PROVIDE( _ilm = . );
|
|
||||||
} >rom AT>rom
|
|
||||||
|
|
||||||
.text :
|
|
||||||
{
|
|
||||||
*(.text.unlikely .text.unlikely.*)
|
|
||||||
*(.text.startup .text.startup.*)
|
|
||||||
*(.text .text.*)
|
|
||||||
*(.gnu.linkonce.t.*)
|
|
||||||
} >rom AT>rom
|
|
||||||
|
|
||||||
.rodata : ALIGN(4)
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
*(.rdata)
|
|
||||||
*(.rodata .rodata.*)
|
|
||||||
/* section information for initial. */
|
|
||||||
. = ALIGN(4);
|
|
||||||
__rt_init_start = .;
|
|
||||||
KEEP(*(SORT(.rti_fn*)))
|
|
||||||
__rt_init_end = .;
|
|
||||||
/* section information for finsh shell */
|
|
||||||
. = ALIGN(4);
|
|
||||||
__fsymtab_start = .;
|
|
||||||
KEEP(*(FSymTab))
|
|
||||||
__fsymtab_end = .;
|
|
||||||
. = ALIGN(4);
|
|
||||||
__vsymtab_start = .;
|
|
||||||
KEEP(*(VSymTab))
|
|
||||||
__vsymtab_end = .;
|
|
||||||
*(.gnu.linkonce.r.*)
|
|
||||||
|
|
||||||
} >rom AT>rom
|
|
||||||
|
|
||||||
.fini :
|
|
||||||
{
|
|
||||||
KEEP (*(SORT_NONE(.fini)))
|
|
||||||
} >rom AT>rom
|
|
||||||
|
|
||||||
. = ALIGN(4);
|
|
||||||
|
|
||||||
PROVIDE (__etext = .);
|
|
||||||
PROVIDE (_etext = .);
|
|
||||||
PROVIDE (etext = .);
|
|
||||||
PROVIDE( _eilm = . );
|
|
||||||
|
|
||||||
|
|
||||||
.preinit_array :
|
|
||||||
{
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
|
||||||
KEEP (*(.preinit_array))
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
|
||||||
} >rom AT>rom
|
|
||||||
|
|
||||||
.init_array :
|
|
||||||
{
|
|
||||||
PROVIDE_HIDDEN (__init_array_start = .);
|
|
||||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
|
||||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
|
||||||
PROVIDE_HIDDEN (__init_array_end = .);
|
|
||||||
} >rom AT>rom
|
|
||||||
|
|
||||||
.fini_array :
|
|
||||||
{
|
|
||||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
|
||||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
|
||||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
|
||||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
|
||||||
} >rom AT>rom
|
|
||||||
|
|
||||||
.ctors :
|
|
||||||
{
|
|
||||||
/* gcc uses crtbegin.o to find the start of
|
|
||||||
the constructors, so we make sure it is
|
|
||||||
first. Because this is a wildcard, it
|
|
||||||
doesn't matter if the user does not
|
|
||||||
actually link against crtbegin.o; the
|
|
||||||
linker won't look for a file to match a
|
|
||||||
wildcard. The wildcard also means that it
|
|
||||||
doesn't matter which directory crtbegin.o
|
|
||||||
is in. */
|
|
||||||
KEEP (*crtbegin.o(.ctors))
|
|
||||||
KEEP (*crtbegin?.o(.ctors))
|
|
||||||
/* We don't want to include the .ctor section from
|
|
||||||
the crtend.o file until after the sorted ctors.
|
|
||||||
The .ctor section from the crtend file contains the
|
|
||||||
end of ctors marker and it must be last */
|
|
||||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
|
||||||
KEEP (*(SORT(.ctors.*)))
|
|
||||||
KEEP (*(.ctors))
|
|
||||||
} >rom AT>rom
|
|
||||||
|
|
||||||
.dtors :
|
|
||||||
{
|
|
||||||
KEEP (*crtbegin.o(.dtors))
|
|
||||||
KEEP (*crtbegin?.o(.dtors))
|
|
||||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
|
||||||
KEEP (*(SORT(.dtors.*)))
|
|
||||||
KEEP (*(.dtors))
|
|
||||||
} >rom AT>rom
|
|
||||||
|
|
||||||
|
|
||||||
.lalign :
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
PROVIDE( _data_lma = . );
|
|
||||||
} >rom AT>rom
|
|
||||||
|
|
||||||
.dalign :
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
PROVIDE( _data = . );
|
|
||||||
} >ram AT>rom
|
|
||||||
|
|
||||||
.data :
|
|
||||||
{
|
|
||||||
*(.data .data.*)
|
|
||||||
*(.gnu.linkonce.d.*)
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
|
||||||
*(.sdata .sdata.* .sdata*)
|
|
||||||
*(.gnu.linkonce.s.*)
|
|
||||||
. = ALIGN(8);
|
|
||||||
*(.srodata.cst16)
|
|
||||||
*(.srodata.cst8)
|
|
||||||
*(.srodata.cst4)
|
|
||||||
*(.srodata.cst2)
|
|
||||||
*(.srodata .srodata.*)
|
|
||||||
} >ram AT>rom
|
|
||||||
|
|
||||||
. = ALIGN(4);
|
|
||||||
PROVIDE( _edata = . );
|
|
||||||
PROVIDE( edata = . );
|
|
||||||
|
|
||||||
PROVIDE( _fbss = . );
|
|
||||||
PROVIDE( __bss_start = . );
|
|
||||||
.bss :
|
|
||||||
{
|
|
||||||
*(.sbss*)
|
|
||||||
*(.gnu.linkonce.sb.*)
|
|
||||||
*(.bss .bss.*)
|
|
||||||
*(.gnu.linkonce.b.*)
|
|
||||||
*(COMMON)
|
|
||||||
. = ALIGN(4);
|
|
||||||
} >ram AT>ram
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE( _end = . );
|
|
||||||
PROVIDE( end = . );
|
|
||||||
|
|
||||||
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
|
|
||||||
{
|
|
||||||
PROVIDE( _heap_end = . );
|
|
||||||
. = __stack_size;
|
|
||||||
PROVIDE( _sp = . );
|
|
||||||
} >ram AT>ram
|
|
||||||
}
|
|
||||||
|
|
@ -1,209 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2019 Nuclei Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
|
||||||
* not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
|
||||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*/
|
|
||||||
/******************************************************************************
|
|
||||||
* @file gcc_demosoc_flash.ld
|
|
||||||
* @brief GNU Linker Script for Nuclei N/NX based device in flash Download Mode
|
|
||||||
* @version V1.0.0
|
|
||||||
* @date 17. Dec 2019
|
|
||||||
******************************************************************************/
|
|
||||||
OUTPUT_ARCH( "riscv" )
|
|
||||||
|
|
||||||
ENTRY( _start )
|
|
||||||
|
|
||||||
MEMORY
|
|
||||||
{
|
|
||||||
flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 4M
|
|
||||||
ilm (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64K
|
|
||||||
ram (wxa!ri) : ORIGIN = 0x90000000, LENGTH = 64K
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
SECTIONS
|
|
||||||
{
|
|
||||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
|
||||||
|
|
||||||
.init :
|
|
||||||
{
|
|
||||||
KEEP (*(SORT_NONE(.init)))
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
.ilalign :
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
PROVIDE( _ilm_lma = . );
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
.ialign :
|
|
||||||
{
|
|
||||||
PROVIDE( _ilm = . );
|
|
||||||
} >ilm AT>flash
|
|
||||||
|
|
||||||
.text :
|
|
||||||
{
|
|
||||||
*(.vtable_ilm)
|
|
||||||
*(.text.unlikely .text.unlikely.*)
|
|
||||||
*(.text.startup .text.startup.*)
|
|
||||||
*(.text .text.*)
|
|
||||||
*(.gnu.linkonce.t.*)
|
|
||||||
} >ilm AT>flash
|
|
||||||
|
|
||||||
.rodata : ALIGN(4)
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
} >ilm AT>flash
|
|
||||||
|
|
||||||
.fini :
|
|
||||||
{
|
|
||||||
KEEP (*(SORT_NONE(.fini)))
|
|
||||||
} >ilm AT>flash
|
|
||||||
|
|
||||||
. = ALIGN(4);
|
|
||||||
|
|
||||||
PROVIDE (__etext = .);
|
|
||||||
PROVIDE (_etext = .);
|
|
||||||
PROVIDE (etext = .);
|
|
||||||
PROVIDE( _eilm = . );
|
|
||||||
|
|
||||||
.preinit_array :
|
|
||||||
{
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
|
||||||
KEEP (*(.preinit_array))
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
.init_array :
|
|
||||||
{
|
|
||||||
PROVIDE_HIDDEN (__init_array_start = .);
|
|
||||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
|
||||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
|
||||||
PROVIDE_HIDDEN (__init_array_end = .);
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
.fini_array :
|
|
||||||
{
|
|
||||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
|
||||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
|
||||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
|
||||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
.ctors :
|
|
||||||
{
|
|
||||||
/* gcc uses crtbegin.o to find the start of
|
|
||||||
the constructors, so we make sure it is
|
|
||||||
first. Because this is a wildcard, it
|
|
||||||
doesn't matter if the user does not
|
|
||||||
actually link against crtbegin.o; the
|
|
||||||
linker won't look for a file to match a
|
|
||||||
wildcard. The wildcard also means that it
|
|
||||||
doesn't matter which directory crtbegin.o
|
|
||||||
is in. */
|
|
||||||
KEEP (*crtbegin.o(.ctors))
|
|
||||||
KEEP (*crtbegin?.o(.ctors))
|
|
||||||
/* We don't want to include the .ctor section from
|
|
||||||
the crtend.o file until after the sorted ctors.
|
|
||||||
The .ctor section from the crtend file contains the
|
|
||||||
end of ctors marker and it must be last */
|
|
||||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
|
||||||
KEEP (*(SORT(.ctors.*)))
|
|
||||||
KEEP (*(.ctors))
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
.dtors :
|
|
||||||
{
|
|
||||||
KEEP (*crtbegin.o(.dtors))
|
|
||||||
KEEP (*crtbegin?.o(.dtors))
|
|
||||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
|
||||||
KEEP (*(SORT(.dtors.*)))
|
|
||||||
KEEP (*(.dtors))
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
|
|
||||||
.lalign :
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
PROVIDE( _data_lma = . );
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
.dalign :
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
PROVIDE( _data = . );
|
|
||||||
} >ram AT>flash
|
|
||||||
|
|
||||||
.data :
|
|
||||||
{
|
|
||||||
*(.data .data.*)
|
|
||||||
*(.gnu.linkonce.d.*)
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
|
||||||
*(.sdata .sdata.* .sdata*)
|
|
||||||
*(.gnu.linkonce.s.*)
|
|
||||||
. = ALIGN(8);
|
|
||||||
*(.srodata.cst16)
|
|
||||||
*(.srodata.cst8)
|
|
||||||
*(.srodata.cst4)
|
|
||||||
*(.srodata.cst2)
|
|
||||||
*(.srodata .srodata.*)
|
|
||||||
. = ALIGN(4);
|
|
||||||
*(.rdata)
|
|
||||||
*(.rodata .rodata.*)
|
|
||||||
/* section information for initial. */
|
|
||||||
. = ALIGN(4);
|
|
||||||
__rt_init_start = .;
|
|
||||||
KEEP(*(SORT(.rti_fn*)))
|
|
||||||
__rt_init_end = .;
|
|
||||||
/* section information for finsh shell */
|
|
||||||
. = ALIGN(4);
|
|
||||||
__fsymtab_start = .;
|
|
||||||
KEEP(*(FSymTab))
|
|
||||||
__fsymtab_end = .;
|
|
||||||
. = ALIGN(4);
|
|
||||||
__vsymtab_start = .;
|
|
||||||
KEEP(*(VSymTab))
|
|
||||||
__vsymtab_end = .;
|
|
||||||
*(.gnu.linkonce.r.*)
|
|
||||||
} >ram AT>flash
|
|
||||||
|
|
||||||
. = ALIGN(4);
|
|
||||||
PROVIDE( _edata = . );
|
|
||||||
PROVIDE( edata = . );
|
|
||||||
|
|
||||||
PROVIDE( _fbss = . );
|
|
||||||
PROVIDE( __bss_start = . );
|
|
||||||
.bss :
|
|
||||||
{
|
|
||||||
*(.sbss*)
|
|
||||||
*(.gnu.linkonce.sb.*)
|
|
||||||
*(.bss .bss.*)
|
|
||||||
*(.gnu.linkonce.b.*)
|
|
||||||
*(COMMON)
|
|
||||||
. = ALIGN(4);
|
|
||||||
} >ram AT>ram
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE( _end = . );
|
|
||||||
PROVIDE( end = . );
|
|
||||||
|
|
||||||
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
|
|
||||||
{
|
|
||||||
PROVIDE( _heap_end = . );
|
|
||||||
. = __stack_size;
|
|
||||||
PROVIDE( _sp = . );
|
|
||||||
} >ram AT>ram
|
|
||||||
}
|
|
||||||
|
|
@ -1,284 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2019 Nuclei Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
|
||||||
* not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
|
||||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*/
|
|
||||||
/******************************************************************************
|
|
||||||
* @file gcc_demosoc_flashxip.ld
|
|
||||||
* @brief GNU Linker Script for Nuclei N/NX based device in flashxip Download Mode
|
|
||||||
* @version V1.0.0
|
|
||||||
* @date 17. Dec 2019
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*********** Use Configuration Wizard in Context Menu *************************/
|
|
||||||
|
|
||||||
OUTPUT_ARCH( "riscv" )
|
|
||||||
/********************* Flash Configuration ************************************
|
|
||||||
* <h> Flash Configuration
|
|
||||||
* <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
|
|
||||||
* <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
|
||||||
* </h>
|
|
||||||
*/
|
|
||||||
__ROM_BASE = 0x20000000;
|
|
||||||
__ROM_SIZE = 0x00400000;
|
|
||||||
|
|
||||||
/*--------------------- ILM RAM Configuration ---------------------------
|
|
||||||
* <h> ILM RAM Configuration
|
|
||||||
* <o0> ILM RAM Base Address <0x0-0xFFFFFFFF:8>
|
|
||||||
* <o1> ILM RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
|
||||||
* </h>
|
|
||||||
*/
|
|
||||||
__ILM_RAM_BASE = 0x80000000;
|
|
||||||
__ILM_RAM_SIZE = 0x00010000;
|
|
||||||
|
|
||||||
/*--------------------- Embedded RAM Configuration ---------------------------
|
|
||||||
* <h> RAM Configuration
|
|
||||||
* <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
|
|
||||||
* <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
|
||||||
* </h>
|
|
||||||
*/
|
|
||||||
__RAM_BASE = 0x90000000;
|
|
||||||
__RAM_SIZE = 0x00010000;
|
|
||||||
|
|
||||||
/********************* Stack / Heap Configuration ****************************
|
|
||||||
* <h> Stack / Heap Configuration
|
|
||||||
* <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
|
||||||
* <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
|
||||||
* </h>
|
|
||||||
*/
|
|
||||||
__STACK_SIZE = 0x00000800;
|
|
||||||
__HEAP_SIZE = 0x00000800;
|
|
||||||
|
|
||||||
/**************************** end of configuration section ********************/
|
|
||||||
|
|
||||||
/* Define base address and length of flash and ram */
|
|
||||||
MEMORY
|
|
||||||
{
|
|
||||||
flash (rxai!w) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
|
|
||||||
ram (wxa!ri) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
|
|
||||||
}
|
|
||||||
/* Linker script to place sections and symbol values. Should be used together
|
|
||||||
* with other linker script that defines memory regions FLASH,ILM and RAM.
|
|
||||||
* It references following symbols, which must be defined in code:
|
|
||||||
* _Start : Entry of reset handler
|
|
||||||
*
|
|
||||||
* It defines following symbols, which code can use without definition:
|
|
||||||
* _ilm_lma
|
|
||||||
* _ilm
|
|
||||||
* __etext
|
|
||||||
* _etext
|
|
||||||
* etext
|
|
||||||
* _eilm
|
|
||||||
* __preinit_array_start
|
|
||||||
* __preinit_array_end
|
|
||||||
* __init_array_start
|
|
||||||
* __init_array_end
|
|
||||||
* __fini_array_start
|
|
||||||
* __fini_array_end
|
|
||||||
* _data_lma
|
|
||||||
* _edata
|
|
||||||
* edata
|
|
||||||
* __data_end__
|
|
||||||
* __bss_start
|
|
||||||
* __fbss
|
|
||||||
* _end
|
|
||||||
* end
|
|
||||||
* __heap_end
|
|
||||||
* __StackLimit
|
|
||||||
* __StackTop
|
|
||||||
* __STACK_SIZE
|
|
||||||
*/
|
|
||||||
/* Define entry label of program */
|
|
||||||
ENTRY(_start)
|
|
||||||
SECTIONS
|
|
||||||
{
|
|
||||||
__STACK_SIZE = DEFINED(__STACK_SIZE) ? __STACK_SIZE : 2K;
|
|
||||||
|
|
||||||
.init :
|
|
||||||
{
|
|
||||||
/* vector table locate at flash */
|
|
||||||
*(.vtable)
|
|
||||||
KEEP (*(SORT_NONE(.init)))
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
.ilalign :
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
/* Create a section label as _ilm_lma which located at flash */
|
|
||||||
PROVIDE( _ilm_lma = . );
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
.ialign :
|
|
||||||
{
|
|
||||||
/* Create a section label as _ilm which located at flash */
|
|
||||||
PROVIDE( _ilm = . );
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
/* Code section located at flash */
|
|
||||||
.text :
|
|
||||||
{
|
|
||||||
*(.text.unlikely .text.unlikely.*)
|
|
||||||
*(.text.startup .text.startup.*)
|
|
||||||
*(.text .text.*)
|
|
||||||
*(.gnu.linkonce.t.*)
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
.rodata : ALIGN(4)
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
*(.rdata)
|
|
||||||
*(.rodata .rodata.*)
|
|
||||||
/* section information for initial. */
|
|
||||||
. = ALIGN(4);
|
|
||||||
__rt_init_start = .;
|
|
||||||
KEEP(*(SORT(.rti_fn*)))
|
|
||||||
__rt_init_end = .;
|
|
||||||
/* section information for finsh shell */
|
|
||||||
. = ALIGN(4);
|
|
||||||
__fsymtab_start = .;
|
|
||||||
KEEP(*(FSymTab))
|
|
||||||
__fsymtab_end = .;
|
|
||||||
. = ALIGN(4);
|
|
||||||
__vsymtab_start = .;
|
|
||||||
KEEP(*(VSymTab))
|
|
||||||
__vsymtab_end = .;
|
|
||||||
*(.gnu.linkonce.r.*)
|
|
||||||
. = ALIGN(8);
|
|
||||||
*(.srodata.cst16)
|
|
||||||
*(.srodata.cst8)
|
|
||||||
*(.srodata.cst4)
|
|
||||||
*(.srodata.cst2)
|
|
||||||
*(.srodata .srodata.*)
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
.fini :
|
|
||||||
{
|
|
||||||
KEEP (*(SORT_NONE(.fini)))
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
. = ALIGN(4);
|
|
||||||
|
|
||||||
PROVIDE (__etext = .);
|
|
||||||
PROVIDE (_etext = .);
|
|
||||||
PROVIDE (etext = .);
|
|
||||||
PROVIDE( _eilm = . );
|
|
||||||
|
|
||||||
|
|
||||||
.preinit_array :
|
|
||||||
{
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
|
||||||
KEEP (*(.preinit_array))
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
.init_array :
|
|
||||||
{
|
|
||||||
PROVIDE_HIDDEN (__init_array_start = .);
|
|
||||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
|
||||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
|
||||||
PROVIDE_HIDDEN (__init_array_end = .);
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
.fini_array :
|
|
||||||
{
|
|
||||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
|
||||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
|
||||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
|
||||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
.ctors :
|
|
||||||
{
|
|
||||||
/* gcc uses crtbegin.o to find the start of
|
|
||||||
* the constructors, so we make sure it is
|
|
||||||
* first. Because this is a wildcard, it
|
|
||||||
* doesn't matter if the user does not
|
|
||||||
* actually link against crtbegin.o; the
|
|
||||||
* linker won't look for a file to match a
|
|
||||||
* wildcard. The wildcard also means that it
|
|
||||||
* doesn't matter which directory crtbegin.o
|
|
||||||
* is in.
|
|
||||||
*/
|
|
||||||
KEEP (*crtbegin.o(.ctors))
|
|
||||||
KEEP (*crtbegin?.o(.ctors))
|
|
||||||
/* We don't want to include the .ctor section from
|
|
||||||
* the crtend.o file until after the sorted ctors.
|
|
||||||
* The .ctor section from the crtend file contains the
|
|
||||||
* end of ctors marker and it must be last
|
|
||||||
*/
|
|
||||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
|
||||||
KEEP (*(SORT(.ctors.*)))
|
|
||||||
KEEP (*(.ctors))
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
.dtors :
|
|
||||||
{
|
|
||||||
KEEP (*crtbegin.o(.dtors))
|
|
||||||
KEEP (*crtbegin?.o(.dtors))
|
|
||||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
|
||||||
KEEP (*(SORT(.dtors.*)))
|
|
||||||
KEEP (*(.dtors))
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
.lalign :
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
PROVIDE( _data_lma = . );
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
.dalign :
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
PROVIDE( _data = . );
|
|
||||||
} >ram AT>flash
|
|
||||||
|
|
||||||
/* Define data section virtual address is ram and physical address is flash */
|
|
||||||
.data :
|
|
||||||
{
|
|
||||||
*(.data .data.*)
|
|
||||||
*(.gnu.linkonce.d.*)
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
|
||||||
*(.sdata .sdata.* .sdata*)
|
|
||||||
*(.gnu.linkonce.s.*)
|
|
||||||
} >ram AT>flash
|
|
||||||
|
|
||||||
. = ALIGN(4);
|
|
||||||
PROVIDE( _edata = . );
|
|
||||||
PROVIDE( edata = . );
|
|
||||||
|
|
||||||
PROVIDE( _fbss = . );
|
|
||||||
PROVIDE( __bss_start = . );
|
|
||||||
.bss :
|
|
||||||
{
|
|
||||||
*(.sbss*)
|
|
||||||
*(.gnu.linkonce.sb.*)
|
|
||||||
*(.bss .bss.*)
|
|
||||||
*(.gnu.linkonce.b.*)
|
|
||||||
*(COMMON)
|
|
||||||
. = ALIGN(4);
|
|
||||||
} >ram AT>ram
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE( _end = . );
|
|
||||||
PROVIDE( end = . );
|
|
||||||
/* Define stack and head location at ram */
|
|
||||||
.stack ORIGIN(ram) + LENGTH(ram) - __STACK_SIZE :
|
|
||||||
{
|
|
||||||
PROVIDE( _heap_end = . );
|
|
||||||
. = __STACK_SIZE;
|
|
||||||
PROVIDE( _sp = . );
|
|
||||||
} >ram AT>ram
|
|
||||||
}
|
|
||||||
|
|
@ -1,210 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2019 Nuclei Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
|
||||||
* not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
|
||||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*/
|
|
||||||
/******************************************************************************
|
|
||||||
* @file gcc_demosoc_ilm.ld
|
|
||||||
* @brief GNU Linker Script for Nuclei N/NX based device in ilm Download Mode
|
|
||||||
* @version V1.0.0
|
|
||||||
* @date 17. Dec 2019
|
|
||||||
******************************************************************************/
|
|
||||||
OUTPUT_ARCH( "riscv" )
|
|
||||||
|
|
||||||
ENTRY( _start )
|
|
||||||
|
|
||||||
MEMORY
|
|
||||||
{
|
|
||||||
|
|
||||||
ilm (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64K
|
|
||||||
ram (wxa!ri) : ORIGIN = 0x90000000, LENGTH = 64K
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
SECTIONS
|
|
||||||
{
|
|
||||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
|
||||||
|
|
||||||
.init :
|
|
||||||
{
|
|
||||||
*(.vtable)
|
|
||||||
KEEP (*(SORT_NONE(.init)))
|
|
||||||
} >ilm AT>ilm
|
|
||||||
|
|
||||||
.ilalign :
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
PROVIDE( _ilm_lma = . );
|
|
||||||
} >ilm AT>ilm
|
|
||||||
|
|
||||||
.ialign :
|
|
||||||
{
|
|
||||||
PROVIDE( _ilm = . );
|
|
||||||
} >ilm AT>ilm
|
|
||||||
|
|
||||||
.text :
|
|
||||||
{
|
|
||||||
*(.text.unlikely .text.unlikely.*)
|
|
||||||
*(.text.startup .text.startup.*)
|
|
||||||
*(.text .text.*)
|
|
||||||
*(.gnu.linkonce.t.*)
|
|
||||||
} >ilm AT>ilm
|
|
||||||
|
|
||||||
.rodata : ALIGN(4)
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
*(.rdata)
|
|
||||||
*(.rodata .rodata.*)
|
|
||||||
/* section information for initial. */
|
|
||||||
. = ALIGN(4);
|
|
||||||
__rt_init_start = .;
|
|
||||||
KEEP(*(SORT(.rti_fn*)))
|
|
||||||
__rt_init_end = .;
|
|
||||||
/* section information for finsh shell */
|
|
||||||
. = ALIGN(4);
|
|
||||||
__fsymtab_start = .;
|
|
||||||
KEEP(*(FSymTab))
|
|
||||||
__fsymtab_end = .;
|
|
||||||
. = ALIGN(4);
|
|
||||||
__vsymtab_start = .;
|
|
||||||
KEEP(*(VSymTab))
|
|
||||||
__vsymtab_end = .;
|
|
||||||
*(.gnu.linkonce.r.*)
|
|
||||||
|
|
||||||
} >ilm AT>ilm
|
|
||||||
|
|
||||||
.fini :
|
|
||||||
{
|
|
||||||
KEEP (*(SORT_NONE(.fini)))
|
|
||||||
} >ilm AT>ilm
|
|
||||||
|
|
||||||
. = ALIGN(4);
|
|
||||||
|
|
||||||
PROVIDE (__etext = .);
|
|
||||||
PROVIDE (_etext = .);
|
|
||||||
PROVIDE (etext = .);
|
|
||||||
PROVIDE( _eilm = . );
|
|
||||||
|
|
||||||
|
|
||||||
.preinit_array :
|
|
||||||
{
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
|
||||||
KEEP (*(.preinit_array))
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
|
||||||
} >ilm AT>ilm
|
|
||||||
|
|
||||||
.init_array :
|
|
||||||
{
|
|
||||||
PROVIDE_HIDDEN (__init_array_start = .);
|
|
||||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
|
||||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
|
||||||
PROVIDE_HIDDEN (__init_array_end = .);
|
|
||||||
} >ilm AT>ilm
|
|
||||||
|
|
||||||
.fini_array :
|
|
||||||
{
|
|
||||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
|
||||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
|
||||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
|
||||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
|
||||||
} >ilm AT>ilm
|
|
||||||
|
|
||||||
.ctors :
|
|
||||||
{
|
|
||||||
/* gcc uses crtbegin.o to find the start of
|
|
||||||
the constructors, so we make sure it is
|
|
||||||
first. Because this is a wildcard, it
|
|
||||||
doesn't matter if the user does not
|
|
||||||
actually link against crtbegin.o; the
|
|
||||||
linker won't look for a file to match a
|
|
||||||
wildcard. The wildcard also means that it
|
|
||||||
doesn't matter which directory crtbegin.o
|
|
||||||
is in. */
|
|
||||||
KEEP (*crtbegin.o(.ctors))
|
|
||||||
KEEP (*crtbegin?.o(.ctors))
|
|
||||||
/* We don't want to include the .ctor section from
|
|
||||||
the crtend.o file until after the sorted ctors.
|
|
||||||
The .ctor section from the crtend file contains the
|
|
||||||
end of ctors marker and it must be last */
|
|
||||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
|
||||||
KEEP (*(SORT(.ctors.*)))
|
|
||||||
KEEP (*(.ctors))
|
|
||||||
} >ilm AT>ilm
|
|
||||||
|
|
||||||
.dtors :
|
|
||||||
{
|
|
||||||
KEEP (*crtbegin.o(.dtors))
|
|
||||||
KEEP (*crtbegin?.o(.dtors))
|
|
||||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
|
||||||
KEEP (*(SORT(.dtors.*)))
|
|
||||||
KEEP (*(.dtors))
|
|
||||||
} >ilm AT>ilm
|
|
||||||
|
|
||||||
|
|
||||||
.lalign :
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
PROVIDE( _data_lma = . );
|
|
||||||
} >ilm AT>ilm
|
|
||||||
|
|
||||||
.dalign :
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
PROVIDE( _data = . );
|
|
||||||
} >ram AT>ilm
|
|
||||||
|
|
||||||
.data :
|
|
||||||
{
|
|
||||||
*(.data .data.*)
|
|
||||||
*(.gnu.linkonce.d.*)
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
|
||||||
*(.sdata .sdata.* .sdata*)
|
|
||||||
*(.gnu.linkonce.s.*)
|
|
||||||
. = ALIGN(8);
|
|
||||||
*(.srodata.cst16)
|
|
||||||
*(.srodata.cst8)
|
|
||||||
*(.srodata.cst4)
|
|
||||||
*(.srodata.cst2)
|
|
||||||
*(.srodata .srodata.*)
|
|
||||||
} >ram AT>ilm
|
|
||||||
|
|
||||||
. = ALIGN(4);
|
|
||||||
PROVIDE( _edata = . );
|
|
||||||
PROVIDE( edata = . );
|
|
||||||
|
|
||||||
PROVIDE( _fbss = . );
|
|
||||||
PROVIDE( __bss_start = . );
|
|
||||||
.bss :
|
|
||||||
{
|
|
||||||
*(.sbss*)
|
|
||||||
*(.gnu.linkonce.sb.*)
|
|
||||||
*(.bss .bss.*)
|
|
||||||
*(.gnu.linkonce.b.*)
|
|
||||||
*(COMMON)
|
|
||||||
. = ALIGN(4);
|
|
||||||
} >ram AT>ram
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE( _end = . );
|
|
||||||
PROVIDE( end = . );
|
|
||||||
|
|
||||||
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
|
|
||||||
{
|
|
||||||
PROVIDE( _heap_end = . );
|
|
||||||
. = __stack_size;
|
|
||||||
PROVIDE( _sp = . );
|
|
||||||
} >ram AT>ram
|
|
||||||
}
|
|
||||||
|
|
@ -1,54 +0,0 @@
|
||||||
adapter_khz 1000
|
|
||||||
|
|
||||||
interface ftdi
|
|
||||||
ftdi_vid_pid 0x0403 0x6010
|
|
||||||
ftdi_oscan1_mode off
|
|
||||||
|
|
||||||
## bindto 0.0.0.0 can be used to cover all available interfaces.
|
|
||||||
## Uncomment bindto line to enable remote machine debug
|
|
||||||
# bindto 0.0.0.0
|
|
||||||
|
|
||||||
## If ftdi_device_desc not specified, the device description is ignored during device selection.
|
|
||||||
## So if you want to specify a dedicated FTDI device, you can select following device description:
|
|
||||||
## "Dual RS232-HS" is for Nuclei HummingBird Debugger V1
|
|
||||||
## "USB <-> JTAG-DEBUGGER" is for Nuclei HummingBird Debugger V2
|
|
||||||
## Uncomment one which match your device description
|
|
||||||
# ftdi_device_desc "Dual RS232-HS"
|
|
||||||
# ftdi_device_desc "USB <-> JTAG-DEBUGGER"
|
|
||||||
|
|
||||||
transport select jtag
|
|
||||||
|
|
||||||
ftdi_layout_init 0x0008 0x001b
|
|
||||||
ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
|
|
||||||
ftdi_layout_signal TCK -data 0x0001
|
|
||||||
ftdi_layout_signal TDI -data 0x0002
|
|
||||||
ftdi_layout_signal TDO -input 0x0004
|
|
||||||
ftdi_layout_signal TMS -data 0x0008
|
|
||||||
ftdi_layout_signal JTAG_SEL -data 0x0100 -oe 0x0100
|
|
||||||
|
|
||||||
set _CHIPNAME riscv
|
|
||||||
jtag newtap $_CHIPNAME cpu -irlen 5
|
|
||||||
|
|
||||||
set _TARGETNAME $_CHIPNAME.cpu
|
|
||||||
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
|
|
||||||
$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
|
|
||||||
|
|
||||||
set _FLASHNAME $_CHIPNAME.flash
|
|
||||||
flash bank $_FLASHNAME fespi 0x20000000 0 0 0 $_TARGETNAME
|
|
||||||
# Set the ILM space also as flash, to make sure it can be add breakpoint with hardware trigger
|
|
||||||
#flash bank onboard_ilm fespi 0x80000000 0 0 0 $_TARGETNAME
|
|
||||||
|
|
||||||
# Expose Nuclei self-defined CSRS
|
|
||||||
# See https://github.com/riscv/riscv-gnu-toolchain/issues/319#issuecomment-358397306
|
|
||||||
# Then user can view the csr register value in gdb using: info reg csr775 for CSR MTVT(0x307)
|
|
||||||
riscv expose_csrs 416-496,770-800,835-850,1227-1231,1483-1486,1984-2032,2064-2070,2370-2380,2490-2500,4032-4040
|
|
||||||
|
|
||||||
init
|
|
||||||
|
|
||||||
if {[ info exists pulse_srst]} {
|
|
||||||
ftdi_set_signal nSRST 0
|
|
||||||
ftdi_set_signal nSRST z
|
|
||||||
}
|
|
||||||
halt
|
|
||||||
# We must turn on this because otherwise the IDE version debug cannot download the program into flash
|
|
||||||
flash protect 0 0 last off
|
|
||||||
|
|
@ -1,458 +0,0 @@
|
||||||
/******************************************************************************
|
|
||||||
* @file demosoc.h
|
|
||||||
* @brief NMSIS Core Peripheral Access Layer Header File for
|
|
||||||
* Nuclei Demo SoC which support Nuclei N/NX class cores
|
|
||||||
* @version V1.00
|
|
||||||
* @date 22. Nov 2019
|
|
||||||
******************************************************************************/
|
|
||||||
/*
|
|
||||||
* Copyright (c) 2019 Nuclei Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
|
||||||
* not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
|
||||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __DEMOSOC_H__
|
|
||||||
#define __DEMOSOC_H__
|
|
||||||
|
|
||||||
#include <stddef.h>
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/** @addtogroup Nuclei
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/** @addtogroup demosoc
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/** @addtogroup Configuration_of_NMSIS
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/* =========================================================================================================================== */
|
|
||||||
/* ================ Interrupt Number Definition ================ */
|
|
||||||
/* =========================================================================================================================== */
|
|
||||||
|
|
||||||
typedef enum IRQn {
|
|
||||||
/* ======================================= Nuclei Core Specific Interrupt Numbers ======================================== */
|
|
||||||
|
|
||||||
Reserved0_IRQn = 0, /*!< Internal reserved */
|
|
||||||
Reserved1_IRQn = 1, /*!< Internal reserved */
|
|
||||||
Reserved2_IRQn = 2, /*!< Internal reserved */
|
|
||||||
SysTimerSW_IRQn = 3, /*!< System Timer SW interrupt */
|
|
||||||
Reserved3_IRQn = 4, /*!< Internal reserved */
|
|
||||||
Reserved4_IRQn = 5, /*!< Internal reserved */
|
|
||||||
Reserved5_IRQn = 6, /*!< Internal reserved */
|
|
||||||
SysTimer_IRQn = 7, /*!< System Timer Interrupt */
|
|
||||||
Reserved6_IRQn = 8, /*!< Internal reserved */
|
|
||||||
Reserved7_IRQn = 9, /*!< Internal reserved */
|
|
||||||
Reserved8_IRQn = 10, /*!< Internal reserved */
|
|
||||||
Reserved9_IRQn = 11, /*!< Internal reserved */
|
|
||||||
Reserved10_IRQn = 12, /*!< Internal reserved */
|
|
||||||
Reserved11_IRQn = 13, /*!< Internal reserved */
|
|
||||||
Reserved12_IRQn = 14, /*!< Internal reserved */
|
|
||||||
Reserved13_IRQn = 15, /*!< Internal reserved */
|
|
||||||
Reserved14_IRQn = 16, /*!< Internal reserved */
|
|
||||||
Reserved15_IRQn = 17, /*!< Internal reserved */
|
|
||||||
Reserved16_IRQn = 18, /*!< Internal reserved */
|
|
||||||
|
|
||||||
/* =========================================== demosoc Specific Interrupt Numbers ========================================= */
|
|
||||||
/* ToDo: add here your device specific external interrupt numbers. 19~1023 is reserved number for user. Maxmum interrupt supported
|
|
||||||
could get from clicinfo.NUM_INTERRUPT. According the interrupt handlers defined in startup_Device.s
|
|
||||||
eg.: Interrupt for Timer#1 eclic_tim1_handler -> TIM1_IRQn */
|
|
||||||
SOC_INT19_IRQn = 19, /*!< Device Interrupt */
|
|
||||||
SOC_INT20_IRQn = 20, /*!< Device Interrupt */
|
|
||||||
SOC_INT21_IRQn = 21, /*!< Device Interrupt */
|
|
||||||
SOC_INT22_IRQn = 22, /*!< Device Interrupt */
|
|
||||||
SOC_INT23_IRQn = 23, /*!< Device Interrupt */
|
|
||||||
SOC_INT24_IRQn = 24, /*!< Device Interrupt */
|
|
||||||
SOC_INT25_IRQn = 25, /*!< Device Interrupt */
|
|
||||||
SOC_INT26_IRQn = 26, /*!< Device Interrupt */
|
|
||||||
SOC_INT27_IRQn = 27, /*!< Device Interrupt */
|
|
||||||
SOC_INT28_IRQn = 28, /*!< Device Interrupt */
|
|
||||||
SOC_INT29_IRQn = 29, /*!< Device Interrupt */
|
|
||||||
SOC_INT30_IRQn = 30, /*!< Device Interrupt */
|
|
||||||
SOC_INT31_IRQn = 31, /*!< Device Interrupt */
|
|
||||||
SOC_INT32_IRQn = 32, /*!< Device Interrupt */
|
|
||||||
SOC_INT33_IRQn = 33, /*!< Device Interrupt */
|
|
||||||
SOC_INT34_IRQn = 34, /*!< Device Interrupt */
|
|
||||||
SOC_INT35_IRQn = 35, /*!< Device Interrupt */
|
|
||||||
SOC_INT36_IRQn = 36, /*!< Device Interrupt */
|
|
||||||
SOC_INT37_IRQn = 37, /*!< Device Interrupt */
|
|
||||||
SOC_INT38_IRQn = 38, /*!< Device Interrupt */
|
|
||||||
SOC_INT39_IRQn = 39, /*!< Device Interrupt */
|
|
||||||
SOC_INT40_IRQn = 40, /*!< Device Interrupt */
|
|
||||||
SOC_INT41_IRQn = 41, /*!< Device Interrupt */
|
|
||||||
SOC_INT42_IRQn = 42, /*!< Device Interrupt */
|
|
||||||
SOC_INT43_IRQn = 43, /*!< Device Interrupt */
|
|
||||||
SOC_INT44_IRQn = 44, /*!< Device Interrupt */
|
|
||||||
SOC_INT45_IRQn = 45, /*!< Device Interrupt */
|
|
||||||
SOC_INT46_IRQn = 46, /*!< Device Interrupt */
|
|
||||||
SOC_INT47_IRQn = 47, /*!< Device Interrupt */
|
|
||||||
SOC_INT48_IRQn = 48, /*!< Device Interrupt */
|
|
||||||
SOC_INT49_IRQn = 49, /*!< Device Interrupt */
|
|
||||||
SOC_INT50_IRQn = 50, /*!< Device Interrupt */
|
|
||||||
SOC_INT_MAX,
|
|
||||||
} IRQn_Type;
|
|
||||||
|
|
||||||
/* =========================================================================================================================== */
|
|
||||||
/* ================ Exception Code Definition ================ */
|
|
||||||
/* =========================================================================================================================== */
|
|
||||||
|
|
||||||
typedef enum EXCn {
|
|
||||||
/* ======================================= Nuclei N/NX Specific Exception Code ======================================== */
|
|
||||||
InsUnalign_EXCn = 0, /*!< Instruction address misaligned */
|
|
||||||
InsAccFault_EXCn = 1, /*!< Instruction access fault */
|
|
||||||
IlleIns_EXCn = 2, /*!< Illegal instruction */
|
|
||||||
Break_EXCn = 3, /*!< Beakpoint */
|
|
||||||
LdAddrUnalign_EXCn = 4, /*!< Load address misaligned */
|
|
||||||
LdFault_EXCn = 5, /*!< Load access fault */
|
|
||||||
StAddrUnalign_EXCn = 6, /*!< Store or AMO address misaligned */
|
|
||||||
StAccessFault_EXCn = 7, /*!< Store or AMO access fault */
|
|
||||||
UmodeEcall_EXCn = 8, /*!< Environment call from User mode */
|
|
||||||
MmodeEcall_EXCn = 11, /*!< Environment call from Machine mode */
|
|
||||||
NMI_EXCn = 0xfff, /*!< NMI interrupt */
|
|
||||||
} EXCn_Type;
|
|
||||||
|
|
||||||
/* =========================================================================================================================== */
|
|
||||||
/* ================ Processor and Core Peripheral Section ================ */
|
|
||||||
/* =========================================================================================================================== */
|
|
||||||
|
|
||||||
/* ToDo: set the defines according your Device */
|
|
||||||
/* ToDo: define the correct core revision */
|
|
||||||
#if __riscv_xlen == 32
|
|
||||||
|
|
||||||
#ifndef __NUCLEI_CORE_REV
|
|
||||||
#define __NUCLEI_N_REV 0x0104 /*!< Core Revision r1p4 */
|
|
||||||
#else
|
|
||||||
#define __NUCLEI_N_REV __NUCLEI_CORE_REV
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#elif __riscv_xlen == 64
|
|
||||||
|
|
||||||
#ifndef __NUCLEI_CORE_REV
|
|
||||||
#define __NUCLEI_NX_REV 0x0100 /*!< Core Revision r1p0 */
|
|
||||||
#else
|
|
||||||
#define __NUCLEI_NX_REV __NUCLEI_CORE_REV
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* __riscv_xlen == 64 */
|
|
||||||
|
|
||||||
/* ToDo: define the correct core features for the demosoc */
|
|
||||||
#define __ECLIC_PRESENT 1 /*!< Set to 1 if ECLIC is present */
|
|
||||||
#define __ECLIC_BASEADDR 0x0C000000UL /*!< Set to ECLIC baseaddr of your device */
|
|
||||||
|
|
||||||
//#define __ECLIC_INTCTLBITS 3 /*!< Set to 1 - 8, the number of hardware bits are actually implemented in the clicintctl registers. */
|
|
||||||
#define __ECLIC_INTNUM 51 /*!< Set to 1 - 1024, total interrupt number of ECLIC Unit */
|
|
||||||
#define __SYSTIMER_PRESENT 1 /*!< Set to 1 if System Timer is present */
|
|
||||||
#define __SYSTIMER_BASEADDR 0x02000000UL /*!< Set to SysTimer baseaddr of your device */
|
|
||||||
|
|
||||||
/*!< Set to 0, 1, or 2, 0 not present, 1 single floating point unit present, 2 double floating point unit present */
|
|
||||||
#if !defined(__riscv_flen)
|
|
||||||
#define __FPU_PRESENT 0
|
|
||||||
#elif __riscv_flen == 32
|
|
||||||
#define __FPU_PRESENT 1
|
|
||||||
#else
|
|
||||||
#define __FPU_PRESENT 2
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define __DSP_PRESENT 1 /*!< Set to 1 if DSP is present */
|
|
||||||
#define __PMP_PRESENT 1 /*!< Set to 1 if PMP is present */
|
|
||||||
#define __PMP_ENTRY_NUM 16 /*!< Set to 8 or 16, the number of PMP entries */
|
|
||||||
#define __ICACHE_PRESENT 0 /*!< Set to 1 if I-Cache is present */
|
|
||||||
#define __DCACHE_PRESENT 0 /*!< Set to 1 if D-Cache is present */
|
|
||||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
|
||||||
#define __Vendor_EXCEPTION 0 /*!< Set to 1 if vendor exception handler is present */
|
|
||||||
|
|
||||||
/** @} */ /* End of group Configuration_of_CMSIS */
|
|
||||||
|
|
||||||
|
|
||||||
#include <nmsis_core.h> /*!< Nuclei N/NX class processor and core peripherals */
|
|
||||||
/* ToDo: include your system_demosoc.h file
|
|
||||||
replace 'Device' with your device name */
|
|
||||||
#include "system_demosoc.h" /*!< demosoc System */
|
|
||||||
|
|
||||||
|
|
||||||
/* ======================================== Start of section using anonymous unions ======================================== */
|
|
||||||
#if defined (__GNUC__)
|
|
||||||
/* anonymous unions are enabled by default */
|
|
||||||
#else
|
|
||||||
#warning Not supported compiler type
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define RTC_FREQ 32768
|
|
||||||
// The TIMER frequency is just the RTC frequency
|
|
||||||
#define SOC_TIMER_FREQ RTC_FREQ
|
|
||||||
/* =========================================================================================================================== */
|
|
||||||
/* ================ Device Specific Peripheral Section ================ */
|
|
||||||
/* =========================================================================================================================== */
|
|
||||||
|
|
||||||
|
|
||||||
/** @addtogroup Device_Peripheral_peripherals
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Platform definitions
|
|
||||||
*****************************************************************************/
|
|
||||||
// IOF Mappings
|
|
||||||
#define IOF0_SPI1_MASK _AC(0x000007FC,UL)
|
|
||||||
#define SPI11_NUM_SS (4)
|
|
||||||
#define IOF_SPI1_SS0 (2u)
|
|
||||||
#define IOF_SPI1_SS1 (8u)
|
|
||||||
#define IOF_SPI1_SS2 (9u)
|
|
||||||
#define IOF_SPI1_SS3 (10u)
|
|
||||||
#define IOF_SPI1_MOSI (3u)
|
|
||||||
#define IOF_SPI1_MISO (4u)
|
|
||||||
#define IOF_SPI1_SCK (5u)
|
|
||||||
#define IOF_SPI1_DQ0 (3u)
|
|
||||||
#define IOF_SPI1_DQ1 (4u)
|
|
||||||
#define IOF_SPI1_DQ2 (6u)
|
|
||||||
#define IOF_SPI1_DQ3 (7u)
|
|
||||||
|
|
||||||
#define IOF0_SPI2_MASK _AC(0xFC000000,UL)
|
|
||||||
#define SPI2_NUM_SS (1)
|
|
||||||
#define IOF_SPI2_SS0 (26u)
|
|
||||||
#define IOF_SPI2_MOSI (27u)
|
|
||||||
#define IOF_SPI2_MISO (28u)
|
|
||||||
#define IOF_SPI2_SCK (29u)
|
|
||||||
#define IOF_SPI2_DQ0 (27u)
|
|
||||||
#define IOF_SPI2_DQ1 (28u)
|
|
||||||
#define IOF_SPI2_DQ2 (30u)
|
|
||||||
#define IOF_SPI2_DQ3 (31u)
|
|
||||||
|
|
||||||
#define IOF0_UART0_MASK _AC(0x00030000, UL)
|
|
||||||
#define IOF_UART0_RX (16u)
|
|
||||||
#define IOF_UART0_TX (17u)
|
|
||||||
|
|
||||||
#define IOF0_UART1_MASK _AC(0x03000000, UL)
|
|
||||||
#define IOF_UART1_RX (24u)
|
|
||||||
#define IOF_UART1_TX (25u)
|
|
||||||
|
|
||||||
#define IOF0_I2C_MASK _AC(0x00003000, UL)
|
|
||||||
#define IOF_I2C_SDA (12u)
|
|
||||||
#define IOF_I2C_SCL (13u)
|
|
||||||
|
|
||||||
#define IOF1_PWM0_MASK _AC(0x0000000F, UL)
|
|
||||||
#define IOF1_PWM1_MASK _AC(0x00780000, UL)
|
|
||||||
#define IOF1_PWM2_MASK _AC(0x00003C00, UL)
|
|
||||||
|
|
||||||
// Interrupt Numbers
|
|
||||||
#define SOC_ECLIC_NUM_INTERRUPTS 32
|
|
||||||
#define SOC_ECLIC_INT_GPIO_BASE 19
|
|
||||||
|
|
||||||
// Interrupt Handler Definitions
|
|
||||||
#define SOC_MTIMER_HANDLER eclic_mtip_handler
|
|
||||||
#define SOC_SOFTINT_HANDLER eclic_msip_handler
|
|
||||||
|
|
||||||
#define GPIO_BIT_ALL_ZERO (0x0)
|
|
||||||
#define GPIO_BIT_ALL_ONE (0xFFFFFFFF)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief GPIO
|
|
||||||
*/
|
|
||||||
typedef struct { /*!< GPIO Structure */
|
|
||||||
__IOM uint32_t INPUT_VAL;
|
|
||||||
__IOM uint32_t INPUT_EN;
|
|
||||||
__IOM uint32_t OUTPUT_EN;
|
|
||||||
__IOM uint32_t OUTPUT_VAL;
|
|
||||||
__IOM uint32_t PULLUP_EN;
|
|
||||||
__IOM uint32_t DRIVE;
|
|
||||||
__IOM uint32_t RISE_IE;
|
|
||||||
__IOM uint32_t RISE_IP;
|
|
||||||
__IOM uint32_t FALL_IE;
|
|
||||||
__IOM uint32_t FALL_IP;
|
|
||||||
__IOM uint32_t HIGH_IE;
|
|
||||||
__IOM uint32_t HIGH_IP;
|
|
||||||
__IOM uint32_t LOW_IE;
|
|
||||||
__IOM uint32_t LOW_IP;
|
|
||||||
__IOM uint32_t IOF_EN;
|
|
||||||
__IOM uint32_t IOF_SEL;
|
|
||||||
__IOM uint32_t OUTPUT_XOR;
|
|
||||||
} GPIO_TypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief UART
|
|
||||||
*/
|
|
||||||
typedef struct {
|
|
||||||
__IOM uint32_t TXFIFO;
|
|
||||||
__IOM uint32_t RXFIFO;
|
|
||||||
__IOM uint32_t TXCTRL;
|
|
||||||
__IOM uint32_t RXCTRL;
|
|
||||||
__IOM uint32_t IE;
|
|
||||||
__IOM uint32_t IP;
|
|
||||||
__IOM uint32_t DIV;
|
|
||||||
} UART_TypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief PWM
|
|
||||||
*/
|
|
||||||
typedef struct {
|
|
||||||
__IOM uint32_t CFG;
|
|
||||||
uint32_t RESERVED0;
|
|
||||||
__IOM uint32_t COUNT;
|
|
||||||
uint32_t RESERVED1;
|
|
||||||
__IOM uint32_t S;
|
|
||||||
uint32_t RESERVED2[3];
|
|
||||||
__IOM uint32_t CMP0;
|
|
||||||
__IOM uint32_t CMP1;
|
|
||||||
__IOM uint32_t CMP2;
|
|
||||||
__IOM uint32_t CMP3;
|
|
||||||
} PWM_TypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief QSPI
|
|
||||||
*/
|
|
||||||
typedef struct {
|
|
||||||
__IOM uint32_t SCKDIV;
|
|
||||||
__IOM uint32_t SCKMODE;
|
|
||||||
__IOM uint32_t RESERVED0[2];
|
|
||||||
__IOM uint32_t CSID;
|
|
||||||
__IOM uint32_t CSDEF;
|
|
||||||
__IOM uint32_t CSMODE;
|
|
||||||
__IOM uint32_t RESERVED1[3];
|
|
||||||
__IOM uint32_t DELAY0;
|
|
||||||
__IOM uint32_t DELAY1;
|
|
||||||
__IOM uint32_t RESERVED2[4];
|
|
||||||
__IOM uint32_t FMT;
|
|
||||||
__IOM uint32_t RESERVED3;
|
|
||||||
__IOM uint32_t TXDATA;
|
|
||||||
__IOM uint32_t RXDATA;
|
|
||||||
__IOM uint32_t TXMARK;
|
|
||||||
__IOM uint32_t RXMARK;
|
|
||||||
__IOM uint32_t RESERVED4[2];
|
|
||||||
__IOM uint32_t FCTRL;
|
|
||||||
__IOM uint32_t FFMT;
|
|
||||||
__IOM uint32_t RESERVED5[2];
|
|
||||||
__IOM uint32_t IE;
|
|
||||||
__IOM uint32_t IP;
|
|
||||||
} QSPI_TypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief I2C
|
|
||||||
*/
|
|
||||||
typedef struct {
|
|
||||||
__IOM uint8_t PRERlo;
|
|
||||||
__IOM uint8_t PRERhi;
|
|
||||||
__IOM uint8_t CTR;
|
|
||||||
__IOM uint8_t TXRXR; /* TXR and RXR in same address */
|
|
||||||
__IOM uint8_t CSR; /* CR and SR in same address */
|
|
||||||
} I2C_TypeDef;
|
|
||||||
|
|
||||||
/*@}*/ /* end of group demosoc_Peripherals */
|
|
||||||
|
|
||||||
|
|
||||||
/* ========================================= End of section using anonymous unions ========================================= */
|
|
||||||
#if defined (__GNUC__)
|
|
||||||
/* anonymous unions are enabled by default */
|
|
||||||
#else
|
|
||||||
#warning Not supported compiler type
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
/* =========================================================================================================================== */
|
|
||||||
/* ================ Device Specific Peripheral Address Map ================ */
|
|
||||||
/* =========================================================================================================================== */
|
|
||||||
|
|
||||||
|
|
||||||
/* ToDo: add here your device peripherals base addresses
|
|
||||||
following is an example for timer */
|
|
||||||
/** @addtogroup Device_Peripheral_peripheralAddr
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Peripheral and SRAM base address */
|
|
||||||
#define QSPI_FLASH_BASE (0x20000000UL) /*!< (FLASH ) Base Address */
|
|
||||||
#define ONCHIP_ROM_BASE (0x00001000UL) /*!< (ROM ) Base Address */
|
|
||||||
#define ONCHIP_ILM_BASE (0x80000000UL) /*!< (ILM ) Base Address */
|
|
||||||
#define ONCHIP_DLM_BASE (0x90000000UL) /*!< (DLM ) Base Address */
|
|
||||||
#define DEMOSOC_PERIPH_BASE (0x10000000UL) /*!< (Peripheral) Base Address */
|
|
||||||
|
|
||||||
/* Peripheral memory map */
|
|
||||||
/* Fast-IO Interfaced IP */
|
|
||||||
#define GPIO_BASE (DEMOSOC_PERIPH_BASE + 0x12000) /*!< (GPIO) Base Address */
|
|
||||||
/* PPI Interfaced IP */
|
|
||||||
#define UART0_BASE (DEMOSOC_PERIPH_BASE + 0x13000) /*!< (UART0) Base Address */
|
|
||||||
#define QSPI0_BASE (DEMOSOC_PERIPH_BASE + 0x14000) /*!< (QSPI0) Base Address */
|
|
||||||
#define PWM0_BASE (DEMOSOC_PERIPH_BASE + 0x15000) /*!< (PWM0) Base Address */
|
|
||||||
#define UART1_BASE (DEMOSOC_PERIPH_BASE + 0x23000) /*!< (UART1) Base Address */
|
|
||||||
#define QSPI1_BASE (DEMOSOC_PERIPH_BASE + 0x24000) /*!< (QSPI1) Base Address */
|
|
||||||
#define PWM1_BASE (DEMOSOC_PERIPH_BASE + 0x25000) /*!< (PWM1) Base Address */
|
|
||||||
#define QSPI2_BASE (DEMOSOC_PERIPH_BASE + 0x34000) /*!< (QSPI2) Base Address */
|
|
||||||
#define PWM2_BASE (DEMOSOC_PERIPH_BASE + 0x35000) /*!< (PWM2) Base Address */
|
|
||||||
#define I2C_BASE (DEMOSOC_PERIPH_BASE + 0x42000) /*!< (I2C Master) Base Address */
|
|
||||||
|
|
||||||
/** @} */ /* End of group Device_Peripheral_peripheralAddr */
|
|
||||||
|
|
||||||
|
|
||||||
/* =========================================================================================================================== */
|
|
||||||
/* ================ Peripheral declaration ================ */
|
|
||||||
/* =========================================================================================================================== */
|
|
||||||
|
|
||||||
|
|
||||||
/* ToDo: add here your device peripherals pointer definitions
|
|
||||||
following is an example for timer */
|
|
||||||
/** @addtogroup Device_Peripheral_declaration
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE)
|
|
||||||
#define UART0 ((UART_TypeDef *) UART0_BASE)
|
|
||||||
#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE)
|
|
||||||
#define PWM0 ((PWM_TypeDef *) PWM0_BASE)
|
|
||||||
#define UART1 ((UART_TypeDef *) UART1_BASE)
|
|
||||||
#define QSPI1 ((QSPI_TypeDef *) QSPI1_BASE)
|
|
||||||
#define PWM1 ((PWM_TypeDef *) PWM1_BASE)
|
|
||||||
#define QSPI2 ((QSPI_TypeDef *) QSPI2_BASE)
|
|
||||||
#define PWM2 ((PWM_TypeDef *) PWM2_BASE)
|
|
||||||
#define I2C ((I2C_TypeDef *) I2C_BASE)
|
|
||||||
|
|
||||||
// Helper functions
|
|
||||||
#define _REG8(p, i) (*(volatile uint8_t *) ((p) + (i)))
|
|
||||||
#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
|
|
||||||
#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))
|
|
||||||
|
|
||||||
#define GPIO_REG(offset) _REG32(GPIO_BASE, offset)
|
|
||||||
#define PWM0_REG(offset) _REG32(PWM0_BASE, offset)
|
|
||||||
#define PWM1_REG(offset) _REG32(PWM1_BASE, offset)
|
|
||||||
#define PWM2_REG(offset) _REG32(PWM2_BASE, offset)
|
|
||||||
#define SPI0_REG(offset) _REG32(QSPI0_BASE, offset)
|
|
||||||
#define SPI1_REG(offset) _REG32(QSPI1_BASE, offset)
|
|
||||||
#define SPI2_REG(offset) _REG32(QSPI2_BASE, offset)
|
|
||||||
#define UART0_REG(offset) _REG32(UART0_BASE, offset)
|
|
||||||
#define UART1_REG(offset) _REG32(UART1_BASE, offset)
|
|
||||||
#define I2C_REG(offset) _REG8(I2C_BASE, offset)
|
|
||||||
|
|
||||||
// Misc
|
|
||||||
|
|
||||||
#define NUM_GPIO 32
|
|
||||||
|
|
||||||
uint32_t get_cpu_freq();
|
|
||||||
void delay_1ms(uint32_t count);
|
|
||||||
|
|
||||||
/** @} */ /* End of group demosoc */
|
|
||||||
|
|
||||||
/** @} */ /* End of group Nuclei */
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* __DEMOSOC_H__ */
|
|
||||||
|
|
@ -1,56 +0,0 @@
|
||||||
// See LICENSE for license details.
|
|
||||||
#ifndef _DEMOSOC_GPIO_H
|
|
||||||
#define _DEMOSOC_GPIO_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define GPIO_INPUT_VAL (0x00)
|
|
||||||
#define GPIO_INPUT_EN (0x04)
|
|
||||||
#define GPIO_OUTPUT_EN (0x08)
|
|
||||||
#define GPIO_OUTPUT_VAL (0x0C)
|
|
||||||
#define GPIO_PULLUP_EN (0x10)
|
|
||||||
#define GPIO_DRIVE (0x14)
|
|
||||||
#define GPIO_RISE_IE (0x18)
|
|
||||||
#define GPIO_RISE_IP (0x1C)
|
|
||||||
#define GPIO_FALL_IE (0x20)
|
|
||||||
#define GPIO_FALL_IP (0x24)
|
|
||||||
#define GPIO_HIGH_IE (0x28)
|
|
||||||
#define GPIO_HIGH_IP (0x2C)
|
|
||||||
#define GPIO_LOW_IE (0x30)
|
|
||||||
#define GPIO_LOW_IP (0x34)
|
|
||||||
#define GPIO_IOF_EN (0x38)
|
|
||||||
#define GPIO_IOF_SEL (0x3C)
|
|
||||||
#define GPIO_OUTPUT_XOR (0x40)
|
|
||||||
|
|
||||||
typedef enum iof_func {
|
|
||||||
IOF_SEL_GPIO = 0,
|
|
||||||
IOF_SEL_0 = 1,
|
|
||||||
IOF_SEL_1 = 2
|
|
||||||
} IOF_FUNC;
|
|
||||||
|
|
||||||
typedef enum gpio_int_type {
|
|
||||||
GPIO_INT_RISE = 0,
|
|
||||||
GPIO_INT_FALL = 1,
|
|
||||||
GPIO_INT_HIGH = 2,
|
|
||||||
GPIO_INT_LOW = 3
|
|
||||||
} GPIO_INT_TYPE;
|
|
||||||
|
|
||||||
int32_t gpio_iof_config(GPIO_TypeDef* gpio, uint32_t mask, IOF_FUNC func);
|
|
||||||
int32_t gpio_enable_output(GPIO_TypeDef* gpio, uint32_t mask);
|
|
||||||
int32_t gpio_enable_input(GPIO_TypeDef* gpio, uint32_t mask);
|
|
||||||
int32_t gpio_write(GPIO_TypeDef* gpio, uint32_t mask, uint32_t value);
|
|
||||||
int32_t gpio_toggle(GPIO_TypeDef* gpio, uint32_t mask);
|
|
||||||
int32_t gpio_read(GPIO_TypeDef* gpio, uint32_t mask);
|
|
||||||
int32_t gpio_set_pue(GPIO_TypeDef* gpio, uint32_t mask, uint32_t value);
|
|
||||||
int32_t gpio_set_ds(GPIO_TypeDef* gpio, uint32_t mask, uint32_t value);
|
|
||||||
int32_t gpio_set_outxor(GPIO_TypeDef* gpio, uint32_t mask, uint32_t value);
|
|
||||||
int32_t gpio_enable_interrupt(GPIO_TypeDef* gpio, uint32_t mask, GPIO_INT_TYPE type);
|
|
||||||
int32_t gpio_disable_interrupt(GPIO_TypeDef* gpio, uint32_t mask, GPIO_INT_TYPE type);
|
|
||||||
int32_t gpio_clear_interrupt(GPIO_TypeDef* gpio, uint32_t mask, GPIO_INT_TYPE type);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
#endif /* _DEMOSOC_GPIO_H */
|
|
||||||
|
|
@ -1,41 +0,0 @@
|
||||||
//See LICENSE for license details
|
|
||||||
|
|
||||||
#ifndef _DEMOSOC_I2C_H
|
|
||||||
#define _DEMOSOC_I2C_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* register offsets */
|
|
||||||
//all registers are 8 bits width
|
|
||||||
#define I2C_REG_PRERlo 0x00
|
|
||||||
#define I2C_REG_PRERhi 0x01
|
|
||||||
#define I2C_REG_CTR 0X02
|
|
||||||
#define I2C_REG_TXR 0x03
|
|
||||||
#define I2C_REG_RXR 0X03
|
|
||||||
#define I2C_REG_CR 0X04
|
|
||||||
#define I2C_REG_SR 0X04
|
|
||||||
|
|
||||||
#define I2C_CTR_EN (1 << 7)
|
|
||||||
#define I2C_CTR_IE (1 << 6)
|
|
||||||
|
|
||||||
#define I2C_CR_STA (1 << 7)
|
|
||||||
#define I2C_CR_STO (1 << 6)
|
|
||||||
#define I2C_CR_RD (1 << 5)
|
|
||||||
#define I2C_CR_WR (1 << 4)
|
|
||||||
#define I2C_CR_ACK (1 << 3)
|
|
||||||
#define I2C_CR_IACK (1 << 0)
|
|
||||||
|
|
||||||
#define I2C_TXR_WRRD (1 << 0)//0:write to slave; 1:read from slave;
|
|
||||||
|
|
||||||
#define I2C_SR_RXACK (1 << 7)//0:received; 1:no ack resceived
|
|
||||||
#define I2C_SR_BUSY (1 << 6)//0:after 'STOP' detected; 1:after 'START' detected
|
|
||||||
#define I2C_SR_AL (1 << 5)
|
|
||||||
#define I2C_SR_TIP (1 << 1)//0:transfer complete; 1:transferring
|
|
||||||
#define I2C_SR_IF (1 << 0)
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
#endif /* _DEMOSOC_I2C_H */
|
|
||||||
|
|
@ -1,44 +0,0 @@
|
||||||
// See LICENSE for license details.
|
|
||||||
|
|
||||||
#ifndef _DEMOSOC_PWM_H
|
|
||||||
#define _DEMOSOC_PWM_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Register offsets */
|
|
||||||
|
|
||||||
#define PWM_CFG 0x00
|
|
||||||
#define PWM_COUNT 0x08
|
|
||||||
#define PWM_S 0x10
|
|
||||||
#define PWM_CMP0 0x20
|
|
||||||
#define PWM_CMP1 0x24
|
|
||||||
#define PWM_CMP2 0x28
|
|
||||||
#define PWM_CMP3 0x2C
|
|
||||||
|
|
||||||
/* Constants */
|
|
||||||
|
|
||||||
#define PWM_CFG_SCALE 0x0000000F
|
|
||||||
#define PWM_CFG_STICKY 0x00000100
|
|
||||||
#define PWM_CFG_ZEROCMP 0x00000200
|
|
||||||
#define PWM_CFG_DEGLITCH 0x00000400
|
|
||||||
#define PWM_CFG_ENALWAYS 0x00001000
|
|
||||||
#define PWM_CFG_ONESHOT 0x00002000
|
|
||||||
#define PWM_CFG_CMP0CENTER 0x00010000
|
|
||||||
#define PWM_CFG_CMP1CENTER 0x00020000
|
|
||||||
#define PWM_CFG_CMP2CENTER 0x00040000
|
|
||||||
#define PWM_CFG_CMP3CENTER 0x00080000
|
|
||||||
#define PWM_CFG_CMP0GANG 0x01000000
|
|
||||||
#define PWM_CFG_CMP1GANG 0x02000000
|
|
||||||
#define PWM_CFG_CMP2GANG 0x04000000
|
|
||||||
#define PWM_CFG_CMP3GANG 0x08000000
|
|
||||||
#define PWM_CFG_CMP0IP 0x10000000
|
|
||||||
#define PWM_CFG_CMP1IP 0x20000000
|
|
||||||
#define PWM_CFG_CMP2IP 0x40000000
|
|
||||||
#define PWM_CFG_CMP3IP 0x80000000
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
#endif /* _DEMOSOC_PWM_H */
|
|
||||||
|
|
@ -1,86 +0,0 @@
|
||||||
// See LICENSE for license details.
|
|
||||||
|
|
||||||
#ifndef _DEMOSOC_SPI_H
|
|
||||||
#define _DEMOSOC_SPI_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Register offsets */
|
|
||||||
|
|
||||||
#define SPI_REG_SCKDIV 0x00
|
|
||||||
#define SPI_REG_SCKMODE 0x04
|
|
||||||
#define SPI_REG_CSID 0x10
|
|
||||||
#define SPI_REG_CSDEF 0x14
|
|
||||||
#define SPI_REG_CSMODE 0x18
|
|
||||||
|
|
||||||
#define SPI_REG_DCSSCK 0x28
|
|
||||||
#define SPI_REG_DSCKCS 0x2a
|
|
||||||
#define SPI_REG_DINTERCS 0x2c
|
|
||||||
#define SPI_REG_DINTERXFR 0x2e
|
|
||||||
|
|
||||||
#define SPI_REG_FMT 0x40
|
|
||||||
#define SPI_REG_TXFIFO 0x48
|
|
||||||
#define SPI_REG_RXFIFO 0x4c
|
|
||||||
#define SPI_REG_TXCTRL 0x50
|
|
||||||
#define SPI_REG_RXCTRL 0x54
|
|
||||||
|
|
||||||
#define SPI_REG_FCTRL 0x60
|
|
||||||
#define SPI_REG_FFMT 0x64
|
|
||||||
|
|
||||||
#define SPI_REG_IE 0x70
|
|
||||||
#define SPI_REG_IP 0x74
|
|
||||||
|
|
||||||
/* Fields */
|
|
||||||
|
|
||||||
#define SPI_SCK_POL 0x1
|
|
||||||
#define SPI_SCK_PHA 0x2
|
|
||||||
|
|
||||||
#define SPI_FMT_PROTO(x) ((x) & 0x3)
|
|
||||||
#define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2)
|
|
||||||
#define SPI_FMT_DIR(x) (((x) & 0x1) << 3)
|
|
||||||
#define SPI_FMT_LEN(x) (((x) & 0xf) << 16)
|
|
||||||
|
|
||||||
/* TXCTRL register */
|
|
||||||
#define SPI_TXWM(x) ((x) & 0xffff)
|
|
||||||
/* RXCTRL register */
|
|
||||||
#define SPI_RXWM(x) ((x) & 0xffff)
|
|
||||||
|
|
||||||
#define SPI_IP_TXWM 0x1
|
|
||||||
#define SPI_IP_RXWM 0x2
|
|
||||||
|
|
||||||
#define SPI_FCTRL_EN 0x1
|
|
||||||
|
|
||||||
#define SPI_INSN_CMD_EN 0x1
|
|
||||||
#define SPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1)
|
|
||||||
#define SPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4)
|
|
||||||
#define SPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8)
|
|
||||||
#define SPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10)
|
|
||||||
#define SPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12)
|
|
||||||
#define SPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16)
|
|
||||||
#define SPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24)
|
|
||||||
|
|
||||||
#define SPI_TXFIFO_FULL (1 << 31)
|
|
||||||
#define SPI_RXFIFO_EMPTY (1 << 31)
|
|
||||||
|
|
||||||
/* Values */
|
|
||||||
|
|
||||||
#define SPI_CSMODE_AUTO 0
|
|
||||||
#define SPI_CSMODE_HOLD 2
|
|
||||||
#define SPI_CSMODE_OFF 3
|
|
||||||
|
|
||||||
#define SPI_DIR_RX 0
|
|
||||||
#define SPI_DIR_TX 1
|
|
||||||
|
|
||||||
#define SPI_PROTO_S 0
|
|
||||||
#define SPI_PROTO_D 1
|
|
||||||
#define SPI_PROTO_Q 2
|
|
||||||
|
|
||||||
#define SPI_ENDIAN_MSB 0
|
|
||||||
#define SPI_ENDIAN_LSB 1
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
#endif /* _DEMOSOC_SPI_H */
|
|
||||||
|
|
@ -1,75 +0,0 @@
|
||||||
// See LICENSE for license details.
|
|
||||||
|
|
||||||
#ifndef _DEMOSOC_UART_H
|
|
||||||
#define _DEMOSOC_UART_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Register offsets */
|
|
||||||
#define UART_REG_TXFIFO 0x00
|
|
||||||
#define UART_REG_RXFIFO 0x04
|
|
||||||
#define UART_REG_TXCTRL 0x08
|
|
||||||
#define UART_REG_RXCTRL 0x0c
|
|
||||||
#define UART_REG_IE 0x10
|
|
||||||
#define UART_REG_IP 0x14
|
|
||||||
#define UART_REG_DIV 0x18
|
|
||||||
|
|
||||||
/* TXCTRL register */
|
|
||||||
#define UART_TXEN 0x1
|
|
||||||
#define UART_TXWM(x) (((x) & 0xffff) << 16)
|
|
||||||
|
|
||||||
/* RXCTRL register */
|
|
||||||
#define UART_RXEN 0x1
|
|
||||||
#define UART_RXWM(x) (((x) & 0xffff) << 16)
|
|
||||||
|
|
||||||
/* IP register */
|
|
||||||
#define UART_IP_TXWM 0x1
|
|
||||||
#define UART_IP_RXWM 0x2
|
|
||||||
|
|
||||||
#define UART_TXFIFO_FULL (1<<31)
|
|
||||||
#define UART_RXFIFO_EMPTY (1<<31)
|
|
||||||
|
|
||||||
#define UART_TXCTRL_TXCNT_OFS (16)
|
|
||||||
#define UART_TXCTRL_TXCNT_MASK (0x7 << UART_TXCTRL_TXCNT_OFS)
|
|
||||||
#define UART_TXCTRL_TXEN_OFS (0)
|
|
||||||
#define UART_TXCTRL_TXEN_MASK (0x1 << UART_TXCTRL_TXEN_OFS)
|
|
||||||
#define UART_TXCTRL_NSTOP_OFS (1)
|
|
||||||
#define UART_TXCTRL_NSTOP_MASK (0x1 << UART_TXCTRL_TXEN_OFS)
|
|
||||||
|
|
||||||
#define UART_RXCTRL_RXCNT_OFS (16)
|
|
||||||
#define UART_RXCTRL_RXCNT_MASK (0x7 << UART_RXCTRL_RXCNT_OFS)
|
|
||||||
#define UART_RXCTRL_RXEN_OFS (0)
|
|
||||||
#define UART_RXCTRL_RXEN_MASK (0x1 << UART_RXCTRL_RXEN_OFS)
|
|
||||||
|
|
||||||
#define UART_IE_TXIE_OFS (0)
|
|
||||||
#define UART_IE_TXIE_MASK (0x1 << UART_IE_TXIE_OFS)
|
|
||||||
#define UART_IE_RXIE_OFS (1)
|
|
||||||
#define UART_IE_RXIE_MASK (0x1 << UART_IE_RXIE_OFS)
|
|
||||||
|
|
||||||
#define UART_IP_TXIP_OFS (0)
|
|
||||||
#define UART_IP_TXIP_MASK (0x1 << UART_IP_TXIP_OFS)
|
|
||||||
#define UART_IP_RXIP_OFS (1)
|
|
||||||
#define UART_IP_RXIP_MASK (0x1 << UART_IP_RXIP_OFS)
|
|
||||||
|
|
||||||
typedef enum uart_stop_bit {
|
|
||||||
UART_STOP_BIT_1 = 0,
|
|
||||||
UART_STOP_BIT_2 = 1
|
|
||||||
} UART_STOP_BIT;
|
|
||||||
|
|
||||||
int32_t uart_init(UART_TypeDef* uart, uint32_t baudrate);
|
|
||||||
int32_t uart_config_stopbit(UART_TypeDef* uart, UART_STOP_BIT stopbit);
|
|
||||||
int32_t uart_write(UART_TypeDef* uart, uint8_t val);
|
|
||||||
uint8_t uart_read(UART_TypeDef* uart);
|
|
||||||
int32_t uart_set_tx_watermark(UART_TypeDef* uart, uint32_t watermark);
|
|
||||||
int32_t uart_enable_txint(UART_TypeDef* uart);
|
|
||||||
int32_t uart_disable_txint(UART_TypeDef* uart);
|
|
||||||
int32_t uart_set_rx_watermark(UART_TypeDef* uart, uint32_t watermark);
|
|
||||||
int32_t uart_enable_rxint(UART_TypeDef* uart);
|
|
||||||
int32_t uart_disable_rxint(UART_TypeDef* uart);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
#endif /* _DEMOSOC_UART_H */
|
|
||||||
|
|
@ -1,19 +0,0 @@
|
||||||
// See LICENSE for license details.
|
|
||||||
#ifndef _NUCLEI_SDK_SOC_H
|
|
||||||
#define _NUCLEI_SDK_SOC_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#include "demosoc.h"
|
|
||||||
#include "demosoc_uart.h"
|
|
||||||
#include "demosoc_gpio.h"
|
|
||||||
#include "demosoc_i2c.h"
|
|
||||||
#include "demosoc_spi.h"
|
|
||||||
#include "demosoc_pwm.h"
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,79 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
|
||||||
* Copyright (c) 2019 Nuclei Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
|
||||||
* not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
|
||||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*/
|
|
||||||
/*******************************************************************************
|
|
||||||
* @file system_demosoc.h
|
|
||||||
* @brief NMSIS Nuclei N/NX Device Peripheral Access Layer Header File for
|
|
||||||
* Device <Device>
|
|
||||||
* @version V1.00
|
|
||||||
* @date 17. Dec 2019
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
#ifndef __SYSTEM_DEMOSOC_H__ /* ToDo: replace '<Device>' with your device name */
|
|
||||||
#define __SYSTEM_DEMOSOC_H__
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#include <stdint.h>
|
|
||||||
|
|
||||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief Setup the microcontroller system.
|
|
||||||
* \details
|
|
||||||
* Initialize the System and update the SystemCoreClock variable.
|
|
||||||
*/
|
|
||||||
extern void SystemInit(void);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief Update SystemCoreClock variable.
|
|
||||||
* \details
|
|
||||||
* Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
|
|
||||||
*/
|
|
||||||
extern void SystemCoreClockUpdate(void);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief Register an exception handler for exception code EXCn
|
|
||||||
*/
|
|
||||||
extern void Exception_Register_EXC(uint32_t EXCn, unsigned long exc_handler);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief Get current exception handler for exception code EXCn
|
|
||||||
*/
|
|
||||||
extern unsigned long Exception_Get_EXC(uint32_t EXCn);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief Initialize eclic config
|
|
||||||
*/
|
|
||||||
extern void ECLIC_Init(void);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief Initialize a specific IRQ and register the handler
|
|
||||||
* \details
|
|
||||||
* This function set vector mode, trigger mode and polarity, interrupt level and priority,
|
|
||||||
* assign handler for specific IRQn.
|
|
||||||
*/
|
|
||||||
extern int32_t ECLIC_Register_IRQ(IRQn_Type IRQn, uint8_t shv, ECLIC_TRIGGER_Type trig_mode, uint8_t lvl, uint8_t priority, void* handler);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* __SYSTEM_DEMOSOC_H__ */
|
|
||||||
|
|
@ -1,180 +0,0 @@
|
||||||
#include "demosoc.h"
|
|
||||||
#include "demosoc_gpio.h"
|
|
||||||
|
|
||||||
int32_t gpio_iof_config(GPIO_TypeDef* gpio, uint32_t mask, IOF_FUNC func)
|
|
||||||
{
|
|
||||||
if (__RARELY(gpio == NULL)) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
switch (func) {
|
|
||||||
case IOF_SEL_GPIO:
|
|
||||||
gpio->IOF_EN &= ~mask;
|
|
||||||
break;
|
|
||||||
case IOF_SEL_0:
|
|
||||||
gpio->IOF_SEL &= ~mask;
|
|
||||||
gpio->IOF_EN |= mask;
|
|
||||||
break;
|
|
||||||
case IOF_SEL_1:
|
|
||||||
gpio->IOF_SEL |= mask;
|
|
||||||
gpio->IOF_EN |= mask;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int32_t gpio_enable_output(GPIO_TypeDef* gpio, uint32_t mask)
|
|
||||||
{
|
|
||||||
if (__RARELY(gpio == NULL)) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
gpio->OUTPUT_EN |= mask;
|
|
||||||
gpio->INPUT_EN &= ~mask;
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int32_t gpio_enable_input(GPIO_TypeDef* gpio, uint32_t mask)
|
|
||||||
{
|
|
||||||
if (__RARELY(gpio == NULL)) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
gpio->INPUT_EN |= mask;
|
|
||||||
gpio->OUTPUT_EN &= ~mask;
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int32_t gpio_write(GPIO_TypeDef* gpio, uint32_t mask, uint32_t value)
|
|
||||||
{
|
|
||||||
if (__RARELY(gpio == NULL)) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
// If value != 0, mean set gpio pin high, otherwise set pin low
|
|
||||||
if (value) {
|
|
||||||
gpio->OUTPUT_VAL |= (mask);
|
|
||||||
} else {
|
|
||||||
gpio->OUTPUT_VAL &= ~(mask);
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int32_t gpio_toggle(GPIO_TypeDef* gpio, uint32_t mask)
|
|
||||||
{
|
|
||||||
if (__RARELY(gpio == NULL)) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
gpio->OUTPUT_VAL = (mask ^ gpio->OUTPUT_VAL);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
int32_t gpio_read(GPIO_TypeDef* gpio, uint32_t mask)
|
|
||||||
{
|
|
||||||
if (__RARELY(gpio == NULL)) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
return gpio->INPUT_VAL & mask;
|
|
||||||
}
|
|
||||||
|
|
||||||
int32_t gpio_set_pue(GPIO_TypeDef* gpio, uint32_t mask, uint32_t value)
|
|
||||||
{
|
|
||||||
if (__RARELY(gpio == NULL)) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
mask = gpio->PULLUP_EN & (~mask);
|
|
||||||
gpio->PULLUP_EN = (mask | value);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int32_t gpio_set_ds(GPIO_TypeDef* gpio, uint32_t mask, uint32_t value)
|
|
||||||
{
|
|
||||||
if (__RARELY(gpio == NULL)) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
mask = gpio->DRIVE & (~mask);
|
|
||||||
gpio->DRIVE = (mask | value);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int32_t gpio_set_outxor(GPIO_TypeDef* gpio, uint32_t mask, uint32_t value)
|
|
||||||
{
|
|
||||||
if (__RARELY(gpio == NULL)) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
mask = gpio->OUTPUT_XOR & (~mask);
|
|
||||||
gpio->OUTPUT_XOR = (mask | value);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int32_t gpio_enable_interrupt(GPIO_TypeDef* gpio, uint32_t mask, GPIO_INT_TYPE type)
|
|
||||||
{
|
|
||||||
if (__RARELY(gpio == NULL)) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
switch (type) {
|
|
||||||
case GPIO_INT_RISE:
|
|
||||||
gpio->RISE_IE |= mask;
|
|
||||||
break;
|
|
||||||
case GPIO_INT_FALL:
|
|
||||||
gpio->FALL_IE |= mask;
|
|
||||||
break;
|
|
||||||
case GPIO_INT_HIGH:
|
|
||||||
gpio->HIGH_IE |= mask;
|
|
||||||
break;
|
|
||||||
case GPIO_INT_LOW:
|
|
||||||
gpio->LOW_IE |= mask;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int32_t gpio_disable_interrupt(GPIO_TypeDef* gpio, uint32_t mask, GPIO_INT_TYPE type)
|
|
||||||
{
|
|
||||||
if (__RARELY(gpio == NULL)) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
switch (type) {
|
|
||||||
case GPIO_INT_RISE:
|
|
||||||
gpio->RISE_IE &= ~mask;
|
|
||||||
break;
|
|
||||||
case GPIO_INT_FALL:
|
|
||||||
gpio->FALL_IE &= ~mask;
|
|
||||||
break;
|
|
||||||
case GPIO_INT_HIGH:
|
|
||||||
gpio->HIGH_IE &= ~mask;
|
|
||||||
break;
|
|
||||||
case GPIO_INT_LOW:
|
|
||||||
gpio->LOW_IE &= ~mask;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int32_t gpio_clear_interrupt(GPIO_TypeDef* gpio, uint32_t mask, GPIO_INT_TYPE type)
|
|
||||||
{
|
|
||||||
if (__RARELY(gpio == NULL)) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
switch (type) {
|
|
||||||
case GPIO_INT_RISE:
|
|
||||||
gpio->RISE_IP |= mask;
|
|
||||||
break;
|
|
||||||
case GPIO_INT_FALL:
|
|
||||||
gpio->FALL_IP |= mask;
|
|
||||||
break;
|
|
||||||
case GPIO_INT_HIGH:
|
|
||||||
gpio->HIGH_IP |= mask;
|
|
||||||
break;
|
|
||||||
case GPIO_INT_LOW:
|
|
||||||
gpio->LOW_IP |= mask;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
@ -1,104 +0,0 @@
|
||||||
#include "demosoc.h"
|
|
||||||
#include "demosoc_uart.h"
|
|
||||||
|
|
||||||
int32_t uart_init(UART_TypeDef* uart, uint32_t baudrate)
|
|
||||||
{
|
|
||||||
if (__RARELY(uart == NULL)) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
uart->DIV = SystemCoreClock / baudrate - 1;
|
|
||||||
uart->TXCTRL |= UART_TXEN;
|
|
||||||
uart->RXCTRL |= UART_RXEN;
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int32_t uart_config_stopbit(UART_TypeDef* uart, UART_STOP_BIT stopbit)
|
|
||||||
{
|
|
||||||
if (__RARELY(uart == NULL)) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
uint32_t stopval = stopbit;
|
|
||||||
stopval = (stopbit << UART_TXCTRL_NSTOP_OFS) & UART_TXCTRL_TXCNT_MASK;
|
|
||||||
uart->TXCTRL &= stopval | (~UART_TXCTRL_TXCNT_MASK);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int32_t uart_write(UART_TypeDef* uart, uint8_t val)
|
|
||||||
{
|
|
||||||
if (__RARELY(uart == NULL)) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
#ifndef SIMULATION_XLSPIKE
|
|
||||||
while (uart->TXFIFO & UART_TXFIFO_FULL);
|
|
||||||
#endif
|
|
||||||
uart->TXFIFO = val;
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint8_t uart_read(UART_TypeDef* uart)
|
|
||||||
{
|
|
||||||
uint32_t reg;
|
|
||||||
if (__RARELY(uart == NULL)) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
do {
|
|
||||||
reg = uart->RXFIFO;
|
|
||||||
} while (reg & UART_RXFIFO_EMPTY);
|
|
||||||
return (uint8_t)(reg & 0xFF);
|
|
||||||
}
|
|
||||||
|
|
||||||
int32_t uart_set_tx_watermark(UART_TypeDef* uart, uint32_t watermark)
|
|
||||||
{
|
|
||||||
if (__RARELY(uart == NULL)) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
watermark = (watermark << UART_TXCTRL_TXCNT_OFS) & UART_TXCTRL_TXCNT_MASK;
|
|
||||||
uart->TXCTRL &= watermark | (~UART_TXCTRL_TXCNT_MASK);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int32_t uart_enable_txint(UART_TypeDef* uart)
|
|
||||||
{
|
|
||||||
if (__RARELY(uart == NULL)) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
uart->IE |= UART_IE_TXIE_MASK;
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int32_t uart_disable_txint(UART_TypeDef* uart)
|
|
||||||
{
|
|
||||||
if (__RARELY(uart == NULL)) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
uart->IE &= ~UART_IE_TXIE_MASK;
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int32_t uart_set_rx_watermark(UART_TypeDef* uart, uint32_t watermark)
|
|
||||||
{
|
|
||||||
if (__RARELY(uart == NULL)) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
watermark = (watermark << UART_RXCTRL_RXCNT_OFS) & UART_RXCTRL_RXCNT_MASK;
|
|
||||||
uart->RXCTRL &= watermark | (~UART_RXCTRL_RXCNT_MASK);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int32_t uart_enable_rxint(UART_TypeDef* uart)
|
|
||||||
{
|
|
||||||
if (__RARELY(uart == NULL)) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
uart->IE |= UART_IE_RXIE_MASK;
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int32_t uart_disable_rxint(UART_TypeDef* uart)
|
|
||||||
{
|
|
||||||
if (__RARELY(uart == NULL)) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
uart->IE &= ~UART_IE_RXIE_MASK;
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
@ -1,231 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2019 Nuclei Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
|
||||||
* not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
|
||||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*/
|
|
||||||
/******************************************************************************
|
|
||||||
* \file intexc_demosoc.S
|
|
||||||
* \brief NMSIS Interrupt and Exception Handling Template File
|
|
||||||
* for Nuclei Demo SoC which support Nuclei N/NX class cores
|
|
||||||
* \version V1.00
|
|
||||||
* \date 17 Dec 2019
|
|
||||||
*
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
#include "riscv_encoding.h"
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief Global interrupt disabled
|
|
||||||
* \details
|
|
||||||
* This function disable global interrupt.
|
|
||||||
* \remarks
|
|
||||||
* - All the interrupt requests will be ignored by CPU.
|
|
||||||
*/
|
|
||||||
.macro DISABLE_MIE
|
|
||||||
csrc CSR_MSTATUS, MSTATUS_MIE
|
|
||||||
.endm
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief Macro for context save
|
|
||||||
* \details
|
|
||||||
* This macro save ABI defined caller saved registers in the stack.
|
|
||||||
* \remarks
|
|
||||||
* - This Macro could use to save context when you enter to interrupt
|
|
||||||
* or exception
|
|
||||||
*/
|
|
||||||
/* Save caller registers */
|
|
||||||
.macro SAVE_CONTEXT
|
|
||||||
/* Allocate stack space for context saving */
|
|
||||||
#ifndef __riscv_32e
|
|
||||||
addi sp, sp, -20*REGBYTES
|
|
||||||
#else
|
|
||||||
addi sp, sp, -14*REGBYTES
|
|
||||||
#endif /* __riscv_32e */
|
|
||||||
|
|
||||||
STORE x1, 0*REGBYTES(sp)
|
|
||||||
STORE x4, 1*REGBYTES(sp)
|
|
||||||
STORE x5, 2*REGBYTES(sp)
|
|
||||||
STORE x6, 3*REGBYTES(sp)
|
|
||||||
STORE x7, 4*REGBYTES(sp)
|
|
||||||
STORE x10, 5*REGBYTES(sp)
|
|
||||||
STORE x11, 6*REGBYTES(sp)
|
|
||||||
STORE x12, 7*REGBYTES(sp)
|
|
||||||
STORE x13, 8*REGBYTES(sp)
|
|
||||||
STORE x14, 9*REGBYTES(sp)
|
|
||||||
STORE x15, 10*REGBYTES(sp)
|
|
||||||
#ifndef __riscv_32e
|
|
||||||
STORE x16, 14*REGBYTES(sp)
|
|
||||||
STORE x17, 15*REGBYTES(sp)
|
|
||||||
STORE x28, 16*REGBYTES(sp)
|
|
||||||
STORE x29, 17*REGBYTES(sp)
|
|
||||||
STORE x30, 18*REGBYTES(sp)
|
|
||||||
STORE x31, 19*REGBYTES(sp)
|
|
||||||
#endif /* __riscv_32e */
|
|
||||||
.endm
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief Macro for restore caller registers
|
|
||||||
* \details
|
|
||||||
* This macro restore ABI defined caller saved registers from stack.
|
|
||||||
* \remarks
|
|
||||||
* - You could use this macro to restore context before you want return
|
|
||||||
* from interrupt or exeception
|
|
||||||
*/
|
|
||||||
/* Restore caller registers */
|
|
||||||
.macro RESTORE_CONTEXT
|
|
||||||
LOAD x1, 0*REGBYTES(sp)
|
|
||||||
LOAD x4, 1*REGBYTES(sp)
|
|
||||||
LOAD x5, 2*REGBYTES(sp)
|
|
||||||
LOAD x6, 3*REGBYTES(sp)
|
|
||||||
LOAD x7, 4*REGBYTES(sp)
|
|
||||||
LOAD x10, 5*REGBYTES(sp)
|
|
||||||
LOAD x11, 6*REGBYTES(sp)
|
|
||||||
LOAD x12, 7*REGBYTES(sp)
|
|
||||||
LOAD x13, 8*REGBYTES(sp)
|
|
||||||
LOAD x14, 9*REGBYTES(sp)
|
|
||||||
LOAD x15, 10*REGBYTES(sp)
|
|
||||||
#ifndef __riscv_32e
|
|
||||||
LOAD x16, 14*REGBYTES(sp)
|
|
||||||
LOAD x17, 15*REGBYTES(sp)
|
|
||||||
LOAD x28, 16*REGBYTES(sp)
|
|
||||||
LOAD x29, 17*REGBYTES(sp)
|
|
||||||
LOAD x30, 18*REGBYTES(sp)
|
|
||||||
LOAD x31, 19*REGBYTES(sp)
|
|
||||||
|
|
||||||
/* De-allocate the stack space */
|
|
||||||
addi sp, sp, 20*REGBYTES
|
|
||||||
#else
|
|
||||||
/* De-allocate the stack space */
|
|
||||||
addi sp, sp, 14*REGBYTES
|
|
||||||
#endif /* __riscv_32e */
|
|
||||||
|
|
||||||
.endm
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief Macro for save necessary CSRs to stack
|
|
||||||
* \details
|
|
||||||
* This macro store MCAUSE, MEPC, MSUBM to stack.
|
|
||||||
*/
|
|
||||||
.macro SAVE_CSR_CONTEXT
|
|
||||||
/* Store CSR mcause to stack using pushmcause */
|
|
||||||
csrrwi x0, CSR_PUSHMCAUSE, 11
|
|
||||||
/* Store CSR mepc to stack using pushmepc */
|
|
||||||
csrrwi x0, CSR_PUSHMEPC, 12
|
|
||||||
/* Store CSR msub to stack using pushmsub */
|
|
||||||
csrrwi x0, CSR_PUSHMSUBM, 13
|
|
||||||
.endm
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief Macro for restore necessary CSRs from stack
|
|
||||||
* \details
|
|
||||||
* This macro restore MSUBM, MEPC, MCAUSE from stack.
|
|
||||||
*/
|
|
||||||
.macro RESTORE_CSR_CONTEXT
|
|
||||||
LOAD x5, 13*REGBYTES(sp)
|
|
||||||
csrw CSR_MSUBM, x5
|
|
||||||
LOAD x5, 12*REGBYTES(sp)
|
|
||||||
csrw CSR_MEPC, x5
|
|
||||||
LOAD x5, 11*REGBYTES(sp)
|
|
||||||
csrw CSR_MCAUSE, x5
|
|
||||||
.endm
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief Exception/NMI Entry
|
|
||||||
* \details
|
|
||||||
* This function provide common entry functions for exception/nmi.
|
|
||||||
* \remarks
|
|
||||||
* This function provide a default exception/nmi entry.
|
|
||||||
* ABI defined caller save register and some CSR registers
|
|
||||||
* to be saved before enter interrupt handler and be restored before return.
|
|
||||||
*/
|
|
||||||
.section .text.trap
|
|
||||||
/* In CLIC mode, the exeception entry must be 64bytes aligned */
|
|
||||||
.align 6
|
|
||||||
.global exc_entry
|
|
||||||
.weak exc_entry
|
|
||||||
exc_entry:
|
|
||||||
/* Save the caller saving registers (context) */
|
|
||||||
SAVE_CONTEXT
|
|
||||||
/* Save the necessary CSR registers */
|
|
||||||
SAVE_CSR_CONTEXT
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Set the exception handler function arguments
|
|
||||||
* argument 1: mcause value
|
|
||||||
* argument 2: current stack point(SP) value
|
|
||||||
*/
|
|
||||||
csrr a0, mcause
|
|
||||||
mv a1, sp
|
|
||||||
/*
|
|
||||||
* By default, the function template is provided in
|
|
||||||
* system_Device.c, you can adjust it as you want
|
|
||||||
*/
|
|
||||||
call core_exception_handler
|
|
||||||
|
|
||||||
/* Restore the necessary CSR registers */
|
|
||||||
RESTORE_CSR_CONTEXT
|
|
||||||
/* Restore the caller saving registers (context) */
|
|
||||||
RESTORE_CONTEXT
|
|
||||||
|
|
||||||
/* Return to regular code */
|
|
||||||
mret
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief Non-Vector Interrupt Entry
|
|
||||||
* \details
|
|
||||||
* This function provide common entry functions for handling
|
|
||||||
* non-vector interrupts
|
|
||||||
* \remarks
|
|
||||||
* This function provide a default non-vector interrupt entry.
|
|
||||||
* ABI defined caller save register and some CSR registers need
|
|
||||||
* to be saved before enter interrupt handler and be restored before return.
|
|
||||||
*/
|
|
||||||
.section .text.irq
|
|
||||||
/* In CLIC mode, the interrupt entry must be 4bytes aligned */
|
|
||||||
.align 2
|
|
||||||
.global irq_entry
|
|
||||||
.weak irq_entry
|
|
||||||
/* This label will be set to MTVT2 register */
|
|
||||||
irq_entry:
|
|
||||||
/* Save the caller saving registers (context) */
|
|
||||||
SAVE_CONTEXT
|
|
||||||
/* Save the necessary CSR registers */
|
|
||||||
SAVE_CSR_CONTEXT
|
|
||||||
|
|
||||||
/* This special CSR read/write operation, which is actually
|
|
||||||
* claim the CLIC to find its pending highest ID, if the ID
|
|
||||||
* is not 0, then automatically enable the mstatus.MIE, and
|
|
||||||
* jump to its vector-entry-label, and update the link register
|
|
||||||
*/
|
|
||||||
csrrw ra, CSR_JALMNXTI, ra
|
|
||||||
|
|
||||||
/* Critical section with interrupts disabled */
|
|
||||||
DISABLE_MIE
|
|
||||||
|
|
||||||
/* Restore the necessary CSR registers */
|
|
||||||
RESTORE_CSR_CONTEXT
|
|
||||||
/* Restore the caller saving registers (context) */
|
|
||||||
RESTORE_CONTEXT
|
|
||||||
|
|
||||||
/* Return to regular code */
|
|
||||||
mret
|
|
||||||
|
|
||||||
/* Default Handler for Exceptions / Interrupts */
|
|
||||||
.global default_intexc_handler
|
|
||||||
.weak default_intexc_handler
|
|
||||||
Undef_Handler:
|
|
||||||
default_intexc_handler:
|
|
||||||
1:
|
|
||||||
j 1b
|
|
||||||
|
|
@ -1,306 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2019 Nuclei Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
|
||||||
* not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
|
||||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*/
|
|
||||||
/******************************************************************************
|
|
||||||
* \file startup_demosoc.S
|
|
||||||
* \brief NMSIS Nuclei N/NX Class Core based Core Device Startup File for
|
|
||||||
* Nuclei Demo SoC which support Nuclei N/NX class cores
|
|
||||||
* \version V1.00
|
|
||||||
* \date 17. Dec 2019
|
|
||||||
*
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
#include "riscv_encoding.h"
|
|
||||||
|
|
||||||
.macro DECLARE_INT_HANDLER INT_HDL_NAME
|
|
||||||
#if defined(__riscv_xlen) && (__riscv_xlen == 32)
|
|
||||||
.word \INT_HDL_NAME
|
|
||||||
#else
|
|
||||||
.dword \INT_HDL_NAME
|
|
||||||
#endif
|
|
||||||
.endm
|
|
||||||
|
|
||||||
/*
|
|
||||||
* === Different Download and Running Mode ===
|
|
||||||
* flashxip: Program will to be download into flash and run directly in Flash
|
|
||||||
* flash: Program will be download into flash, when running, program will be copied to ilm/ram and run in ilm/ram
|
|
||||||
* ilm: Program will be download into ilm/ram and run directly in ilm/ram, program lost when poweroff
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*** Vector Table Code Section ***/
|
|
||||||
/*
|
|
||||||
* Put the interrupt vectors in this section according to the run mode:
|
|
||||||
* FlashXIP: .vtable
|
|
||||||
* ILM: .vtable
|
|
||||||
* Flash: .vtable_ilm
|
|
||||||
*/
|
|
||||||
#if defined(DOWNLOAD_MODE) && (DOWNLOAD_MODE == DOWNLOAD_MODE_FLASH)
|
|
||||||
.section .vtable_ilm
|
|
||||||
#else
|
|
||||||
.section .vtable
|
|
||||||
#endif
|
|
||||||
|
|
||||||
.weak eclic_msip_handler
|
|
||||||
.weak eclic_mtip_handler
|
|
||||||
.weak eclic_irq19_handler
|
|
||||||
.weak eclic_irq20_handler
|
|
||||||
.weak eclic_irq21_handler
|
|
||||||
.weak eclic_irq22_handler
|
|
||||||
.weak eclic_irq23_handler
|
|
||||||
.weak eclic_irq24_handler
|
|
||||||
.weak eclic_irq25_handler
|
|
||||||
.weak eclic_irq26_handler
|
|
||||||
.weak eclic_irq27_handler
|
|
||||||
.weak eclic_irq28_handler
|
|
||||||
.weak eclic_irq29_handler
|
|
||||||
.weak eclic_irq30_handler
|
|
||||||
.weak eclic_irq31_handler
|
|
||||||
.weak eclic_irq32_handler
|
|
||||||
.weak eclic_irq33_handler
|
|
||||||
.weak eclic_irq34_handler
|
|
||||||
.weak eclic_irq35_handler
|
|
||||||
.weak eclic_irq36_handler
|
|
||||||
.weak eclic_irq37_handler
|
|
||||||
.weak eclic_irq38_handler
|
|
||||||
.weak eclic_irq39_handler
|
|
||||||
.weak eclic_irq40_handler
|
|
||||||
.weak eclic_irq41_handler
|
|
||||||
.weak eclic_irq42_handler
|
|
||||||
.weak eclic_irq43_handler
|
|
||||||
.weak eclic_irq44_handler
|
|
||||||
.weak eclic_irq45_handler
|
|
||||||
.weak eclic_irq46_handler
|
|
||||||
.weak eclic_irq47_handler
|
|
||||||
.weak eclic_irq48_handler
|
|
||||||
.weak eclic_irq49_handler
|
|
||||||
.weak eclic_irq50_handler
|
|
||||||
|
|
||||||
.globl vector_base
|
|
||||||
.type vector_base, @object
|
|
||||||
vector_base:
|
|
||||||
#if defined(DOWNLOAD_MODE) && (DOWNLOAD_MODE != DOWNLOAD_MODE_FLASH)
|
|
||||||
j _start /* 0: Reserved, Jump to _start when reset for ILM/FlashXIP mode.*/
|
|
||||||
.align LOG_REGBYTES /* Need to align 4 byte for RV32, 8 Byte for RV64 */
|
|
||||||
#else
|
|
||||||
DECLARE_INT_HANDLER default_intexc_handler /* 0: Reserved, default handler for Flash download mode */
|
|
||||||
#endif
|
|
||||||
DECLARE_INT_HANDLER default_intexc_handler /* 1: Reserved */
|
|
||||||
DECLARE_INT_HANDLER default_intexc_handler /* 2: Reserved */
|
|
||||||
DECLARE_INT_HANDLER eclic_msip_handler /* 3: Machine software interrupt */
|
|
||||||
|
|
||||||
DECLARE_INT_HANDLER default_intexc_handler /* 4: Reserved */
|
|
||||||
DECLARE_INT_HANDLER default_intexc_handler /* 5: Reserved */
|
|
||||||
DECLARE_INT_HANDLER default_intexc_handler /* 6: Reserved */
|
|
||||||
DECLARE_INT_HANDLER eclic_mtip_handler /* 7: Machine timer interrupt */
|
|
||||||
|
|
||||||
DECLARE_INT_HANDLER default_intexc_handler /* 8: Reserved */
|
|
||||||
DECLARE_INT_HANDLER default_intexc_handler /* 9: Reserved */
|
|
||||||
DECLARE_INT_HANDLER default_intexc_handler /* 10: Reserved */
|
|
||||||
DECLARE_INT_HANDLER default_intexc_handler /* 11: Reserved */
|
|
||||||
|
|
||||||
DECLARE_INT_HANDLER default_intexc_handler /* 12: Reserved */
|
|
||||||
DECLARE_INT_HANDLER default_intexc_handler /* 13: Reserved */
|
|
||||||
DECLARE_INT_HANDLER default_intexc_handler /* 14: Reserved */
|
|
||||||
DECLARE_INT_HANDLER default_intexc_handler /* 15: Reserved */
|
|
||||||
|
|
||||||
DECLARE_INT_HANDLER default_intexc_handler /* 16: Reserved */
|
|
||||||
DECLARE_INT_HANDLER default_intexc_handler /* 17: Reserved */
|
|
||||||
DECLARE_INT_HANDLER default_intexc_handler /* 18: Reserved */
|
|
||||||
DECLARE_INT_HANDLER eclic_irq19_handler /* 19: Interrupt 19 */
|
|
||||||
|
|
||||||
DECLARE_INT_HANDLER eclic_irq20_handler /* 20: Interrupt 20 */
|
|
||||||
DECLARE_INT_HANDLER eclic_irq21_handler /* 21: Interrupt 21 */
|
|
||||||
DECLARE_INT_HANDLER eclic_irq22_handler /* 22: Interrupt 22 */
|
|
||||||
DECLARE_INT_HANDLER eclic_irq23_handler /* 23: Interrupt 23 */
|
|
||||||
|
|
||||||
DECLARE_INT_HANDLER eclic_irq24_handler /* 24: Interrupt 24 */
|
|
||||||
DECLARE_INT_HANDLER eclic_irq25_handler /* 25: Interrupt 25 */
|
|
||||||
DECLARE_INT_HANDLER eclic_irq26_handler /* 26: Interrupt 26 */
|
|
||||||
DECLARE_INT_HANDLER eclic_irq27_handler /* 27: Interrupt 27 */
|
|
||||||
|
|
||||||
DECLARE_INT_HANDLER eclic_irq28_handler /* 28: Interrupt 28 */
|
|
||||||
DECLARE_INT_HANDLER eclic_irq29_handler /* 29: Interrupt 29 */
|
|
||||||
DECLARE_INT_HANDLER eclic_irq30_handler /* 30: Interrupt 30 */
|
|
||||||
DECLARE_INT_HANDLER eclic_irq31_handler /* 31: Interrupt 31 */
|
|
||||||
|
|
||||||
DECLARE_INT_HANDLER eclic_irq32_handler /* 32: Interrupt 32 */
|
|
||||||
DECLARE_INT_HANDLER eclic_irq33_handler /* 33: Interrupt 33 */
|
|
||||||
DECLARE_INT_HANDLER eclic_irq34_handler /* 34: Interrupt 34 */
|
|
||||||
DECLARE_INT_HANDLER eclic_irq35_handler /* 35: Interrupt 35 */
|
|
||||||
|
|
||||||
DECLARE_INT_HANDLER eclic_irq36_handler /* 36: Interrupt 36 */
|
|
||||||
DECLARE_INT_HANDLER eclic_irq37_handler /* 37: Interrupt 37 */
|
|
||||||
DECLARE_INT_HANDLER eclic_irq38_handler /* 38: Interrupt 38 */
|
|
||||||
DECLARE_INT_HANDLER eclic_irq39_handler /* 39: Interrupt 39 */
|
|
||||||
|
|
||||||
DECLARE_INT_HANDLER eclic_irq40_handler /* 40: Interrupt 40 */
|
|
||||||
DECLARE_INT_HANDLER eclic_irq41_handler /* 41: Interrupt 41 */
|
|
||||||
DECLARE_INT_HANDLER eclic_irq42_handler /* 42: Interrupt 42 */
|
|
||||||
DECLARE_INT_HANDLER eclic_irq43_handler /* 43: Interrupt 43 */
|
|
||||||
|
|
||||||
DECLARE_INT_HANDLER eclic_irq44_handler /* 44: Interrupt 44 */
|
|
||||||
DECLARE_INT_HANDLER eclic_irq45_handler /* 45: Interrupt 45 */
|
|
||||||
DECLARE_INT_HANDLER eclic_irq46_handler /* 46: Interrupt 46 */
|
|
||||||
DECLARE_INT_HANDLER eclic_irq47_handler /* 47: Interrupt 47 */
|
|
||||||
|
|
||||||
DECLARE_INT_HANDLER eclic_irq48_handler /* 48: Interrupt 48 */
|
|
||||||
DECLARE_INT_HANDLER eclic_irq49_handler /* 49: Interrupt 49 */
|
|
||||||
DECLARE_INT_HANDLER eclic_irq50_handler /* 50: Interrupt 50 */
|
|
||||||
|
|
||||||
|
|
||||||
.section .init
|
|
||||||
|
|
||||||
.globl _start
|
|
||||||
.type _start, @function
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Reset Handler called on controller reset
|
|
||||||
*/
|
|
||||||
_start:
|
|
||||||
/* ===== Startup Stage 1 ===== */
|
|
||||||
/* Disable Global Interrupt */
|
|
||||||
csrc CSR_MSTATUS, MSTATUS_MIE
|
|
||||||
|
|
||||||
/* Initialize GP and Stack Pointer SP */
|
|
||||||
.option push
|
|
||||||
.option norelax
|
|
||||||
la gp, __global_pointer$
|
|
||||||
.option pop
|
|
||||||
la sp, _sp
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Set the the NMI base mnvec to share
|
|
||||||
* with mtvec by setting CSR_MMISC_CTL
|
|
||||||
* bit 9 NMI_CAUSE_FFF to 1
|
|
||||||
*/
|
|
||||||
li t0, MMISC_CTL_NMI_CAUSE_FFF
|
|
||||||
csrs CSR_MMISC_CTL, t0
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Initialize ECLIC vector interrupt
|
|
||||||
* base address mtvt to vector_base
|
|
||||||
*/
|
|
||||||
la t0, vector_base
|
|
||||||
csrw CSR_MTVT, t0
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Set ECLIC non-vector entry to be controlled
|
|
||||||
* by mtvt2 CSR register.
|
|
||||||
* Initialize ECLIC non-vector interrupt
|
|
||||||
* base address mtvt2 to irq_entry.
|
|
||||||
*/
|
|
||||||
la t0, irq_entry
|
|
||||||
csrw CSR_MTVT2, t0
|
|
||||||
csrs CSR_MTVT2, 0x1
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Set Exception Entry MTVEC to exc_entry
|
|
||||||
* Due to settings above, Exception and NMI
|
|
||||||
* will share common entry.
|
|
||||||
*/
|
|
||||||
la t0, exc_entry
|
|
||||||
csrw CSR_MTVEC, t0
|
|
||||||
|
|
||||||
/* Set the interrupt processing mode to ECLIC mode */
|
|
||||||
li t0, 0x3f
|
|
||||||
csrc CSR_MTVEC, t0
|
|
||||||
csrs CSR_MTVEC, 0x3
|
|
||||||
|
|
||||||
/* ===== Startup Stage 2 ===== */
|
|
||||||
|
|
||||||
#ifdef __riscv_flen
|
|
||||||
/* Enable FPU */
|
|
||||||
li t0, MSTATUS_FS
|
|
||||||
csrs mstatus, t0
|
|
||||||
csrw fcsr, x0
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Enable mcycle and minstret counter */
|
|
||||||
csrci CSR_MCOUNTINHIBIT, 0x5
|
|
||||||
|
|
||||||
/* ===== Startup Stage 3 ===== */
|
|
||||||
/*
|
|
||||||
* Load code section from FLASH to ILM
|
|
||||||
* when code LMA is different with VMA
|
|
||||||
*/
|
|
||||||
la a0, _ilm_lma
|
|
||||||
la a1, _ilm
|
|
||||||
/* If the ILM phy-address same as the logic-address, then quit */
|
|
||||||
beq a0, a1, 2f
|
|
||||||
la a2, _eilm
|
|
||||||
bgeu a1, a2, 2f
|
|
||||||
|
|
||||||
1:
|
|
||||||
/* Load code section if necessary */
|
|
||||||
lw t0, (a0)
|
|
||||||
sw t0, (a1)
|
|
||||||
addi a0, a0, 4
|
|
||||||
addi a1, a1, 4
|
|
||||||
bltu a1, a2, 1b
|
|
||||||
2:
|
|
||||||
/* Load data section */
|
|
||||||
la a0, _data_lma
|
|
||||||
la a1, _data
|
|
||||||
la a2, _edata
|
|
||||||
bgeu a1, a2, 2f
|
|
||||||
1:
|
|
||||||
lw t0, (a0)
|
|
||||||
sw t0, (a1)
|
|
||||||
addi a0, a0, 4
|
|
||||||
addi a1, a1, 4
|
|
||||||
bltu a1, a2, 1b
|
|
||||||
2:
|
|
||||||
/* Clear bss section */
|
|
||||||
la a0, __bss_start
|
|
||||||
la a1, _end
|
|
||||||
bgeu a0, a1, 2f
|
|
||||||
1:
|
|
||||||
sw zero, (a0)
|
|
||||||
addi a0, a0, 4
|
|
||||||
bltu a0, a1, 1b
|
|
||||||
2:
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Call vendor defined SystemInit to
|
|
||||||
* initialize the micro-controller system
|
|
||||||
*/
|
|
||||||
call SystemInit
|
|
||||||
|
|
||||||
/* Call global constructors */
|
|
||||||
la a0, __libc_fini_array
|
|
||||||
call atexit
|
|
||||||
/* Call C/C++ constructor start up code */
|
|
||||||
call __libc_init_array
|
|
||||||
|
|
||||||
/* do pre-init steps before main */
|
|
||||||
call _premain_init
|
|
||||||
/* ===== Call Main Function ===== */
|
|
||||||
/* argc = argv = 0 */
|
|
||||||
li a0, 0
|
|
||||||
li a1, 0
|
|
||||||
|
|
||||||
#ifdef RTOS_RTTHREAD
|
|
||||||
// Call entry function when using RT-Thread
|
|
||||||
call entry
|
|
||||||
#else
|
|
||||||
call main
|
|
||||||
#endif
|
|
||||||
/* do post-main steps after main */
|
|
||||||
call _postmain_fini
|
|
||||||
|
|
||||||
1:
|
|
||||||
j 1b
|
|
||||||
|
|
@ -1,14 +0,0 @@
|
||||||
/* See LICENSE of license details. */
|
|
||||||
#include "nuclei_sdk_soc.h"
|
|
||||||
#include <errno.h>
|
|
||||||
#include <time.h>
|
|
||||||
#include <stdint.h>
|
|
||||||
|
|
||||||
/* Get resolution of clock. */
|
|
||||||
__WEAK int clock_getres(clockid_t clock_id, struct timespec* res)
|
|
||||||
{
|
|
||||||
res->tv_sec = 0;
|
|
||||||
res->tv_nsec = 1000000000 / SystemCoreClock;
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
@ -1,21 +0,0 @@
|
||||||
/* See LICENSE of license details. */
|
|
||||||
#include "nuclei_sdk_soc.h"
|
|
||||||
#include <errno.h>
|
|
||||||
#include <time.h>
|
|
||||||
#include <sys/time.h>
|
|
||||||
|
|
||||||
extern int _gettimeofday(struct timeval* tp, void* tzp);
|
|
||||||
|
|
||||||
/* Get current value of CLOCK and store it in tp. */
|
|
||||||
__WEAK int clock_gettime(clockid_t clock_id, struct timespec* tp)
|
|
||||||
{
|
|
||||||
struct timeval tv;
|
|
||||||
int retval = -1;
|
|
||||||
|
|
||||||
retval = _gettimeofday(&tv, NULL);
|
|
||||||
if (retval == 0) {
|
|
||||||
TIMEVAL_TO_TIMESPEC(&tv, tp);
|
|
||||||
}
|
|
||||||
|
|
||||||
return retval;
|
|
||||||
}
|
|
||||||
|
|
@ -1,10 +0,0 @@
|
||||||
/* See LICENSE of license details. */
|
|
||||||
#include "nuclei_sdk_soc.h"
|
|
||||||
#include <errno.h>
|
|
||||||
#include <time.h>
|
|
||||||
|
|
||||||
/* Set CLOCK to value TP. */
|
|
||||||
__WEAK int clock_settime(clockid_t clock_id, const struct timespec* tp)
|
|
||||||
{
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
|
|
@ -1,12 +0,0 @@
|
||||||
/* See LICENSE of license details. */
|
|
||||||
#include "nuclei_sdk_soc.h"
|
|
||||||
#include <errno.h>
|
|
||||||
|
|
||||||
#undef errno
|
|
||||||
extern int errno;
|
|
||||||
|
|
||||||
__WEAK int _close(int fd)
|
|
||||||
{
|
|
||||||
errno = EBADF;
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
|
|
@ -1,12 +0,0 @@
|
||||||
/* See LICENSE of license details. */
|
|
||||||
#include "nuclei_sdk_soc.h"
|
|
||||||
#include <errno.h>
|
|
||||||
|
|
||||||
#undef errno
|
|
||||||
extern int errno;
|
|
||||||
|
|
||||||
__WEAK int _execve(char* name, char** argv, char** env)
|
|
||||||
{
|
|
||||||
errno = ENOMEM;
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
|
|
@ -1,9 +0,0 @@
|
||||||
/* See LICENSE of license details. */
|
|
||||||
#include "nuclei_sdk_soc.h"
|
|
||||||
|
|
||||||
__WEAK void _exit(int fd)
|
|
||||||
{
|
|
||||||
while (1) {
|
|
||||||
__WFI();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
@ -1,12 +0,0 @@
|
||||||
/* See LICENSE of license details. */
|
|
||||||
#include "nuclei_sdk_soc.h"
|
|
||||||
#include <errno.h>
|
|
||||||
|
|
||||||
#undef errno
|
|
||||||
extern int errno;
|
|
||||||
|
|
||||||
__WEAK int _fork(void)
|
|
||||||
{
|
|
||||||
errno = EAGAIN;
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
|
|
@ -1,19 +0,0 @@
|
||||||
/* See LICENSE of license details. */
|
|
||||||
#include "nuclei_sdk_soc.h"
|
|
||||||
#include <errno.h>
|
|
||||||
#include <sys/stat.h>
|
|
||||||
#include <unistd.h>
|
|
||||||
|
|
||||||
#undef errno
|
|
||||||
extern int errno;
|
|
||||||
|
|
||||||
__WEAK int _fstat(int file, struct stat* st)
|
|
||||||
{
|
|
||||||
if ((STDOUT_FILENO == file) || (STDERR_FILENO == file)) {
|
|
||||||
st->st_mode = S_IFCHR;
|
|
||||||
return 0;
|
|
||||||
} else {
|
|
||||||
errno = EBADF;
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
@ -1,8 +0,0 @@
|
||||||
/* See LICENSE of license details. */
|
|
||||||
#include "nuclei_sdk_soc.h"
|
|
||||||
#include <errno.h>
|
|
||||||
|
|
||||||
__WEAK int _getpid(void)
|
|
||||||
{
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
@ -1,15 +0,0 @@
|
||||||
/* See LICENSE of license details. */
|
|
||||||
#include <errno.h>
|
|
||||||
#include <sys/time.h>
|
|
||||||
#include "nuclei_sdk_soc.h"
|
|
||||||
|
|
||||||
__WEAK int _gettimeofday(struct timeval* tp, void* tzp)
|
|
||||||
{
|
|
||||||
uint64_t cycles;
|
|
||||||
|
|
||||||
cycles = __get_rv_cycle();
|
|
||||||
|
|
||||||
tp->tv_sec = cycles / SystemCoreClock;
|
|
||||||
tp->tv_usec = (cycles % SystemCoreClock) * 1000000 / SystemCoreClock;
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
@ -1,8 +0,0 @@
|
||||||
/* See LICENSE of license details. */
|
|
||||||
#include "nuclei_sdk_soc.h"
|
|
||||||
#include <unistd.h>
|
|
||||||
|
|
||||||
__WEAK int _isatty(int fd)
|
|
||||||
{
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
@ -1,11 +0,0 @@
|
||||||
/* See LICENSE of license details. */
|
|
||||||
#include "nuclei_sdk_soc.h"
|
|
||||||
#include <errno.h>
|
|
||||||
#undef errno
|
|
||||||
extern int errno;
|
|
||||||
|
|
||||||
__WEAK int _kill(int pid, int sig)
|
|
||||||
{
|
|
||||||
errno = EINVAL;
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
|
|
@ -1,12 +0,0 @@
|
||||||
/* See LICENSE of license details. */
|
|
||||||
#include "nuclei_sdk_soc.h"
|
|
||||||
#include <errno.h>
|
|
||||||
|
|
||||||
#undef errno
|
|
||||||
extern int errno;
|
|
||||||
|
|
||||||
int _link(char* old, char* new)
|
|
||||||
{
|
|
||||||
errno = EMLINK;
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
|
|
@ -1,11 +0,0 @@
|
||||||
/* See LICENSE of license details. */
|
|
||||||
#include "nuclei_sdk_soc.h"
|
|
||||||
#include <errno.h>
|
|
||||||
|
|
||||||
#undef errno
|
|
||||||
extern int errno;
|
|
||||||
|
|
||||||
__WEAK int _lseek(int file, int offset, int whence)
|
|
||||||
{
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
@ -1,12 +0,0 @@
|
||||||
/* See LICENSE of license details. */
|
|
||||||
#include "nuclei_sdk_soc.h"
|
|
||||||
#include <errno.h>
|
|
||||||
|
|
||||||
#undef errno
|
|
||||||
extern int errno;
|
|
||||||
|
|
||||||
__WEAK int _open(const char* name, int flags, int mode)
|
|
||||||
{
|
|
||||||
errno = ENOSYS;
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
|
|
@ -1,22 +0,0 @@
|
||||||
/* See LICENSE of license details. */
|
|
||||||
#include <stdint.h>
|
|
||||||
#include <errno.h>
|
|
||||||
#include <unistd.h>
|
|
||||||
#include <sys/types.h>
|
|
||||||
#include "nuclei_sdk_hal.h"
|
|
||||||
|
|
||||||
// #define UART_AUTO_ECHO
|
|
||||||
|
|
||||||
__WEAK ssize_t _read(int fd, void* ptr, size_t len)
|
|
||||||
{
|
|
||||||
if (fd != STDIN_FILENO) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint8_t* readbuf = (uint8_t*)ptr;
|
|
||||||
readbuf[0] = uart_read(SOC_DEBUG_UART);
|
|
||||||
#ifdef UART_AUTO_ECHO
|
|
||||||
uart_write(SOC_DEBUG_UART, readbuf[0]);
|
|
||||||
#endif
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
@ -1,19 +0,0 @@
|
||||||
/* See LICENSE of license details. */
|
|
||||||
#include "nuclei_sdk_soc.h"
|
|
||||||
#include <stdint.h>
|
|
||||||
#include <stddef.h>
|
|
||||||
#include <unistd.h>
|
|
||||||
|
|
||||||
__WEAK void* _sbrk(ptrdiff_t incr)
|
|
||||||
{
|
|
||||||
extern char _end[];
|
|
||||||
extern char _heap_end[];
|
|
||||||
static char* curbrk = _end;
|
|
||||||
|
|
||||||
if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) {
|
|
||||||
return (void*)(-1);
|
|
||||||
}
|
|
||||||
|
|
||||||
curbrk += incr;
|
|
||||||
return (void*)(curbrk - incr);
|
|
||||||
}
|
|
||||||
|
|
@ -1,9 +0,0 @@
|
||||||
/* See LICENSE of license details. */
|
|
||||||
#include "nuclei_sdk_soc.h"
|
|
||||||
#include <sys/stat.h>
|
|
||||||
|
|
||||||
__WEAK int _stat(char* file, struct stat* st)
|
|
||||||
{
|
|
||||||
st->st_mode = S_IFCHR;
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
@ -1,27 +0,0 @@
|
||||||
/* See LICENSE of license details. */
|
|
||||||
#include <sys/times.h>
|
|
||||||
#include <sys/time.h>
|
|
||||||
#include <time.h>
|
|
||||||
#include "nuclei_sdk_soc.h"
|
|
||||||
|
|
||||||
extern int _gettimeofday(struct timeval*, void*);
|
|
||||||
|
|
||||||
__WEAK clock_t _times(struct tms* buf)
|
|
||||||
{
|
|
||||||
static struct timeval t0;
|
|
||||||
struct timeval t;
|
|
||||||
long long utime;
|
|
||||||
|
|
||||||
/* When called for the first time, initialize t0. */
|
|
||||||
if (t0.tv_sec == 0 && t0.tv_usec == 0) {
|
|
||||||
_gettimeofday(&t0, 0);
|
|
||||||
}
|
|
||||||
|
|
||||||
_gettimeofday(&t, 0);
|
|
||||||
|
|
||||||
utime = (t.tv_sec - t0.tv_sec) * 1000000 + (t.tv_usec - t0.tv_usec);
|
|
||||||
buf->tms_utime = utime * CLOCKS_PER_SEC / 1000000;
|
|
||||||
buf->tms_stime = buf->tms_cstime = buf->tms_cutime = 0;
|
|
||||||
|
|
||||||
return buf->tms_utime;
|
|
||||||
}
|
|
||||||
|
|
@ -1,12 +0,0 @@
|
||||||
|
|
||||||
/* See LICENSE of license details. */
|
|
||||||
#include <errno.h>
|
|
||||||
#include <nuclei_sdk_hal.h>
|
|
||||||
|
|
||||||
#undef errno
|
|
||||||
extern int errno;
|
|
||||||
|
|
||||||
__WEAK int _unlink(const char* name)
|
|
||||||
{
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
|
|
@ -1,13 +0,0 @@
|
||||||
/* See LICENSE of license details. */
|
|
||||||
#include "nuclei_sdk_soc.h"
|
|
||||||
#include <sys/stat.h>
|
|
||||||
#include <errno.h>
|
|
||||||
|
|
||||||
#undef errno
|
|
||||||
extern int errno;
|
|
||||||
|
|
||||||
__WEAK int _wait(int* status)
|
|
||||||
{
|
|
||||||
errno = ECHILD;
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
|
|
@ -1,22 +0,0 @@
|
||||||
/* See LICENSE of license details. */
|
|
||||||
#include <stdint.h>
|
|
||||||
#include <errno.h>
|
|
||||||
#include <unistd.h>
|
|
||||||
#include <sys/types.h>
|
|
||||||
#include <nuclei_sdk_hal.h>
|
|
||||||
|
|
||||||
__WEAK ssize_t _write(int fd, const void* ptr, size_t len)
|
|
||||||
{
|
|
||||||
if (!isatty(fd)) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
|
|
||||||
const uint8_t* writebuf = (const uint8_t*)ptr;
|
|
||||||
for (size_t i = 0; i < len; i++) {
|
|
||||||
if (writebuf[i] == '\n') {
|
|
||||||
uart_write(SOC_DEBUG_UART, '\r');
|
|
||||||
}
|
|
||||||
uart_write(SOC_DEBUG_UART, writebuf[i]);
|
|
||||||
}
|
|
||||||
return len;
|
|
||||||
}
|
|
||||||
|
|
@ -1,69 +0,0 @@
|
||||||
#include "nuclei_sdk_soc.h"
|
|
||||||
|
|
||||||
static uint32_t get_timer_freq()
|
|
||||||
{
|
|
||||||
return SOC_TIMER_FREQ;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t measure_cpu_freq(uint32_t n)
|
|
||||||
{
|
|
||||||
uint32_t start_mcycle, delta_mcycle;
|
|
||||||
uint32_t start_mtime, delta_mtime;
|
|
||||||
uint32_t mtime_freq = get_timer_freq();
|
|
||||||
|
|
||||||
// Don't start measuruing until we see an mtime tick
|
|
||||||
uint32_t tmp = (uint32_t)SysTimer_GetLoadValue();
|
|
||||||
do {
|
|
||||||
start_mtime = (uint32_t)SysTimer_GetLoadValue();
|
|
||||||
start_mcycle = __RV_CSR_READ(CSR_MCYCLE);
|
|
||||||
} while (start_mtime == tmp);
|
|
||||||
|
|
||||||
do {
|
|
||||||
delta_mtime = (uint32_t)SysTimer_GetLoadValue() - start_mtime;
|
|
||||||
delta_mcycle = __RV_CSR_READ(CSR_MCYCLE) - start_mcycle;
|
|
||||||
} while (delta_mtime < n);
|
|
||||||
|
|
||||||
return (delta_mcycle / delta_mtime) * mtime_freq
|
|
||||||
+ ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t get_cpu_freq()
|
|
||||||
{
|
|
||||||
uint32_t cpu_freq;
|
|
||||||
|
|
||||||
// warm up
|
|
||||||
measure_cpu_freq(1);
|
|
||||||
// measure for real
|
|
||||||
cpu_freq = measure_cpu_freq(100);
|
|
||||||
|
|
||||||
return cpu_freq;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief delay a time in milliseconds
|
|
||||||
* \details
|
|
||||||
* provide API for delay
|
|
||||||
* \param[in] count: count in milliseconds
|
|
||||||
* \remarks
|
|
||||||
*/
|
|
||||||
void delay_1ms(uint32_t count)
|
|
||||||
{
|
|
||||||
uint64_t start_mtime, delta_mtime;
|
|
||||||
uint64_t delay_ticks = (SOC_TIMER_FREQ * (uint64_t)count) / 1000;
|
|
||||||
|
|
||||||
start_mtime = SysTimer_GetLoadValue();
|
|
||||||
|
|
||||||
do {
|
|
||||||
delta_mtime = SysTimer_GetLoadValue() - start_mtime;
|
|
||||||
} while (delta_mtime < delay_ticks);
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef SIMULATION_XLSPIKE
|
|
||||||
// never return for xlspike
|
|
||||||
void xlspike_exit(int status)
|
|
||||||
{
|
|
||||||
// pass exit status via rxfifo register
|
|
||||||
UART0->RXFIFO = status;
|
|
||||||
uart_write(UART0, 4);
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,389 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
|
||||||
* Copyright (c) 2019 Nuclei Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
|
||||||
* not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
|
||||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*/
|
|
||||||
/******************************************************************************
|
|
||||||
* @file system_demosoc.c
|
|
||||||
* @brief NMSIS Nuclei Core Device Peripheral Access Layer Source File for
|
|
||||||
* Nuclei Demo SoC which support Nuclei N/NX class cores
|
|
||||||
* @version V1.00
|
|
||||||
* @date 22. Nov 2019
|
|
||||||
******************************************************************************/
|
|
||||||
#include <stdint.h>
|
|
||||||
#include <stdio.h>
|
|
||||||
#include "nuclei_sdk_hal.h"
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------
|
|
||||||
Define clocks
|
|
||||||
*----------------------------------------------------------------------------*/
|
|
||||||
#ifndef SYSTEM_CLOCK
|
|
||||||
#define SYSTEM_CLOCK (80000000UL)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \defgroup NMSIS_Core_SystemConfig System Device Configuration
|
|
||||||
* \brief Functions for system and clock setup available in system_<device>.c.
|
|
||||||
* \details
|
|
||||||
* Nuclei provides a template file **system_Device.c** that must be adapted by
|
|
||||||
* the silicon vendor to match their actual device. As a <b>minimum requirement</b>,
|
|
||||||
* this file must provide:
|
|
||||||
* - A device-specific system configuration function, \ref SystemInit.
|
|
||||||
* - A global variable that contains the system frequency, \ref SystemCoreClock.
|
|
||||||
* - A global eclic configuration initialization, \ref ECLIC_Init.
|
|
||||||
* - Global c library \ref _init and \ref _fini functions called right before calling main function.
|
|
||||||
* - Vendor customized interrupt, exception and nmi handling code, see \ref NMSIS_Core_IntExcNMI_Handling
|
|
||||||
*
|
|
||||||
* The file configures the device and, typically, initializes the oscillator (PLL) that is part
|
|
||||||
* of the microcontroller device. This file might export other functions or variables that provide
|
|
||||||
* a more flexible configuration of the microcontroller system.
|
|
||||||
*
|
|
||||||
* And this file also provided common interrupt, exception and NMI exception handling framework template,
|
|
||||||
* Silicon vendor can customize these template code as they want.
|
|
||||||
*
|
|
||||||
* \note Please pay special attention to the static variable \c SystemCoreClock. This variable might be
|
|
||||||
* used throughout the whole system initialization and runtime to calculate frequency/time related values.
|
|
||||||
* Thus one must assure that the variable always reflects the actual system clock speed.
|
|
||||||
*
|
|
||||||
* \attention
|
|
||||||
* Be aware that a value stored to \c SystemCoreClock during low level initialization (i.e. \c SystemInit()) might get
|
|
||||||
* overwritten by C libray startup code and/or .bss section initialization.
|
|
||||||
* Thus its highly recommended to call \ref SystemCoreClockUpdate at the beginning of the user \c main() routine.
|
|
||||||
*
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------
|
|
||||||
System Core Clock Variable
|
|
||||||
*----------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* \brief Variable to hold the system core clock value
|
|
||||||
* \details
|
|
||||||
* Holds the system core clock, which is the system clock frequency supplied to the SysTick
|
|
||||||
* timer and the processor core clock. This variable can be used by debuggers to query the
|
|
||||||
* frequency of the debug timer or to configure the trace clock speed.
|
|
||||||
*
|
|
||||||
* \attention
|
|
||||||
* Compilers must be configured to avoid removing this variable in case the application
|
|
||||||
* program is not using it. Debugging systems require the variable to be physically
|
|
||||||
* present in memory so that it can be examined to configure the debugger.
|
|
||||||
*/
|
|
||||||
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Clock Frequency (Core Clock) */
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------
|
|
||||||
Clock functions
|
|
||||||
*----------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief Function to update the variable \ref SystemCoreClock
|
|
||||||
* \details
|
|
||||||
* Updates the variable \ref SystemCoreClock and must be called whenever the core clock is changed
|
|
||||||
* during program execution. The function evaluates the clock register settings and calculates
|
|
||||||
* the current core clock.
|
|
||||||
*/
|
|
||||||
void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */
|
|
||||||
{
|
|
||||||
/* Note: This function can be used to retrieve the system core clock frequeny
|
|
||||||
* after user changed register settings.
|
|
||||||
*/
|
|
||||||
SystemCoreClock = SYSTEM_CLOCK;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief Function to Initialize the system.
|
|
||||||
* \details
|
|
||||||
* Initializes the microcontroller system. Typically, this function configures the
|
|
||||||
* oscillator (PLL) that is part of the microcontroller device. For systems
|
|
||||||
* with a variable clock speed, it updates the variable \ref SystemCoreClock.
|
|
||||||
* SystemInit is called from the file <b>startup<i>_device</i></b>.
|
|
||||||
*/
|
|
||||||
void SystemInit(void)
|
|
||||||
{
|
|
||||||
/* Warn: do not use global variables because this function is called before
|
|
||||||
* reaching pre-main. RW section maybe overwritten afterwards.
|
|
||||||
*/
|
|
||||||
SystemCoreClock = SYSTEM_CLOCK;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \defgroup NMSIS_Core_IntExcNMI_Handling Interrupt and Exception and NMI Handling
|
|
||||||
* \brief Functions for interrupt, exception and nmi handle available in system_<device>.c.
|
|
||||||
* \details
|
|
||||||
* Nuclei provide a template for interrupt, exception and NMI handling. Silicon Vendor could adapat according
|
|
||||||
* to their requirement. Silicon vendor could implement interface for different exception code and
|
|
||||||
* replace current implementation.
|
|
||||||
*
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/** \brief Max exception handler number, don't include the NMI(0xFFF) one */
|
|
||||||
#define MAX_SYSTEM_EXCEPTION_NUM 12
|
|
||||||
/**
|
|
||||||
* \brief Store the exception handlers for each exception ID
|
|
||||||
* \note
|
|
||||||
* - This SystemExceptionHandlers are used to store all the handlers for all
|
|
||||||
* the exception codes Nuclei N/NX core provided.
|
|
||||||
* - Exception code 0 - 11, totally 12 exceptions are mapped to SystemExceptionHandlers[0:11]
|
|
||||||
* - Exception for NMI is also re-routed to exception handling(exception code 0xFFF) in startup code configuration, the handler itself is mapped to SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM]
|
|
||||||
*/
|
|
||||||
static unsigned long SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM + 1];
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief Exception Handler Function Typedef
|
|
||||||
* \note
|
|
||||||
* This typedef is only used internal in this system_<Device>.c file.
|
|
||||||
* It is used to do type conversion for registered exception handler before calling it.
|
|
||||||
*/
|
|
||||||
typedef void (*EXC_HANDLER)(unsigned long mcause, unsigned long sp);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief System Default Exception Handler
|
|
||||||
* \details
|
|
||||||
* This function provided a default exception and NMI handling code for all exception ids.
|
|
||||||
* By default, It will just print some information for debug, Vendor can customize it according to its requirements.
|
|
||||||
*/
|
|
||||||
static void system_default_exception_handler(unsigned long mcause, unsigned long sp)
|
|
||||||
{
|
|
||||||
printf("MCAUSE : 0x%lx\r\n", mcause);
|
|
||||||
printf("MDCAUSE: 0x%lx\r\n", __RV_CSR_READ(CSR_MDCAUSE));
|
|
||||||
printf("MEPC : 0x%lx\r\n", __RV_CSR_READ(CSR_MEPC));
|
|
||||||
printf("MTVAL : 0x%lx\r\n", __RV_CSR_READ(CSR_MTVAL));
|
|
||||||
while (1);
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief Initialize all the default core exception handlers
|
|
||||||
* \details
|
|
||||||
* The core exception handler for each exception id will be initialized to \ref system_default_exception_handler.
|
|
||||||
* \note
|
|
||||||
* Called in \ref _init function, used to initialize default exception handlers for all exception IDs
|
|
||||||
*/
|
|
||||||
static void Exception_Init(void)
|
|
||||||
{
|
|
||||||
for (int i = 0; i < MAX_SYSTEM_EXCEPTION_NUM + 1; i++) {
|
|
||||||
SystemExceptionHandlers[i] = (unsigned long)system_default_exception_handler;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief Register an exception handler for exception code EXCn
|
|
||||||
* \details
|
|
||||||
* * For EXCn < \ref MAX_SYSTEM_EXCEPTION_NUM, it will be registered into SystemExceptionHandlers[EXCn-1].
|
|
||||||
* * For EXCn == NMI_EXCn, it will be registered into SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM].
|
|
||||||
* \param EXCn See \ref EXCn_Type
|
|
||||||
* \param exc_handler The exception handler for this exception code EXCn
|
|
||||||
*/
|
|
||||||
void Exception_Register_EXC(uint32_t EXCn, unsigned long exc_handler)
|
|
||||||
{
|
|
||||||
if ((EXCn < MAX_SYSTEM_EXCEPTION_NUM) && (EXCn >= 0)) {
|
|
||||||
SystemExceptionHandlers[EXCn] = exc_handler;
|
|
||||||
} else if (EXCn == NMI_EXCn) {
|
|
||||||
SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM] = exc_handler;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief Get current exception handler for exception code EXCn
|
|
||||||
* \details
|
|
||||||
* * For EXCn < \ref MAX_SYSTEM_EXCEPTION_NUM, it will return SystemExceptionHandlers[EXCn-1].
|
|
||||||
* * For EXCn == NMI_EXCn, it will return SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM].
|
|
||||||
* \param EXCn See \ref EXCn_Type
|
|
||||||
* \return Current exception handler for exception code EXCn, if not found, return 0.
|
|
||||||
*/
|
|
||||||
unsigned long Exception_Get_EXC(uint32_t EXCn)
|
|
||||||
{
|
|
||||||
if ((EXCn < MAX_SYSTEM_EXCEPTION_NUM) && (EXCn >= 0)) {
|
|
||||||
return SystemExceptionHandlers[EXCn];
|
|
||||||
} else if (EXCn == NMI_EXCn) {
|
|
||||||
return SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM];
|
|
||||||
} else {
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief Common NMI and Exception handler entry
|
|
||||||
* \details
|
|
||||||
* This function provided a command entry for NMI and exception. Silicon Vendor could modify
|
|
||||||
* this template implementation according to requirement.
|
|
||||||
* \remarks
|
|
||||||
* - RISCV provided common entry for all types of exception. This is proposed code template
|
|
||||||
* for exception entry function, Silicon Vendor could modify the implementation.
|
|
||||||
* - For the core_exception_handler template, we provided exception register function \ref Exception_Register_EXC
|
|
||||||
* which can help developer to register your exception handler for specific exception number.
|
|
||||||
*/
|
|
||||||
uint32_t core_exception_handler(unsigned long mcause, unsigned long sp)
|
|
||||||
{
|
|
||||||
uint32_t EXCn = (uint32_t)(mcause & 0X00000fff);
|
|
||||||
EXC_HANDLER exc_handler;
|
|
||||||
|
|
||||||
if ((EXCn < MAX_SYSTEM_EXCEPTION_NUM) && (EXCn >= 0)) {
|
|
||||||
exc_handler = (EXC_HANDLER)SystemExceptionHandlers[EXCn];
|
|
||||||
} else if (EXCn == NMI_EXCn) {
|
|
||||||
exc_handler = (EXC_HANDLER)SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM];
|
|
||||||
} else {
|
|
||||||
exc_handler = (EXC_HANDLER)system_default_exception_handler;
|
|
||||||
}
|
|
||||||
if (exc_handler != NULL) {
|
|
||||||
exc_handler(mcause, sp);
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
/** @} */ /* End of Doxygen Group NMSIS_Core_ExceptionAndNMI */
|
|
||||||
|
|
||||||
/** Banner Print for Nuclei SDK */
|
|
||||||
void SystemBannerPrint(void)
|
|
||||||
{
|
|
||||||
#if defined(NUCLEI_BANNER) && (NUCLEI_BANNER == 1)
|
|
||||||
#ifndef DOWNLOAD_MODE
|
|
||||||
#error DOWNLOAD_MODE is not defined via build system, please check!
|
|
||||||
#endif
|
|
||||||
const char* download_modes[] = {"FLASHXIP", "FLASH", "ILM", "DDR"};
|
|
||||||
printf("Nuclei SDK Build Time: %s, %s\r\n", __DATE__, __TIME__);
|
|
||||||
printf("Download Mode: %s\r\n", download_modes[DOWNLOAD_MODE]);
|
|
||||||
printf("CPU Frequency %lu Hz\r\n", SystemCoreClock);
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief initialize eclic config
|
|
||||||
* \details
|
|
||||||
* ECLIC needs be initialized after boot up,
|
|
||||||
* Vendor could also change the initialization
|
|
||||||
* configuration.
|
|
||||||
*/
|
|
||||||
void ECLIC_Init(void)
|
|
||||||
{
|
|
||||||
/* Global Configuration about MTH and NLBits.
|
|
||||||
* This function is called in _init function */
|
|
||||||
ECLIC_SetMth(0);
|
|
||||||
ECLIC_SetCfgNlbits(__ECLIC_INTCTLBITS);
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief Initialize a specific IRQ and register the handler
|
|
||||||
* \details
|
|
||||||
* This function set vector mode, trigger mode and polarity, interrupt level and priority,
|
|
||||||
* assign handler for specific IRQn.
|
|
||||||
* \param [in] IRQn NMI interrupt handler address
|
|
||||||
* \param [in] shv \ref ECLIC_NON_VECTOR_INTERRUPT means non-vector mode, and \ref ECLIC_VECTOR_INTERRUPT is vector mode
|
|
||||||
* \param [in] trig_mode see \ref ECLIC_TRIGGER_Type
|
|
||||||
* \param [in] lvl interrupt level
|
|
||||||
* \param [in] priority interrupt priority
|
|
||||||
* \param [in] handler interrupt handler, if NULL, handler will not be installed
|
|
||||||
* \return -1 means invalid input parameter. 0 means successful.
|
|
||||||
* \remarks
|
|
||||||
* - This function use to configure specific eclic interrupt and register its interrupt handler and enable its interrupt.
|
|
||||||
* - If the vector table is placed in read-only section(FLASHXIP mode), handler could not be installed
|
|
||||||
*/
|
|
||||||
int32_t ECLIC_Register_IRQ(IRQn_Type IRQn, uint8_t shv, ECLIC_TRIGGER_Type trig_mode, uint8_t lvl, uint8_t priority, void* handler)
|
|
||||||
{
|
|
||||||
if ((IRQn > SOC_INT_MAX) || (shv > ECLIC_VECTOR_INTERRUPT) \
|
|
||||||
|| (trig_mode > ECLIC_NEGTIVE_EDGE_TRIGGER)) {
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* set interrupt vector mode */
|
|
||||||
ECLIC_SetShvIRQ(IRQn, shv);
|
|
||||||
/* set interrupt trigger mode and polarity */
|
|
||||||
ECLIC_SetTrigIRQ(IRQn, trig_mode);
|
|
||||||
/* set interrupt level */
|
|
||||||
ECLIC_SetLevelIRQ(IRQn, lvl);
|
|
||||||
/* set interrupt priority */
|
|
||||||
ECLIC_SetPriorityIRQ(IRQn, priority);
|
|
||||||
if (handler != NULL) {
|
|
||||||
/* set interrupt handler entry to vector table */
|
|
||||||
ECLIC_SetVector(IRQn, (rv_csr_t)handler);
|
|
||||||
}
|
|
||||||
/* enable interrupt */
|
|
||||||
ECLIC_EnableIRQ(IRQn);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
/** @} */ /* End of Doxygen Group NMSIS_Core_ExceptionAndNMI */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief early init function before main
|
|
||||||
* \details
|
|
||||||
* This function is executed right before main function.
|
|
||||||
* For RISC-V gnu toolchain, _init function might not be called
|
|
||||||
* by __libc_init_array function, so we defined a new function
|
|
||||||
* to do initialization
|
|
||||||
*/
|
|
||||||
void _premain_init(void)
|
|
||||||
{
|
|
||||||
/* __ICACHE_PRESENT and __DCACHE_PRESENT are defined in demosoc.h */
|
|
||||||
#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT == 1
|
|
||||||
EnableICache();
|
|
||||||
#endif
|
|
||||||
#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT == 1
|
|
||||||
EnableDCache();
|
|
||||||
#endif
|
|
||||||
SystemCoreClock = get_cpu_freq();
|
|
||||||
gpio_iof_config(GPIO, IOF0_UART0_MASK, IOF_SEL_0);
|
|
||||||
uart_init(SOC_DEBUG_UART, 115200);
|
|
||||||
/* Display banner after UART initialized */
|
|
||||||
SystemBannerPrint();
|
|
||||||
/* Initialize exception default handlers */
|
|
||||||
Exception_Init();
|
|
||||||
/* ECLIC initialization, mainly MTH and NLBIT */
|
|
||||||
ECLIC_Init();
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief finish function after main
|
|
||||||
* \param [in] status status code return from main
|
|
||||||
* \details
|
|
||||||
* This function is executed right after main function.
|
|
||||||
* For RISC-V gnu toolchain, _fini function might not be called
|
|
||||||
* by __libc_fini_array function, so we defined a new function
|
|
||||||
* to do initialization
|
|
||||||
*/
|
|
||||||
void _postmain_fini(int status)
|
|
||||||
{
|
|
||||||
#ifdef SIMULATION_XLSPIKE
|
|
||||||
extern void xlspike_exit(int status);
|
|
||||||
xlspike_exit(status);
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief _init function called in __libc_init_array()
|
|
||||||
* \details
|
|
||||||
* This `__libc_init_array()` function is called during startup code,
|
|
||||||
* user need to implement this function, otherwise when link it will
|
|
||||||
* error init.c:(.text.__libc_init_array+0x26): undefined reference to `_init'
|
|
||||||
* \note
|
|
||||||
* Please use \ref _premain_init function now
|
|
||||||
*/
|
|
||||||
void _init(void)
|
|
||||||
{
|
|
||||||
/* Don't put any code here, please use _premain_init now */
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief _fini function called in __libc_fini_array()
|
|
||||||
* \details
|
|
||||||
* This `__libc_fini_array()` function is called when exit main.
|
|
||||||
* user need to implement this function, otherwise when link it will
|
|
||||||
* error fini.c:(.text.__libc_fini_array+0x28): undefined reference to `_fini'
|
|
||||||
* \note
|
|
||||||
* Please use \ref _postmain_fini function now
|
|
||||||
*/
|
|
||||||
void _fini(void)
|
|
||||||
{
|
|
||||||
/* Don't put any code here, please use _postmain_fini now */
|
|
||||||
}
|
|
||||||
|
|
||||||
/** @} */ /* End of Doxygen Group NMSIS_Core_SystemAndClock */
|
|
||||||
|
|
@ -1,34 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file : main.c
|
|
||||||
* @brief : Main program body
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* Copyright (c) 2021 Nuclei Limited. All rights reserved.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include <stdio.h>
|
|
||||||
#include "nuclei_sdk_hal.h"
|
|
||||||
#include "task_sample.h"
|
|
||||||
#include "target_config.h"
|
|
||||||
/**
|
|
||||||
* @brief The application entry point.
|
|
||||||
* @retval int
|
|
||||||
*/
|
|
||||||
int main(void)
|
|
||||||
{
|
|
||||||
/* USER CODE BEGIN Init */
|
|
||||||
RunTaskSample();
|
|
||||||
while (1) {
|
|
||||||
}
|
|
||||||
}
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,106 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
|
||||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
|
||||||
* Copyright (c) 2021 Nuclei Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
* are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
|
||||||
* conditions and the following disclaimer.
|
|
||||||
*
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
|
||||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
|
||||||
* provided with the distribution.
|
|
||||||
*
|
|
||||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
|
||||||
* to endorse or promote products derived from this software without specific prior written
|
|
||||||
* permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
||||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
|
||||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
|
||||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
|
||||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
|
||||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
|
||||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
|
||||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
|
||||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
|
||||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
* Description: Provide a task example.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "task_sample.h"
|
|
||||||
#include "los_config.h"
|
|
||||||
#include "los_debug.h"
|
|
||||||
#include "los_interrupt.h"
|
|
||||||
#include "los_task.h"
|
|
||||||
#include "los_tick.h"
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
#if __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif /* __cplusplus */
|
|
||||||
#endif /* __cplusplus */
|
|
||||||
|
|
||||||
UINT8 __attribute__ ((aligned (8))) g_memStart[OS_SYS_MEM_SIZE];
|
|
||||||
|
|
||||||
VOID TaskSampleEntry2(VOID)
|
|
||||||
{
|
|
||||||
while (1) {
|
|
||||||
printf("TaskSampleEntry2 running...\n");
|
|
||||||
LOS_TaskDelay(10000); /* 10 Seconds */
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
VOID TaskSampleEntry1(VOID)
|
|
||||||
{
|
|
||||||
while (1) {
|
|
||||||
printf("TaskSampleEntry1 running...\n");
|
|
||||||
LOS_TaskDelay(2000); /* 2 Seconds */
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
VOID TaskSample(VOID)
|
|
||||||
{
|
|
||||||
UINT32 uwRet;
|
|
||||||
UINT32 taskID1;
|
|
||||||
UINT32 taskID2;
|
|
||||||
TSK_INIT_PARAM_S stTask = {0};
|
|
||||||
|
|
||||||
stTask.pfnTaskEntry = (TSK_ENTRY_FUNC)TaskSampleEntry1;
|
|
||||||
stTask.uwStackSize = 0x1000;
|
|
||||||
stTask.pcName = "TaskSampleEntry1";
|
|
||||||
stTask.usTaskPrio = 6; /* Os task priority is 6 */
|
|
||||||
uwRet = LOS_TaskCreate(&taskID1, &stTask);
|
|
||||||
if (uwRet != LOS_OK) {
|
|
||||||
printf("Task1 create failed\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
stTask.pfnTaskEntry = (TSK_ENTRY_FUNC)TaskSampleEntry2;
|
|
||||||
stTask.uwStackSize = 0x1000;
|
|
||||||
stTask.pcName = "TaskSampleEntry2";
|
|
||||||
stTask.usTaskPrio = 7; /* Os task priority is 7 */
|
|
||||||
uwRet = LOS_TaskCreate(&taskID2, &stTask);
|
|
||||||
if (uwRet != LOS_OK) {
|
|
||||||
printf("Task2 create failed\n");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
VOID RunTaskSample(VOID)
|
|
||||||
{
|
|
||||||
UINT32 ret;
|
|
||||||
ret = LOS_KernelInit();
|
|
||||||
if (ret == LOS_OK) {
|
|
||||||
TaskSample();
|
|
||||||
LOS_Start();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
#if __cplusplus
|
|
||||||
}
|
|
||||||
#endif /* __cplusplus */
|
|
||||||
#endif /* __cplusplus */
|
|
||||||
|
|
@ -1,54 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
|
||||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
|
||||||
* Copyright (c) 2021 Nuclei Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
* are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
|
||||||
* conditions and the following disclaimer.
|
|
||||||
*
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
|
||||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
|
||||||
* provided with the distribution.
|
|
||||||
*
|
|
||||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
|
||||||
* to endorse or promote products derived from this software without specific prior written
|
|
||||||
* permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
||||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
|
||||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
|
||||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
|
||||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
|
||||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
|
||||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
|
||||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
|
||||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
|
||||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
|
|
||||||
*
|
|
||||||
* Description: Provide a task example.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _TASKSAMPLE_H
|
|
||||||
#define _TASKSAMPLE_H
|
|
||||||
|
|
||||||
#include "los_compiler.h"
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
#if __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif /* __cplusplus */
|
|
||||||
#endif /* __cplusplus */
|
|
||||||
|
|
||||||
VOID RunTaskSample(VOID);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
#if __cplusplus
|
|
||||||
}
|
|
||||||
#endif /* __cplusplus */
|
|
||||||
#endif /* __cplusplus */
|
|
||||||
|
|
||||||
#endif /* _TASKSAMPLE_H */
|
|
||||||
Binary file not shown.
|
Before Width: | Height: | Size: 41 KiB |
|
|
@ -1,9 +0,0 @@
|
||||||
# ignore openocd logfile and build folder
|
|
||||||
targets/*/GCC/build/
|
|
||||||
*.log
|
|
||||||
*.lst
|
|
||||||
*.bin
|
|
||||||
*.dasm
|
|
||||||
*.elf
|
|
||||||
*.hex
|
|
||||||
*.map
|
|
||||||
|
|
@ -1,224 +0,0 @@
|
||||||
# ------------------------------------------------
|
|
||||||
# Generic Makefile (based on gcc)
|
|
||||||
#
|
|
||||||
# ChangeLog :
|
|
||||||
# 2021-04-02 - first version
|
|
||||||
# ------------------------------------------------
|
|
||||||
|
|
||||||
######################################
|
|
||||||
# target
|
|
||||||
######################################
|
|
||||||
TARGET = Nuclei-rvstar-gd32vf103-soc
|
|
||||||
|
|
||||||
######################################
|
|
||||||
# building variables
|
|
||||||
######################################
|
|
||||||
# debug build?
|
|
||||||
DEBUG = 1
|
|
||||||
# optimization
|
|
||||||
OPT = -O2
|
|
||||||
|
|
||||||
|
|
||||||
#######################################
|
|
||||||
# paths
|
|
||||||
#######################################
|
|
||||||
# Build path
|
|
||||||
BUILD_DIR = build
|
|
||||||
|
|
||||||
#######################################
|
|
||||||
# Base directory
|
|
||||||
#######################################
|
|
||||||
# LiteOS top path
|
|
||||||
LITEOSTOPDIR := ../../../
|
|
||||||
|
|
||||||
######################################
|
|
||||||
# source
|
|
||||||
######################################
|
|
||||||
# C sources
|
|
||||||
C_SOURCES = \
|
|
||||||
$(wildcard ../Src/*.c) \
|
|
||||||
$(wildcard ../SoC/gd32vf103/Common/Source/*.c) \
|
|
||||||
$(wildcard ../SoC/gd32vf103/Board/gd32vf103v_rvstar/Source/*.c) \
|
|
||||||
$(wildcard ../SoC/gd32vf103/Common/Source/Drivers/*.c) \
|
|
||||||
$(wildcard ../SoC/gd32vf103/Common/Source/Drivers/Usb/*.c) \
|
|
||||||
$(wildcard ../SoC/gd32vf103/Common/Source/Stubs/*.c)
|
|
||||||
|
|
||||||
# ASM sources
|
|
||||||
ASMS_SOURCES = \
|
|
||||||
$(wildcard ../SoC/gd32vf103/Common/Source/GCC/*.S)
|
|
||||||
|
|
||||||
#######################################
|
|
||||||
# binaries
|
|
||||||
#######################################
|
|
||||||
PREFIX = riscv-nuclei-elf-
|
|
||||||
# The gcc compiler bin path can be either defined in make command via NUCLEI_TOOL_ROOT variable (> make NUCLEI_TOOL_ROOT=xxx)
|
|
||||||
# either it can be added to the PATH environment variable.
|
|
||||||
NUCLEI_RISCV_GCC_ROOT ?= $(NUCLEI_TOOL_ROOT)/gcc
|
|
||||||
NUCLEI_OPENOCD_ROOT ?= $(NUCLEI_TOOL_ROOT)/openocd
|
|
||||||
|
|
||||||
NUCLEI_TOOL_ROOT_EXIST = 0
|
|
||||||
ifneq ($(wildcard $(NUCLEI_RISCV_GCC_ROOT)),)
|
|
||||||
ifneq ($(wildcard $(NUCLEI_OPENOCD_ROOT)),)
|
|
||||||
NUCLEI_TOOL_ROOT_EXIST = 1
|
|
||||||
endif
|
|
||||||
endif
|
|
||||||
|
|
||||||
ifeq ($(NUCLEI_TOOL_ROOT_EXIST),1)
|
|
||||||
CC = $(NUCLEI_RISCV_GCC_ROOT)/bin/$(PREFIX)gcc
|
|
||||||
AS = $(NUCLEI_RISCV_GCC_ROOT)/bin/$(PREFIX)gcc -x assembler-with-cpp
|
|
||||||
CP = $(NUCLEI_RISCV_GCC_ROOT)/bin/$(PREFIX)objcopy
|
|
||||||
DP = $(NUCLEI_RISCV_GCC_ROOT)/bin/$(PREFIX)objdump
|
|
||||||
SZ = $(NUCLEI_RISCV_GCC_ROOT)/bin/$(PREFIX)size
|
|
||||||
GDB = $(NUCLEI_RISCV_GCC_ROOT)/bin/$(PREFIX)gdb
|
|
||||||
OPENOCD := $(NUCLEI_OPENOCD_ROOT)/bin/openocd
|
|
||||||
else
|
|
||||||
CC = $(PREFIX)gcc
|
|
||||||
AS = $(PREFIX)gcc -x assembler-with-cpp
|
|
||||||
CP = $(PREFIX)objcopy
|
|
||||||
DP = $(PREFIX)objdump
|
|
||||||
SZ = $(PREFIX)size
|
|
||||||
GDB = $(PREFIX)gdb
|
|
||||||
OPENOCD := openocd
|
|
||||||
endif
|
|
||||||
HEX = $(CP) -O ihex
|
|
||||||
BIN = $(CP) -O binary -S
|
|
||||||
|
|
||||||
ECHO := echo
|
|
||||||
|
|
||||||
OPENOCD_CFG := openocd_gd32vf103.cfg
|
|
||||||
|
|
||||||
#######################################
|
|
||||||
# CFLAGS
|
|
||||||
#######################################
|
|
||||||
#risc-v arch & abi
|
|
||||||
CORE_ARCH_ABI = -march=rv32imac -mabi=ilp32
|
|
||||||
|
|
||||||
#other flags
|
|
||||||
OTHER_FLAGS += -g -mcmodel=medany -fno-common
|
|
||||||
|
|
||||||
# macros for gcc
|
|
||||||
# AS defines
|
|
||||||
AS_DEFS = -DDOWNLOAD_MODE=DOWNLOAD_MODE_FLASHXIP
|
|
||||||
|
|
||||||
# C defines
|
|
||||||
C_DEFS = -DDOWNLOAD_MODE=DOWNLOAD_MODE_FLASHXIP
|
|
||||||
|
|
||||||
|
|
||||||
# AS includes
|
|
||||||
AS_INCLUDES =
|
|
||||||
|
|
||||||
# C includes
|
|
||||||
C_INCLUDES = \
|
|
||||||
-I../OS_CONFIG \
|
|
||||||
-I../Src \
|
|
||||||
-I../SoC/gd32vf103/Board/gd32vf103v_rvstar/Include \
|
|
||||||
-I../SoC/gd32vf103/Common/Include \
|
|
||||||
-I../SoC/gd32vf103/Common/Include/Usb \
|
|
||||||
-I../SoC/gd32vf103/Common/Source/Stubs
|
|
||||||
|
|
||||||
# compile gcc flags
|
|
||||||
ASFLAGS = $(AS_DEFS) $(OPT) $(CORE_ARCH_ABI) $(OTHER_FLAGS) $(AS_INCLUDES) -Wall -fdata-sections -ffunction-sections
|
|
||||||
|
|
||||||
CFLAGS = $(C_DEFS) $(C_INCLUDES) $(OPT) $(CORE_ARCH_ABI) $(OTHER_FLAGS) -Wall -fdata-sections -ffunction-sections
|
|
||||||
|
|
||||||
# Generate dependency information
|
|
||||||
CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)"
|
|
||||||
|
|
||||||
# Set your GDB port using variable GDB_PORT
|
|
||||||
GDB_PORT ?= 3333
|
|
||||||
## Makefile Variable GDBREMOTE
|
|
||||||
# You can change GDBREMOTE to other gdb remotes
|
|
||||||
## eg. if you have started openocd server with (bindto 0.0.0.0 defined in openocd.cfg)
|
|
||||||
## make sure your machine can connect to remote machine
|
|
||||||
## in remote machine(ipaddr 192.168.43.199, port 3333) which connect the hardware board,
|
|
||||||
## then you can change the GDBREMOTE to 192.168.43.199:3333
|
|
||||||
## GDBREMOTE ?= 192.168.43.199:3333
|
|
||||||
GDBREMOTE ?= | $(OPENOCD) --pipe -f $(OPENOCD_CFG)
|
|
||||||
|
|
||||||
GDB_UPLOAD_ARGS ?= --batch
|
|
||||||
GDB_UPLOAD_CMDS += -ex "monitor halt"
|
|
||||||
GDB_UPLOAD_CMDS += -ex "monitor flash protect 0 0 last off"
|
|
||||||
GDB_UPLOAD_CMDS += -ex "load"
|
|
||||||
GDB_UPLOAD_CMDS += -ex "monitor resume"
|
|
||||||
GDB_UPLOAD_CMDS += -ex "quit"
|
|
||||||
|
|
||||||
OPENOCD_PORT_ARGS = -c "gdb_port $(GDB_PORT)"
|
|
||||||
|
|
||||||
OPENOCD_ARGS += -f $(OPENOCD_CFG)
|
|
||||||
GDB_CMDS += -ex "set remotetimeout 240"
|
|
||||||
GDB_CMDS += -ex "target extended-remote localhost:$(GDB_PORT)"
|
|
||||||
|
|
||||||
#######################################
|
|
||||||
# LDFLAGS
|
|
||||||
#######################################
|
|
||||||
# link script
|
|
||||||
LDSCRIPT = gcc_gd32vf103_flashxip.ld
|
|
||||||
|
|
||||||
# libraries
|
|
||||||
LIBS = -lm
|
|
||||||
LIBDIR =
|
|
||||||
LDFLAGS = $(CORE_ARCH_ABI) $(OTHER_FLAGS) -specs=nano.specs -specs=nosys.specs -T $(LDSCRIPT) $(LIBDIR) $(LIBS) -nostartfiles -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections
|
|
||||||
|
|
||||||
# default action: build all
|
|
||||||
all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).dasm $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin
|
|
||||||
|
|
||||||
include liteos_m.mk
|
|
||||||
|
|
||||||
#######################################
|
|
||||||
# build the application
|
|
||||||
#######################################
|
|
||||||
# list of objects
|
|
||||||
OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o)))
|
|
||||||
vpath %.c $(sort $(dir $(C_SOURCES)))
|
|
||||||
# list of ASM program objects
|
|
||||||
OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.S=.o)))
|
|
||||||
vpath %.s $(sort $(dir $(ASM_SOURCES)))
|
|
||||||
|
|
||||||
$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR)
|
|
||||||
$(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@
|
|
||||||
|
|
||||||
$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR)
|
|
||||||
$(AS) -c $(CFLAGS) $(ASFLAGS) $< -o $@
|
|
||||||
|
|
||||||
$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile $(LDSCRIPT)
|
|
||||||
$(CC) $(OBJECTS) $(LDFLAGS) -o $@
|
|
||||||
$(SZ) $@
|
|
||||||
|
|
||||||
$(BUILD_DIR)/%.dasm: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
|
|
||||||
$(DP) -D -S $< > $@
|
|
||||||
|
|
||||||
$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
|
|
||||||
$(HEX) $< $@
|
|
||||||
|
|
||||||
$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
|
|
||||||
$(BIN) $< $@
|
|
||||||
|
|
||||||
$(BUILD_DIR):
|
|
||||||
mkdir $@
|
|
||||||
|
|
||||||
#######################################
|
|
||||||
# clean up
|
|
||||||
#######################################
|
|
||||||
clean:
|
|
||||||
-rm -fR $(BUILD_DIR)
|
|
||||||
|
|
||||||
#######################################
|
|
||||||
# upload & debug
|
|
||||||
#######################################
|
|
||||||
upload: $(BUILD_DIR)/$(TARGET).elf
|
|
||||||
@$(ECHO) "Download and run $<"
|
|
||||||
$(GDB) $< -ex "set remotetimeout 240" \
|
|
||||||
-ex "target remote $(GDBREMOTE)" \
|
|
||||||
$(GDB_UPLOAD_ARGS) $(GDB_UPLOAD_CMDS)
|
|
||||||
|
|
||||||
debug: $(BUILD_DIR)/$(TARGET).elf
|
|
||||||
@$(ECHO) "Download and debug $<"
|
|
||||||
$(GDB) $< -ex "set remotetimeout 240" \
|
|
||||||
-ex "target remote $(GDBREMOTE)"
|
|
||||||
|
|
||||||
#######################################
|
|
||||||
# dependencies
|
|
||||||
#######################################
|
|
||||||
-include $(wildcard $(BUILD_DIR)/*.d)
|
|
||||||
|
|
||||||
# *** EOF ***
|
|
||||||
|
|
@ -1,289 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2019 Nuclei Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
|
||||||
* not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
|
||||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*/
|
|
||||||
/******************************************************************************
|
|
||||||
* @file gcc_Device.ld
|
|
||||||
* @brief GNU Linker Script for gd32vf103 based device
|
|
||||||
* @version V1.0.0
|
|
||||||
* @date 17. Dec 2019
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*********** Use Configuration Wizard in Context Menu *************************/
|
|
||||||
|
|
||||||
OUTPUT_ARCH( "riscv" )
|
|
||||||
/********************* Flash Configuration ************************************
|
|
||||||
* <h> Flash Configuration
|
|
||||||
* <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
|
|
||||||
* <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
|
||||||
* </h>
|
|
||||||
*/
|
|
||||||
__ROM_BASE = 0x08000000;
|
|
||||||
__ROM_SIZE = 0x00020000;
|
|
||||||
|
|
||||||
/*--------------------- ILM RAM Configuration ---------------------------
|
|
||||||
* <h> ILM RAM Configuration
|
|
||||||
* <o0> ILM RAM Base Address <0x0-0xFFFFFFFF:8>
|
|
||||||
* <o1> ILM RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
|
||||||
* </h>
|
|
||||||
*/
|
|
||||||
__ILM_RAM_BASE = 0x80000000;
|
|
||||||
__ILM_RAM_SIZE = 0x00010000;
|
|
||||||
|
|
||||||
/*--------------------- Embedded RAM Configuration ---------------------------
|
|
||||||
* <h> RAM Configuration
|
|
||||||
* <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
|
|
||||||
* <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
|
||||||
* </h>
|
|
||||||
*/
|
|
||||||
__RAM_BASE = 0x20000000;
|
|
||||||
__RAM_SIZE = 0x00005000;
|
|
||||||
|
|
||||||
/********************* Stack / Heap Configuration ****************************
|
|
||||||
* <h> Stack / Heap Configuration
|
|
||||||
* <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
|
||||||
* <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
|
||||||
* </h>
|
|
||||||
*/
|
|
||||||
__STACK_SIZE = 0x00000800;
|
|
||||||
__HEAP_SIZE = 0x00000800;
|
|
||||||
|
|
||||||
/**************************** end of configuration section ********************/
|
|
||||||
|
|
||||||
/* Define base address and length of flash and ram */
|
|
||||||
MEMORY
|
|
||||||
{
|
|
||||||
flash (rxai!w) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
|
|
||||||
ram (wxa!ri) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
|
|
||||||
}
|
|
||||||
/* Linker script to place sections and symbol values. Should be used together
|
|
||||||
* with other linker script that defines memory regions FLASH,ILM and RAM.
|
|
||||||
* It references following symbols, which must be defined in code:
|
|
||||||
* _Start : Entry of reset handler
|
|
||||||
*
|
|
||||||
* It defines following symbols, which code can use without definition:
|
|
||||||
* _ilm_lma
|
|
||||||
* _ilm
|
|
||||||
* __etext
|
|
||||||
* _etext
|
|
||||||
* etext
|
|
||||||
* _eilm
|
|
||||||
* __preinit_array_start
|
|
||||||
* __preinit_array_end
|
|
||||||
* __init_array_start
|
|
||||||
* __init_array_end
|
|
||||||
* __fini_array_start
|
|
||||||
* __fini_array_end
|
|
||||||
* _data_lma
|
|
||||||
* _edata
|
|
||||||
* edata
|
|
||||||
* __data_end__
|
|
||||||
* __bss_start
|
|
||||||
* __fbss
|
|
||||||
* _end
|
|
||||||
* end
|
|
||||||
* __heap_end
|
|
||||||
* __StackLimit
|
|
||||||
* __StackTop
|
|
||||||
* __STACK_SIZE
|
|
||||||
*/
|
|
||||||
/* Define entry label of program */
|
|
||||||
ENTRY(_start)
|
|
||||||
SECTIONS
|
|
||||||
{
|
|
||||||
__STACK_SIZE = DEFINED(__STACK_SIZE) ? __STACK_SIZE : 2K;
|
|
||||||
|
|
||||||
.init :
|
|
||||||
{
|
|
||||||
/* vector table locate at flash */
|
|
||||||
*(.vtable)
|
|
||||||
KEEP (*(SORT_NONE(.init)))
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
.ilalign :
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
/* Create a section label as _ilm_lma which located at flash */
|
|
||||||
PROVIDE( _ilm_lma = . );
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
.ialign :
|
|
||||||
{
|
|
||||||
/* Create a section label as _ilm which located at flash */
|
|
||||||
PROVIDE( _ilm = . );
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
/* Code section located at flash */
|
|
||||||
.text :
|
|
||||||
{
|
|
||||||
*(.text.unlikely .text.unlikely.*)
|
|
||||||
*(.text.startup .text.startup.*)
|
|
||||||
*(.text .text.*)
|
|
||||||
*(.gnu.linkonce.t.*)
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
.rodata : ALIGN(4)
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
*(.rdata)
|
|
||||||
*(.rodata .rodata.*)
|
|
||||||
/* section information for initial. */
|
|
||||||
. = ALIGN(4);
|
|
||||||
__rt_init_start = .;
|
|
||||||
KEEP(*(SORT(.rti_fn*)))
|
|
||||||
__rt_init_end = .;
|
|
||||||
/* section information for finsh shell */
|
|
||||||
. = ALIGN(4);
|
|
||||||
__fsymtab_start = .;
|
|
||||||
KEEP(*(FSymTab))
|
|
||||||
__fsymtab_end = .;
|
|
||||||
. = ALIGN(4);
|
|
||||||
__vsymtab_start = .;
|
|
||||||
KEEP(*(VSymTab))
|
|
||||||
__vsymtab_end = .;
|
|
||||||
*(.gnu.linkonce.r.*)
|
|
||||||
. = ALIGN(8);
|
|
||||||
*(.srodata.cst16)
|
|
||||||
*(.srodata.cst8)
|
|
||||||
*(.srodata.cst4)
|
|
||||||
*(.srodata.cst2)
|
|
||||||
*(.srodata .srodata.*)
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
.fini :
|
|
||||||
{
|
|
||||||
KEEP (*(SORT_NONE(.fini)))
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
. = ALIGN(4);
|
|
||||||
|
|
||||||
PROVIDE (__etext = .);
|
|
||||||
PROVIDE (_etext = .);
|
|
||||||
PROVIDE (etext = .);
|
|
||||||
PROVIDE( _eilm = . );
|
|
||||||
|
|
||||||
|
|
||||||
.preinit_array :
|
|
||||||
{
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
|
||||||
KEEP (*(.preinit_array))
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
.init_array :
|
|
||||||
{
|
|
||||||
PROVIDE_HIDDEN (__init_array_start = .);
|
|
||||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
|
||||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
|
||||||
PROVIDE_HIDDEN (__init_array_end = .);
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
.fini_array :
|
|
||||||
{
|
|
||||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
|
||||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
|
||||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
|
||||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
.ctors :
|
|
||||||
{
|
|
||||||
/* gcc uses crtbegin.o to find the start of
|
|
||||||
* the constructors, so we make sure it is
|
|
||||||
* first. Because this is a wildcard, it
|
|
||||||
* doesn't matter if the user does not
|
|
||||||
* actually link against crtbegin.o; the
|
|
||||||
* linker won't look for a file to match a
|
|
||||||
* wildcard. The wildcard also means that it
|
|
||||||
* doesn't matter which directory crtbegin.o
|
|
||||||
* is in.
|
|
||||||
*/
|
|
||||||
KEEP (*crtbegin.o(.ctors))
|
|
||||||
KEEP (*crtbegin?.o(.ctors))
|
|
||||||
/* We don't want to include the .ctor section from
|
|
||||||
* the crtend.o file until after the sorted ctors.
|
|
||||||
* The .ctor section from the crtend file contains the
|
|
||||||
* end of ctors marker and it must be last
|
|
||||||
*/
|
|
||||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
|
||||||
KEEP (*(SORT(.ctors.*)))
|
|
||||||
KEEP (*(.ctors))
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
.dtors :
|
|
||||||
{
|
|
||||||
KEEP (*crtbegin.o(.dtors))
|
|
||||||
KEEP (*crtbegin?.o(.dtors))
|
|
||||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
|
||||||
KEEP (*(SORT(.dtors.*)))
|
|
||||||
KEEP (*(.dtors))
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
.lalign :
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
PROVIDE( _data_lma = . );
|
|
||||||
} >flash AT>flash
|
|
||||||
|
|
||||||
.dalign :
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
PROVIDE( _data = . );
|
|
||||||
} >ram AT>flash
|
|
||||||
|
|
||||||
/* Define data section virtual address is ram and physical address is flash */
|
|
||||||
.data :
|
|
||||||
{
|
|
||||||
*(.data .data.*)
|
|
||||||
*(.gnu.linkonce.d.*)
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
|
||||||
*(.sdata .sdata.* .sdata*)
|
|
||||||
*(.gnu.linkonce.s.*)
|
|
||||||
} >ram AT>flash
|
|
||||||
|
|
||||||
. = ALIGN(4);
|
|
||||||
PROVIDE( _edata = . );
|
|
||||||
PROVIDE( edata = . );
|
|
||||||
|
|
||||||
PROVIDE( _fbss = . );
|
|
||||||
PROVIDE( __bss_start = . );
|
|
||||||
.bss :
|
|
||||||
{
|
|
||||||
*(.sbss*)
|
|
||||||
*(.gnu.linkonce.sb.*)
|
|
||||||
*(.bss .bss.*)
|
|
||||||
*(.gnu.linkonce.b.*)
|
|
||||||
*(COMMON)
|
|
||||||
. = ALIGN(4);
|
|
||||||
} >ram AT>ram
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE( _end = . );
|
|
||||||
PROVIDE( end = . );
|
|
||||||
/* Define stack and head location at ram */
|
|
||||||
.stack ORIGIN(ram) + LENGTH(ram) - __STACK_SIZE - __HEAP_SIZE :
|
|
||||||
{
|
|
||||||
PROVIDE( _heap_end = . );
|
|
||||||
/*
|
|
||||||
PROVIDE( __los_heap_addr_start__ = . );
|
|
||||||
. = __HEAP_SIZE;
|
|
||||||
PROVIDE( __los_heap_addr_end__ = . );
|
|
||||||
*/
|
|
||||||
. = __STACK_SIZE;
|
|
||||||
PROVIDE( _sp = . );
|
|
||||||
} >ram AT>ram
|
|
||||||
}
|
|
||||||
|
|
@ -1,46 +0,0 @@
|
||||||
LITEOSTOPDIR := ../../../
|
|
||||||
LITEOSTOPDIR := $(realpath $(LITEOSTOPDIR))
|
|
||||||
|
|
||||||
# Common
|
|
||||||
C_SOURCES += $(wildcard $(LITEOSTOPDIR)/kernel/src/*.c) \
|
|
||||||
$(wildcard $(LITEOSTOPDIR)/kernel/src/mm/*.c) \
|
|
||||||
$(wildcard $(LITEOSTOPDIR)/components/cpup/*.c) \
|
|
||||||
$(wildcard $(LITEOSTOPDIR)/components/backtrace/*.c) \
|
|
||||||
$(wildcard $(LITEOSTOPDIR)/components/power/*.c) \
|
|
||||||
$(wildcard $(LITEOSTOPDIR)/utils/*.c)
|
|
||||||
|
|
||||||
C_INCLUDES += -I$(LITEOSTOPDIR)/utils \
|
|
||||||
-I$(LITEOSTOPDIR)/kernel/include \
|
|
||||||
-I$(LITEOSTOPDIR)/components/cpup \
|
|
||||||
-I$(LITEOSTOPDIR)/components/backtrace \
|
|
||||||
-I$(LITEOSTOPDIR)/components/power
|
|
||||||
|
|
||||||
#third party related
|
|
||||||
C_INCLUDES += -I$(LITEOSTOPDIR)/../../third_party/bounds_checking_function/include \
|
|
||||||
-I$(LITEOSTOPDIR)/../../third_party/bounds_checking_function/src
|
|
||||||
|
|
||||||
C_SOURCES += $(wildcard $(LITEOSTOPDIR)/../../third_party/bounds_checking_function/src/*.c)
|
|
||||||
|
|
||||||
# NMSIS related
|
|
||||||
C_INCLUDES += -I$(LITEOSTOPDIR)/arch/risc-v/nuclei/gcc/nmsis/Core/Include \
|
|
||||||
-I$(LITEOSTOPDIR)/arch/risc-v/nuclei/gcc/nmsis/DSP/Include \
|
|
||||||
-I$(LITEOSTOPDIR)/arch/risc-v/nuclei/gcc/nmsis/NN/Include
|
|
||||||
|
|
||||||
ASM_SOURCES += $(wildcard $(LITEOSTOPDIR)/arch/risc-v/nuclei/gcc/*.s)
|
|
||||||
|
|
||||||
ASMS_SOURCES += $(wildcard $(LITEOSTOPDIR)/arch/risc-v/nuclei/gcc/*.S)
|
|
||||||
|
|
||||||
C_SOURCES += $(wildcard $(LITEOSTOPDIR)/arch/risc-v/nuclei/gcc/*.c)
|
|
||||||
|
|
||||||
C_INCLUDES += -I. \
|
|
||||||
-I$(LITEOSTOPDIR)/arch/include \
|
|
||||||
-I$(LITEOSTOPDIR)/arch/risc-v/nuclei/gcc
|
|
||||||
|
|
||||||
ASFLAGS += -imacros $(LITEOSTOPDIR)/kernel/include/los_config.h -DCLZ=CLZ
|
|
||||||
|
|
||||||
# list of ASM .S program objects
|
|
||||||
OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASMS_SOURCES:.S=.o)))
|
|
||||||
vpath %.S $(sort $(dir $(ASMS_SOURCES)))
|
|
||||||
|
|
||||||
$(BUILD_DIR)/%.o: %.S Makefile | $(BUILD_DIR)
|
|
||||||
$(CC) -c $(CFLAGS) $(ASFLAGS) $< -o $@
|
|
||||||
|
|
@ -1,53 +0,0 @@
|
||||||
adapter_khz 10000
|
|
||||||
reset_config srst_only
|
|
||||||
adapter_nsrst_assert_width 100
|
|
||||||
|
|
||||||
interface ftdi
|
|
||||||
ftdi_vid_pid 0x0403 0x6010
|
|
||||||
|
|
||||||
## If ftdi_device_desc not specified, the device description is ignored during device selection.
|
|
||||||
## So if you want to specify a dedicated FTDI device, you can select following device description:
|
|
||||||
## "Dual RS232-HS" is for RVSTAR V1 on-board debugger
|
|
||||||
## "USB <-> JTAG-DEBUGGER" is for RVSTAR V2 on-board debugger
|
|
||||||
## Uncomment one which match your device description
|
|
||||||
# ftdi_device_desc "Dual RS232-HS"
|
|
||||||
# ftdi_device_desc "USB <-> JTAG-DEBUGGER"
|
|
||||||
|
|
||||||
ftdi_layout_init 0x0008 0x001b
|
|
||||||
ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
|
|
||||||
# These signals are used for cJTAG escape sequence on initialization only
|
|
||||||
ftdi_layout_signal TCK -data 0x0001
|
|
||||||
ftdi_layout_signal TDI -data 0x0002
|
|
||||||
ftdi_layout_signal TDO -input 0x0004
|
|
||||||
ftdi_layout_signal TMS -data 0x0008
|
|
||||||
ftdi_layout_signal JTAG_SEL -data 0x0100 -oe 0x0100
|
|
||||||
transport select jtag
|
|
||||||
|
|
||||||
set _CHIPNAME riscv
|
|
||||||
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1e200a6d
|
|
||||||
|
|
||||||
# Work-area is a space in RAM used for flash programming
|
|
||||||
if { [info exists WORKAREASIZE] } {
|
|
||||||
set _WORKAREASIZE $WORKAREASIZE
|
|
||||||
} else {
|
|
||||||
set _WORKAREASIZE 0x5000
|
|
||||||
}
|
|
||||||
|
|
||||||
set _TARGETNAME $_CHIPNAME.cpu
|
|
||||||
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
|
|
||||||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
|
||||||
|
|
||||||
set _FLASHNAME $_CHIPNAME.flash
|
|
||||||
|
|
||||||
flash bank $_FLASHNAME gd32vf103 0x08000000 0 0 0 $_TARGETNAME
|
|
||||||
|
|
||||||
# Expose Nuclei self-defined CSRS range
|
|
||||||
# See https://github.com/riscv/riscv-gnu-toolchain/issues/319#issuecomment-358397306
|
|
||||||
# Then user can view the csr register value in gdb using: info reg csr775 for CSR MTVT(0x307)
|
|
||||||
riscv expose_csrs 770-800,835-850,1984-2032,2064-2070
|
|
||||||
|
|
||||||
riscv set_reset_timeout_sec 1
|
|
||||||
|
|
||||||
init
|
|
||||||
|
|
||||||
halt
|
|
||||||
|
|
@ -1,122 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
|
||||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
|
||||||
* Copyright (c) 2021 Nuclei Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
* are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
|
||||||
* conditions and the following disclaimer.
|
|
||||||
*
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
|
||||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
|
||||||
* provided with the distribution.
|
|
||||||
*
|
|
||||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
|
||||||
* to endorse or promote products derived from this software without specific prior written
|
|
||||||
* permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
||||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
|
||||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
|
||||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
|
||||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
|
||||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
|
||||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
|
||||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
|
||||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
|
||||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**@defgroup los_config System configuration items
|
|
||||||
* @ingroup kernel
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _TARGET_CONFIG_H
|
|
||||||
#define _TARGET_CONFIG_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
#if __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif /* __cplusplus */
|
|
||||||
#endif /* __cplusplus */
|
|
||||||
|
|
||||||
#include "nuclei_sdk_soc.h"
|
|
||||||
|
|
||||||
/*=============================================================================
|
|
||||||
System clock module configuration
|
|
||||||
=============================================================================*/
|
|
||||||
#define OS_SYS_CLOCK (SOC_TIMER_FREQ)
|
|
||||||
#define LOSCFG_BASE_CORE_TICK_PER_SECOND (1000UL)
|
|
||||||
#define LOSCFG_BASE_CORE_TICK_HW_TIME 0
|
|
||||||
#define LOSCFG_BASE_CORE_TICK_WTIMER 1
|
|
||||||
/*=============================================================================
|
|
||||||
Hardware interrupt module configuration
|
|
||||||
=============================================================================*/
|
|
||||||
#define LOSCFG_PLATFORM_HWI 1
|
|
||||||
#define LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT 0
|
|
||||||
#define LOSCFG_PLATFORM_HWI_LIMIT 32
|
|
||||||
/*=============================================================================
|
|
||||||
Task module configuration
|
|
||||||
=============================================================================*/
|
|
||||||
#define LOSCFG_BASE_CORE_TSK_LIMIT 12
|
|
||||||
#define LOSCFG_BASE_CORE_TSK_IDLE_STACK_SIZE (0x280U)
|
|
||||||
#define LOSCFG_BASE_CORE_TSK_DEFAULT_STACK_SIZE (0x200U)
|
|
||||||
#define LOSCFG_BASE_CORE_TSK_MIN_STACK_SIZE (0x130U)
|
|
||||||
#define LOSCFG_BASE_CORE_TIMESLICE 1
|
|
||||||
#define LOSCFG_BASE_CORE_TIMESLICE_TIMEOUT 20000
|
|
||||||
#define LOSCFG_BASE_CORE_TICK_RESPONSE_MAX 0xFFFFFF
|
|
||||||
/*=============================================================================
|
|
||||||
Semaphore module configuration
|
|
||||||
=============================================================================*/
|
|
||||||
#define LOSCFG_BASE_IPC_SEM 1
|
|
||||||
#define LOSCFG_BASE_IPC_SEM_LIMIT 48
|
|
||||||
/*=============================================================================
|
|
||||||
Mutex module configuration
|
|
||||||
=============================================================================*/
|
|
||||||
#define LOSCFG_BASE_IPC_MUX 1
|
|
||||||
#define LOSCFG_BASE_IPC_MUX_LIMIT 10
|
|
||||||
/*=============================================================================
|
|
||||||
Queue module configuration
|
|
||||||
=============================================================================*/
|
|
||||||
#define LOSCFG_BASE_IPC_QUEUE 1
|
|
||||||
#define LOSCFG_BASE_IPC_QUEUE_LIMIT 6
|
|
||||||
/*=============================================================================
|
|
||||||
Software timer module configuration
|
|
||||||
=============================================================================*/
|
|
||||||
#define LOSCFG_BASE_CORE_SWTMR 1
|
|
||||||
#define LOSCFG_BASE_CORE_SWTMR_ALIGN 1
|
|
||||||
#define LOSCFG_BASE_CORE_SWTMR_LIMIT 6
|
|
||||||
/*=============================================================================
|
|
||||||
Memory module configuration
|
|
||||||
=============================================================================*/
|
|
||||||
#define LOSCFG_SYS_HEAP_SIZE 0x03800UL
|
|
||||||
#define OS_SYS_MEM_SIZE 0x00000800
|
|
||||||
#define LOSCFG_BASE_MEM_NODE_INTEGRITY_CHECK 0
|
|
||||||
#define LOSCFG_BASE_MEM_NODE_SIZE_CHECK 1
|
|
||||||
#define LOSCFG_MEM_MUL_POOL 0
|
|
||||||
#define OS_SYS_MEM_NUM 20
|
|
||||||
#define LOSCFG_KERNEL_MEM_SLAB 0
|
|
||||||
/*=============================================================================
|
|
||||||
Exception module configuration
|
|
||||||
=============================================================================*/
|
|
||||||
#define LOSCFG_PLATFORM_EXC 0
|
|
||||||
/* =============================================================================
|
|
||||||
printf module configuration
|
|
||||||
============================================================================= */
|
|
||||||
#define LOSCFG_KERNEL_PRINTF 1
|
|
||||||
/* =============================================================================
|
|
||||||
enable backtrace
|
|
||||||
============================================================================= */
|
|
||||||
#define LOSCFG_BACKTRACE_TYPE 0
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
#if __cplusplus
|
|
||||||
}
|
|
||||||
#endif /* __cplusplus */
|
|
||||||
#endif /* __cplusplus */
|
|
||||||
|
|
||||||
|
|
||||||
#endif /* _TARGET_CONFIG_H */
|
|
||||||
|
|
@ -1,205 +0,0 @@
|
||||||
# RV-STAR开发板LiteOS使用说明
|
|
||||||
|
|
||||||
## RV-STAR开发板简介
|
|
||||||
|
|
||||||
RV-STAR是一款基于GD32VF103 MCU的RISC-V评估开发板，提供了板载调试器、Reset和Wakeup用户按键、RGB LED、USB OTG，以及EXMC、Arduino和PMOD扩展接口等资源。
|
|
||||||
|
|
||||||
开发板资料链接：
|
|
||||||
|
|
||||||
- [RV-STAR开发板电路原理图](https://www.rvmcu.com/quickstart-doc-u-pdf-id-235.html)
|
|
||||||
- [RV-STAR开发板用户手册（Segger Embedded Studio IDE版）](https://www.rvmcu.com/quickstart-doc-u-pdf-id-236.html)
|
|
||||||
- [RV-STAR开发板用户手册（Nuclei Studio IDE版）](https://www.rvmcu.com/quickstart-doc-u-pdf-id-531.html)
|
|
||||||
- [RV-STAR板载GD32VF103芯片资料](https://www.rvmcu.com/quickstart-doc-u-gd32vf103.html)
|
|
||||||
- [芯来RISC-V Bumblebee内核指令集手册](https://www.rvmcu.com/quickstart-doc-u-pdf-id-8.html)
|
|
||||||
|
|
||||||
## 文件结构
|
|
||||||
|
|
||||||
```
|
|
||||||
├── components # 可选组件
|
|
||||||
│ ├── cppsupport # C++支持
|
|
||||||
│ └── cpup # CPUP功能
|
|
||||||
├── kal # 内核抽象层
|
|
||||||
│ └── posix # posix标准接口支持
|
|
||||||
├── arch # 内核指令架构层代码
|
|
||||||
│ ├── risc-v # risc-v架构的代码
|
|
||||||
│ │ └── nuclei # nuclei内核相关代码
|
|
||||||
│ │ └── gcc # gcc编译器相关代码
|
|
||||||
│ │ └── nmsis # nmsis内核标准
|
|
||||||
│ └── include # 对外接口存放目录
|
|
||||||
│ ├── los_atomic.h # 定义通用arch的原子操作
|
|
||||||
│ ├── los_context.h # 定义通用arch的上下文切换
|
|
||||||
│ ├── los_arch.h # 定义通用arch初始化
|
|
||||||
│ └── los_interrupt.h # 定义通用arch中断
|
|
||||||
├── kernel # 内核最小功能集支持
|
|
||||||
│ ├── include # 对外接口存放目录
|
|
||||||
│ │ ├── los_config.h # 功能开关和配置参数
|
|
||||||
│ │ ├── los_event.h # 事件
|
|
||||||
│ │ ├── los_liteos.h # liteos最小功能集对外提供的头文件
|
|
||||||
│ │ ├── los_memory.h # 堆内存管理
|
|
||||||
│ │ ├── los_mutex.h # 互斥锁
|
|
||||||
│ │ ├── los_queue.h # 队列
|
|
||||||
│ │ ├── los_scheduler.h # 调度算法
|
|
||||||
│ │ ├── los_sem.h # 信号量
|
|
||||||
│ │ ├── los_task.h # 任务
|
|
||||||
│ │ └── los_timer.h # 定时器
|
|
||||||
│ └── src # 内核最小功能集源码
|
|
||||||
├── targets # 板级工程目录
|
|
||||||
│ └── riscv_nuclei_gd32vf103_soc_gcc # RV-STAR开发板相关代码
|
|
||||||
│ ├── GCC # 编译相关
|
|
||||||
│ ├── OS_CONFIG # 开发板配置功能开关和配置参数
|
|
||||||
│ ├── SoC # gd32vf103 SOC相关代码
|
|
||||||
│ └── Src # application相关代码
|
|
||||||
└── utils # 通用公共目录
|
|
||||||
├── include
|
|
||||||
│ ├── los_compiler.h # 编译工具配置，类型定义
|
|
||||||
│ ├── los_debug.h # debug，printf相关
|
|
||||||
│ ├── los_error.h # 错误定义
|
|
||||||
│ └── los_list.h
|
|
||||||
└── src
|
|
||||||
```
|
|
||||||
|
|
||||||
## 使用说明
|
|
||||||
|
|
||||||
软件需求：linux环境
|
|
||||||
|
|
||||||
硬件需求：RV-STAR开发板
|
|
||||||
|
|
||||||
[环境配置](#sectionb1)
|
|
||||||
|
|
||||||
[编译源码](#sectionb2)
|
|
||||||
|
|
||||||
[下载调试、运行](#sectionb3)
|
|
||||||
|
|
||||||
本示例将新建并运行两个任务，PA0按键为外部中断，按下后可以查看任务列表信息。
|
|
||||||
|
|
||||||
### 环境配置<a name="sectionb1"></a>
|
|
||||||
|
|
||||||
- **工具链配置**
|
|
||||||
|
|
||||||
请先确认您使用的是centos系统或Ubuntu 64bit。
|
|
||||||
|
|
||||||
1. 新建一个`Nuclei` 文件夹，比如`~/Software/Nuclei`
|
|
||||||
2. 参考下图，从[Nuclei Download Center](https://nucleisys.com/download.php)下载工具链和OpenOCD。
|
|
||||||
- CentOS或Ubuntu系统请点击图中红框1下载RISC-V GNU工具链
|
|
||||||
- 点击图中蓝框2-1下载64bit的OpenOCD
|
|
||||||
- **确保Make工具版本不低于3.82**: ubuntu系统使用`sudo apt-get install make`指令安装`make`工具, CentOS系统使用`sudo yum install make`指令安装。
|
|
||||||
|
|
||||||
图1 Linux环境要下载的Nuclei Tools
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
3. 在之前新建的`Nuclei`文件夹中新建`gcc`文件夹和`openocd`文件夹。
|
|
||||||
- 解压缩之前下载的**gnu工具链**到任意文件夹中，复制其中`bin`文件件所在层级的所有内容到`gcc`文件夹中。
|
|
||||||
- 同样解压缩之前下载的**OpenOCD**到任意文件夹中，复制其中`bin`文件件所在层级的所有内容到`openocd`文件夹中。
|
|
||||||
|
|
||||||
> 注意：
|
|
||||||
>
|
|
||||||
> 请务必下载并解压缩Linux版本的工具，不要下载windows版本工具。
|
|
||||||
|
|
||||||
- **驱动配置**
|
|
||||||
|
|
||||||
驱动配置步骤如下：
|
|
||||||
|
|
||||||
1. 连接开发板到Linux中，确保USB被Linux识别出来。
|
|
||||||
|
|
||||||
2. 在控制台中使用lsusb指令查看信息，参考的打印信息如下：
|
|
||||||
|
|
||||||
```
|
|
||||||
Bus 001 Device 010: ID 0403:6010 Future Technology Devices International, Ltd FT2232xxxx
|
|
||||||
```
|
|
||||||
|
|
||||||
3. 将github（https://github.com/riscv-mcu/ses_nuclei_sdk_projects/blob/master/misc/99-openocd.rules）上misc文件夹内99-openocd.rules文件复制到当前路径下，控制台中输入sudo cp 99-openocd.rules /etc/udev/rules.d/99-openocd.rules指令复制文件到指定路径下。
|
|
||||||
|
|
||||||
4. 断开调试器再重新连接到Linux系统中。
|
|
||||||
|
|
||||||
5. 使用ls /dev/ttyUSB*命令查看ttyUSB信息，参考输出如下：
|
|
||||||
|
|
||||||
```
|
|
||||||
/dev/ttyUSB0 /dev/ttyUSB1
|
|
||||||
```
|
|
||||||
|
|
||||||
6. 使用ls -l /dev/ttyUSB1命令查看分组信息，参考输出如下:
|
|
||||||
|
|
||||||
```
|
|
||||||
crw-rw-r-- 1 root plugdev 188, 1 Nov 28 12:53 /dev/ttyUSB1
|
|
||||||
```
|
|
||||||
|
|
||||||
可以看到ttyUSB1已经加入plugdev组，接下来我们要将自己添加到plugdev组。使用whoami命令查看当前用户名，我们将其记录为\< your_user_name >。
|
|
||||||
|
|
||||||
7. 使用sudo usermod -a -G plugdev \<your_user_name>命令将自己添加进plugdev组。
|
|
||||||
|
|
||||||
8. 再次确认当前用户名已属于plugdev组，使用groups命令，可以看到打印信息中有plugdev即成功将当前用户添加至plugdev组。
|
|
||||||
|
|
||||||
### 编译源码<a name="sectionb2"></a>
|
|
||||||
|
|
||||||
使用`git clone`复制代码到任意目录下，打开进入到工程根目录下，输入`git submodule update --init --recursive`下载更新子模块。
|
|
||||||
|
|
||||||
编译前请在当前控制台中配置`NUCLEI_TOOL_ROOT`路径，假设`Nuclei`文件夹所在路径为`/home/Nuclei`，输入`export NUCLEI_TOOL_ROOT=/home/Nuclei` 。或者使用时make选项增加`NUCLEI_TOOL_ROOT=/home/Nuclei`。
|
|
||||||
|
|
||||||
配置路径后打开至代码根目录下的/target/riscv_nuclei_gd32vf103_soc_gcc/GCC位置，输入如下指令开始编译：
|
|
||||||
|
|
||||||
```
|
|
||||||
make all
|
|
||||||
```
|
|
||||||
|
|
||||||
编译结束后部分参考输出如下：
|
|
||||||
|
|
||||||
```
|
|
||||||
text data bss dec hex filename
|
|
||||||
24330 112 16768 41210 a0fa build/Nuclei-rvstar-gd32vf103-soc.elf
|
|
||||||
```
|
|
||||||
|
|
||||||
若编译前想清理工程，请使用如下指令：
|
|
||||||
|
|
||||||
```
|
|
||||||
make clean
|
|
||||||
```
|
|
||||||
|
|
||||||
### 下载调试、运行<a name="sectionb3"></a>
|
|
||||||
|
|
||||||
调试或运行前请先连接RV-STAR开发板，确保已按照[环境配置](#sectionb1)中驱动配置部分配置完成。
|
|
||||||
|
|
||||||
同样配置好`NUCLEI_TOOL_ROOT`路径并打开至代码根目录下的/target/riscv_nuclei_gd32vf103_soc_gcc/GCC位置，输入如下指令进入GDB调试：
|
|
||||||
|
|
||||||
```
|
|
||||||
make debug
|
|
||||||
```
|
|
||||||
|
|
||||||
等待到进入GDB调试界面时，输入`load`指令下载编译好的elf文件，就可以开始调试。
|
|
||||||
|
|
||||||
若想直接运行，请在调试时所在位置输入如下指令：
|
|
||||||
|
|
||||||
```
|
|
||||||
make upload
|
|
||||||
```
|
|
||||||
|
|
||||||
运行时可以查看串口打印内容，使用串口查看工具，这里以`minicom`为例，若未安装此工具可自行安装或使用其他串口查看工具。打开控制台，输入`minicom -D /dev/ttyUSB1 -b 115200`指令打开串口查看工具。
|
|
||||||
|
|
||||||
运行时参考输出如下：
|
|
||||||
|
|
||||||
```
|
|
||||||
Nuclei SDK Build Time: Mar 30 2021, 18:26:53
|
|
||||||
Download Mode: FLASHXIP
|
|
||||||
CPU Frequency 108540000 Hz
|
|
||||||
entering kernel init...
|
|
||||||
TaskSampleEntry1 running...
|
|
||||||
TaskSampleEntry1 running...
|
|
||||||
TaskSampleEntry1 running...
|
|
||||||
TaskSampleEntry1 running...
|
|
||||||
TaskSampleEntry2 running...
|
|
||||||
TaskSampleEntry1 running...
|
|
||||||
TaskSampleEntry1 running...
|
|
||||||
EXTI0_IRQHandler running...
|
|
||||||
ID Pri Status name
|
|
||||||
-- --- --------- ----
|
|
||||||
0 0 QueuePend Swt_Task
|
|
||||||
1 31 Running IdleCore000
|
|
||||||
2 6 Delay TaskSampleEntry1
|
|
||||||
3 7 Delay TaskSampleEntry2
|
|
||||||
TaskSampleEntry1 running...
|
|
||||||
TaskSampleEntry1 running...
|
|
||||||
TaskSampleEntry1 running...
|
|
||||||
TaskSampleEntry2 running...
|
|
||||||
```
|
|
||||||
|
|
@ -1,134 +0,0 @@
|
||||||
/*!
|
|
||||||
\file gd32vf103c_start.h
|
|
||||||
\brief definitions for GD32VF103C_START's leds, keys and COM ports hardware resources
|
|
||||||
|
|
||||||
\version 2019-06-05, V1.0.0, demo for GD32VF103
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef GD32VF103C_RVSTART_H
|
|
||||||
#define GD32VF103C_RVSTART_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#include "nuclei_sdk_soc.h"
|
|
||||||
|
|
||||||
/* exported types */
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
LED1 = 0,
|
|
||||||
LED2 = 1,
|
|
||||||
LED3 = 2,
|
|
||||||
LED_1 = 0,
|
|
||||||
LED_2 = 1,
|
|
||||||
LED_3 = 2
|
|
||||||
}led_typedef_enum;
|
|
||||||
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
KEY_WAKEUP = 0,
|
|
||||||
}key_typedef_enum;
|
|
||||||
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
KEY_MODE_GPIO = 0,
|
|
||||||
KEY_MODE_EXTI = 1
|
|
||||||
}keymode_typedef_enum;
|
|
||||||
|
|
||||||
|
|
||||||
/* rvstar board low layer led */
|
|
||||||
#define LEDn 3U
|
|
||||||
|
|
||||||
#define LEDG_PIN GPIO_PIN_1
|
|
||||||
#define LEDG_GPIO_PORT GPIOA
|
|
||||||
#define LEDG_GPIO_CLK RCU_GPIOA
|
|
||||||
|
|
||||||
#define LEDB_PIN GPIO_PIN_3
|
|
||||||
#define LEDB_GPIO_PORT GPIOA
|
|
||||||
#define LEDB_GPIO_CLK RCU_GPIOA
|
|
||||||
|
|
||||||
#define LEDR_PIN GPIO_PIN_2
|
|
||||||
#define LEDR_GPIO_PORT GPIOA
|
|
||||||
#define LEDR_GPIO_CLK RCU_GPIOA
|
|
||||||
|
|
||||||
/* rvstar board UART com port */
|
|
||||||
#define GD32_COM0 UART4
|
|
||||||
#define GD32_COM_CLK RCU_UART4
|
|
||||||
#define GD32_COM_TX_PIN GPIO_PIN_12
|
|
||||||
#define GD32_COM_RX_PIN GPIO_PIN_2
|
|
||||||
#define GD32_COM_TX_GPIO_PORT GPIOC
|
|
||||||
#define GD32_COM_RX_GPIO_PORT GPIOD
|
|
||||||
#define GD32_COM_TX_GPIO_CLK RCU_GPIOC
|
|
||||||
#define GD32_COM_RX_GPIO_CLK RCU_GPIOD
|
|
||||||
|
|
||||||
/* rvstar board low layer button */
|
|
||||||
#define KEYn (1U)
|
|
||||||
|
|
||||||
/* wakeup push-button */
|
|
||||||
#define WAKEUP_KEY_PIN GPIO_PIN_0
|
|
||||||
#define WAKEUP_KEY_GPIO_PORT GPIOA
|
|
||||||
#define WAKEUP_KEY_GPIO_CLK RCU_GPIOA
|
|
||||||
#define WAKEUP_KEY_EXTI_LINE EXTI_0
|
|
||||||
#define WAKEUP_KEY_EXTI_PORT_SOURCE GPIO_PORT_SOURCE_GPIOA
|
|
||||||
#define WAKEUP_KEY_EXTI_PIN_SOURCE GPIO_PIN_SOURCE_0
|
|
||||||
#define WAKEUP_KEY_EXTI_IRQn EXTI0_IRQn
|
|
||||||
|
|
||||||
/* function declarations */
|
|
||||||
/* configure led GPIO */
|
|
||||||
void gd_led_init(led_typedef_enum lednum);
|
|
||||||
/* turn on selected led */
|
|
||||||
void gd_led_on(led_typedef_enum lednum);
|
|
||||||
/* turn off selected led */
|
|
||||||
void gd_led_off(led_typedef_enum lednum);
|
|
||||||
/* toggle the selected led */
|
|
||||||
void gd_led_toggle(led_typedef_enum lednum);
|
|
||||||
/* configure key */
|
|
||||||
void gd_key_init(key_typedef_enum keynum, keymode_typedef_enum keymode);
|
|
||||||
/* return the selected key state */
|
|
||||||
uint8_t gd_key_state_get(key_typedef_enum keynum);
|
|
||||||
/* configure COM port */
|
|
||||||
void gd_com_init(uint32_t usart_periph);
|
|
||||||
|
|
||||||
/* Defines for LED functions Defines for LED / Key functions to new / general API */
|
|
||||||
#define gd_rvstar_led_init gd_led_init
|
|
||||||
#define gd_rvstar_led_on gd_led_on
|
|
||||||
#define gd_rvstar_led_off gd_led_off
|
|
||||||
#define gd_rvstar_led_toggle gd_led_toggle
|
|
||||||
|
|
||||||
#define gd_rvstar_key_init gd_key_init
|
|
||||||
#define gd_rvstar_key_state_get gd_key_state_get
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* GD32VF103V_RVSTART_H */
|
|
||||||
|
|
||||||
|
|
@ -1,20 +0,0 @@
|
||||||
// See LICENSE for license details.
|
|
||||||
#ifndef _NUCLEI_SDK_HAL_H
|
|
||||||
#define _NUCLEI_SDK_HAL_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#include "gd32vf103v_rvstar.h"
|
|
||||||
|
|
||||||
#define SOC_DEBUG_UART GD32_COM0
|
|
||||||
|
|
||||||
#ifndef NUCLEI_BANNER
|
|
||||||
#define NUCLEI_BANNER 1
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,191 +0,0 @@
|
||||||
/*!
|
|
||||||
* \file gd32vf103c_start.c
|
|
||||||
* \brief firmware functions to manage leds, keys, COM ports
|
|
||||||
*
|
|
||||||
* \version 2020-02-05, V1.0.0, rvstar board functions for GD32VF103
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "gd32vf103v_rvstar.h"
|
|
||||||
|
|
||||||
/* private variables */
|
|
||||||
static const uint32_t GPIO_PORT[LEDn] = {LEDG_GPIO_PORT,LEDB_GPIO_PORT,LEDR_GPIO_PORT};
|
|
||||||
|
|
||||||
static const uint32_t GPIO_PIN[LEDn] = {LEDG_PIN,LEDB_PIN,LEDR_PIN};
|
|
||||||
|
|
||||||
static const rcu_periph_enum GPIO_CLK[LEDn] = {LEDG_GPIO_CLK,LEDB_GPIO_CLK,LEDR_GPIO_CLK};
|
|
||||||
|
|
||||||
static const uint32_t KEY_PORT[KEYn] = {WAKEUP_KEY_GPIO_PORT};
|
|
||||||
|
|
||||||
static const uint32_t KEY_PIN[KEYn] = {WAKEUP_KEY_PIN};
|
|
||||||
|
|
||||||
static const rcu_periph_enum KEY_CLK[KEYn] = {WAKEUP_KEY_GPIO_CLK};
|
|
||||||
|
|
||||||
static const exti_line_enum KEY_EXTI_LINE[KEYn] = {WAKEUP_KEY_EXTI_LINE};
|
|
||||||
|
|
||||||
static const uint8_t KEY_PORT_SOURCE[KEYn] = {WAKEUP_KEY_EXTI_PORT_SOURCE};
|
|
||||||
|
|
||||||
static const uint8_t KEY_PIN_SOURCE[KEYn] = {WAKEUP_KEY_EXTI_PIN_SOURCE};
|
|
||||||
|
|
||||||
static const uint8_t KEY_IRQn[KEYn] = {WAKEUP_KEY_EXTI_IRQn};
|
|
||||||
|
|
||||||
/* eval board low layer private functions */
|
|
||||||
/*!
|
|
||||||
* \brief configure led GPIO
|
|
||||||
* \param[in] lednum: specify the led to be configured
|
|
||||||
* \arg LED1
|
|
||||||
* \param[out] none
|
|
||||||
* \retval none
|
|
||||||
*/
|
|
||||||
void gd_led_init(led_typedef_enum lednum)
|
|
||||||
{
|
|
||||||
/* enable the led clock */
|
|
||||||
rcu_periph_clock_enable(GPIO_CLK[lednum]);
|
|
||||||
/* configure led GPIO port */
|
|
||||||
gpio_init(GPIO_PORT[lednum], GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PIN[lednum]);
|
|
||||||
GPIO_BOP(GPIO_PORT[lednum]) = GPIO_PIN[lednum];
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* \brief turn on selected led
|
|
||||||
* \param[in] lednum: specify the led to be turned on
|
|
||||||
* \arg LED1
|
|
||||||
* \param[out] none
|
|
||||||
* \retval none
|
|
||||||
*/
|
|
||||||
void gd_led_on(led_typedef_enum lednum)
|
|
||||||
{
|
|
||||||
GPIO_BC(GPIO_PORT[lednum]) = GPIO_PIN[lednum];
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* \brief turn off selected led
|
|
||||||
* \param[in] lednum: specify the led to be turned off
|
|
||||||
* \arg LED1
|
|
||||||
* \param[out] none
|
|
||||||
* \retval none
|
|
||||||
*/
|
|
||||||
void gd_led_off(led_typedef_enum lednum)
|
|
||||||
{
|
|
||||||
GPIO_BOP(GPIO_PORT[lednum]) = GPIO_PIN[lednum];
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* \brief toggle selected led
|
|
||||||
* \param[in] lednum: specify the led to be toggled
|
|
||||||
* \arg LED1
|
|
||||||
* \param[out] none
|
|
||||||
* \retval none
|
|
||||||
*/
|
|
||||||
void gd_led_toggle(led_typedef_enum lednum)
|
|
||||||
{
|
|
||||||
gpio_bit_write(GPIO_PORT[lednum], GPIO_PIN[lednum],
|
|
||||||
(bit_status)(1-gpio_input_bit_get(GPIO_PORT[lednum], GPIO_PIN[lednum])));
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* \brief configure key
|
|
||||||
* \param[in] keynum: specify the key to be configured
|
|
||||||
* \arg KEY_WAKEUP: wakeup key
|
|
||||||
* \param[in] keymode: specify button mode
|
|
||||||
* \arg KEY_MODE_GPIO: key will be used as simple IO
|
|
||||||
* \arg KEY_MODE_EXTI: key will be connected to EXTI line with interrupt
|
|
||||||
* \param[out] none
|
|
||||||
* \retval none
|
|
||||||
*/
|
|
||||||
void gd_key_init(key_typedef_enum keynum, keymode_typedef_enum keymode)
|
|
||||||
{
|
|
||||||
/* enable the key clock */
|
|
||||||
rcu_periph_clock_enable(KEY_CLK[keynum]);
|
|
||||||
rcu_periph_clock_enable(RCU_AF);
|
|
||||||
|
|
||||||
/* configure button pin as input */
|
|
||||||
gpio_init(KEY_PORT[keynum], GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, KEY_PIN[keynum]);
|
|
||||||
|
|
||||||
if (keymode == KEY_MODE_EXTI) {
|
|
||||||
/* enable and set key EXTI interrupt to the lowest priority */
|
|
||||||
ECLIC_EnableIRQ(KEY_IRQn[keynum]);
|
|
||||||
ECLIC_SetLevelIRQ(KEY_IRQn[keynum],1);
|
|
||||||
ECLIC_SetPriorityIRQ(KEY_IRQn[keynum],1);
|
|
||||||
|
|
||||||
/* connect key EXTI line to key GPIO pin */
|
|
||||||
gpio_exti_source_select(KEY_PORT_SOURCE[keynum], KEY_PIN_SOURCE[keynum]);
|
|
||||||
|
|
||||||
/* configure key EXTI line */
|
|
||||||
exti_init(KEY_EXTI_LINE[keynum], EXTI_INTERRUPT, EXTI_TRIG_FALLING);
|
|
||||||
exti_interrupt_flag_clear(KEY_EXTI_LINE[keynum]);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* \brief return the selected key state
|
|
||||||
* \param[in] keynum: specify the key to be checked
|
|
||||||
* \arg KEY_WAKEUP: wakeup key
|
|
||||||
* \param[out] none
|
|
||||||
* \retval the key's GPIO pin value
|
|
||||||
*/
|
|
||||||
uint8_t gd_key_state_get(key_typedef_enum keynum)
|
|
||||||
{
|
|
||||||
return gpio_input_bit_get(KEY_PORT[keynum], KEY_PIN[keynum]);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* \brief configure COM port
|
|
||||||
* \param[in] com: COM on the board
|
|
||||||
* \arg GD32_COM0: COM0 on the board
|
|
||||||
* \param[out] none
|
|
||||||
* \retval none
|
|
||||||
*/
|
|
||||||
void gd_com_init(uint32_t usart_periph)
|
|
||||||
{
|
|
||||||
/* enable GPIO TX and RX clock */
|
|
||||||
rcu_periph_clock_enable(GD32_COM_TX_GPIO_CLK);
|
|
||||||
rcu_periph_clock_enable(GD32_COM_RX_GPIO_CLK);
|
|
||||||
|
|
||||||
/* enable USART clock */
|
|
||||||
rcu_periph_clock_enable(GD32_COM_CLK);
|
|
||||||
|
|
||||||
/* connect port to USARTx_Tx */
|
|
||||||
gpio_init(GD32_COM_TX_GPIO_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GD32_COM_TX_PIN);
|
|
||||||
|
|
||||||
/* connect port to USARTx_Rx */
|
|
||||||
gpio_init(GD32_COM_RX_GPIO_PORT, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GD32_COM_RX_PIN);
|
|
||||||
|
|
||||||
/* USART configure */
|
|
||||||
usart_deinit(usart_periph);
|
|
||||||
usart_baudrate_set(usart_periph, 115200U);
|
|
||||||
usart_word_length_set(usart_periph, USART_WL_8BIT);
|
|
||||||
usart_stop_bit_set(usart_periph, USART_STB_1BIT);
|
|
||||||
usart_parity_config(usart_periph, USART_PM_NONE);
|
|
||||||
usart_hardware_flow_rts_config(usart_periph, USART_RTS_DISABLE);
|
|
||||||
usart_hardware_flow_cts_config(usart_periph, USART_CTS_DISABLE);
|
|
||||||
usart_receive_config(usart_periph, USART_RECEIVE_ENABLE);
|
|
||||||
usart_transmit_config(usart_periph, USART_TRANSMIT_ENABLE);
|
|
||||||
usart_enable(usart_periph);
|
|
||||||
}
|
|
||||||
|
|
@ -1,117 +0,0 @@
|
||||||
/*!
|
|
||||||
\file drv_usb_core.h
|
|
||||||
\brief USB core low level driver header file
|
|
||||||
|
|
||||||
\version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __DRV_USB_CORE_H
|
|
||||||
#define __DRV_USB_CORE_H
|
|
||||||
|
|
||||||
#include "drv_usb_regs.h"
|
|
||||||
#include "usb_ch9_std.h"
|
|
||||||
|
|
||||||
#define USB_FS_EP0_MAX_LEN 64U /* maximum packet size of EndPoint0 */
|
|
||||||
|
|
||||||
#define HC_MAX_PACKET_COUNT 140U /* maximum packet count */
|
|
||||||
|
|
||||||
#define EP_ID(x) ((uint8_t)((x) & 0x7FU)) /* endpoint number */
|
|
||||||
#define EP_DIR(x) ((uint8_t)((x) >> 7)) /* endpoint direction */
|
|
||||||
|
|
||||||
enum _usb_eptype {
|
|
||||||
USB_EPTYPE_CTRL = 0U, /*!< control endpoint type */
|
|
||||||
USB_EPTYPE_ISOC = 1U, /*!< isochronous endpoint type */
|
|
||||||
USB_EPTYPE_BULK = 2U, /*!< bulk endpoint type */
|
|
||||||
USB_EPTYPE_INTR = 3U, /*!< interrupt endpoint type */
|
|
||||||
USB_EPTYPE_MASK = 3U, /*!< endpoint type mask */
|
|
||||||
};
|
|
||||||
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
USB_OTG_OK = 0, /*!< USB OTG status OK*/
|
|
||||||
USB_OTG_FAIL /*!< USB OTG status fail*/
|
|
||||||
} usb_otg_status;
|
|
||||||
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
USB_OK = 0, /*!< USB status OK*/
|
|
||||||
USB_FAIL /*!< USB status fail*/
|
|
||||||
} usb_status;
|
|
||||||
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
USB_USE_FIFO, /*!< USB use FIFO transfer mode */
|
|
||||||
USB_USE_DMA /*!< USB use DMA transfer mode */
|
|
||||||
} usb_transfer_mode;
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint8_t core_enum; /*!< USB core type */
|
|
||||||
uint8_t core_speed; /*!< USB core speed */
|
|
||||||
uint8_t num_pipe; /*!< USB host channel numbers */
|
|
||||||
uint8_t num_ep; /*!< USB device endpoint numbers */
|
|
||||||
uint8_t transfer_mode; /*!< USB transfer mode */
|
|
||||||
uint8_t phy_itf; /*!< USB core PHY interface */
|
|
||||||
uint8_t sof_enable; /*!< USB SOF output */
|
|
||||||
uint8_t low_power; /*!< USB low power */
|
|
||||||
} usb_core_basic;
|
|
||||||
|
|
||||||
/* function declarations */
|
|
||||||
|
|
||||||
/* config core capabilities */
|
|
||||||
usb_status usb_basic_init (usb_core_basic *usb_basic,
|
|
||||||
usb_core_regs *usb_regs,
|
|
||||||
usb_core_enum usb_core);
|
|
||||||
|
|
||||||
/*initializes the USB controller registers and prepares the core device mode or host mode operation*/
|
|
||||||
usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs);
|
|
||||||
|
|
||||||
/* read a packet from the Rx FIFO associated with the endpoint */
|
|
||||||
void *usb_rxfifo_read (usb_core_regs *core_regs, uint8_t *dest_buf, uint16_t byte_count);
|
|
||||||
|
|
||||||
/* write a packet into the Tx FIFO associated with the endpoint */
|
|
||||||
usb_status usb_txfifo_write (usb_core_regs *usb_regs,
|
|
||||||
uint8_t *src_buf,
|
|
||||||
uint8_t fifo_num,
|
|
||||||
uint16_t byte_count);
|
|
||||||
|
|
||||||
/* flush a Tx FIFO or all Tx FIFOs */
|
|
||||||
usb_status usb_txfifo_flush (usb_core_regs *usb_regs, uint8_t fifo_num);
|
|
||||||
|
|
||||||
/* flush the entire Rx FIFO */
|
|
||||||
usb_status usb_rxfifo_flush (usb_core_regs *usb_regs);
|
|
||||||
|
|
||||||
/* get the global interrupts */
|
|
||||||
static inline uint32_t usb_coreintr_get(usb_core_regs *usb_regs)
|
|
||||||
{
|
|
||||||
return usb_regs->gr->GINTEN & usb_regs->gr->GINTF;
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* __DRV_USB_CORE_H */
|
|
||||||
|
|
@ -1,217 +0,0 @@
|
||||||
/*!
|
|
||||||
\file drv_usb_dev.h
|
|
||||||
\brief USB device low level driver header file
|
|
||||||
|
|
||||||
\version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __DRV_USB_DEV_H
|
|
||||||
#define __DRV_USB_DEV_H
|
|
||||||
|
|
||||||
#include "drv_usb_core.h"
|
|
||||||
|
|
||||||
enum usb_ctl_status {
|
|
||||||
USB_CTL_IDLE = 0U, /*!< USB control transfer idle state */
|
|
||||||
USB_CTL_DATA_IN, /*!< USB control transfer data in state */
|
|
||||||
USB_CTL_LAST_DATA_IN, /*!< USB control transfer last data in state */
|
|
||||||
USB_CTL_DATA_OUT, /*!< USB control transfer data out state */
|
|
||||||
USB_CTL_LAST_DATA_OUT, /*!< USB control transfer last data out state */
|
|
||||||
USB_CTL_STATUS_IN, /*!< USB control transfer status in state*/
|
|
||||||
USB_CTL_STATUS_OUT /*!< USB control transfer status out state */
|
|
||||||
};
|
|
||||||
|
|
||||||
#define EP_IN(x) ((uint8_t)(0x80U | (x))) /*!< device IN endpoint */
|
|
||||||
#define EP_OUT(x) ((uint8_t)(x)) /*!< device OUT endpoint */
|
|
||||||
|
|
||||||
/* USB descriptor */
|
|
||||||
typedef struct _usb_desc {
|
|
||||||
uint8_t *dev_desc; /*!< device descriptor */
|
|
||||||
uint8_t *config_desc; /*!< config descriptor */
|
|
||||||
uint8_t *bos_desc; /*!< BOS descriptor */
|
|
||||||
|
|
||||||
void* const *strings; /*!< string descriptor */
|
|
||||||
} usb_desc;
|
|
||||||
|
|
||||||
/* USB power management */
|
|
||||||
typedef struct _usb_pm {
|
|
||||||
uint8_t power_mode; /*!< power mode */
|
|
||||||
uint8_t power_low; /*!< power low */
|
|
||||||
uint8_t dev_remote_wakeup; /*!< remote wakeup */
|
|
||||||
uint8_t remote_wakeup_on; /*!< remote wakeup on */
|
|
||||||
} usb_pm;
|
|
||||||
|
|
||||||
/* USB control information */
|
|
||||||
typedef struct _usb_control {
|
|
||||||
usb_req req; /*!< USB standard device request */
|
|
||||||
|
|
||||||
uint8_t ctl_state; /*!< USB control transfer state */
|
|
||||||
uint8_t ctl_zlp; /*!< zero length package */
|
|
||||||
} usb_control;
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
struct {
|
|
||||||
uint8_t num: 4; /*!< the endpoint number.it can be from 0 to 6 */
|
|
||||||
uint8_t pad: 3; /*!< padding between number and direction */
|
|
||||||
uint8_t dir: 1; /*!< the endpoint direction */
|
|
||||||
} ep_addr;
|
|
||||||
|
|
||||||
uint8_t ep_type; /*!< USB endpoint type */
|
|
||||||
uint8_t ep_stall; /*!< USB endpoint stall status */
|
|
||||||
|
|
||||||
uint8_t frame_num; /*!< number of frame */
|
|
||||||
uint16_t max_len; /*!< Maximum packet length */
|
|
||||||
|
|
||||||
/* transaction level variables */
|
|
||||||
uint8_t *xfer_buf; /*!< transmit buffer */
|
|
||||||
uint32_t xfer_len; /*!< transmit buffer length */
|
|
||||||
uint32_t xfer_count; /*!< transmit buffer count */
|
|
||||||
|
|
||||||
uint32_t remain_len; /*!< remain packet length */
|
|
||||||
|
|
||||||
uint32_t dma_addr; /*!< DMA address */
|
|
||||||
} usb_transc;
|
|
||||||
|
|
||||||
typedef struct _usb_core_driver usb_dev;
|
|
||||||
|
|
||||||
typedef struct _usb_class_core
|
|
||||||
{
|
|
||||||
uint8_t command; /*!< device class request command */
|
|
||||||
uint8_t alter_set; /*!< alternative set */
|
|
||||||
|
|
||||||
uint8_t (*init) (usb_dev *udev, uint8_t config_index); /*!< initialize handler */
|
|
||||||
uint8_t (*deinit) (usb_dev *udev, uint8_t config_index); /*!< de-initialize handler */
|
|
||||||
|
|
||||||
uint8_t (*req_proc) (usb_dev *udev, usb_req *req); /*!< device request handler */
|
|
||||||
|
|
||||||
uint8_t (*data_in) (usb_dev *udev, uint8_t ep_num); /*!< device data in handler */
|
|
||||||
uint8_t (*data_out) (usb_dev *udev, uint8_t ep_num); /*!< device data out handler */
|
|
||||||
|
|
||||||
uint8_t (*SOF) (usb_dev *udev); /*!< Start of frame handler */
|
|
||||||
|
|
||||||
uint8_t (*incomplete_isoc_in) (usb_dev *udev); /*!< Incomplete synchronization IN transfer handler */
|
|
||||||
uint8_t (*incomplete_isoc_out) (usb_dev *udev); /*!< Incomplete synchronization OUT transfer handler */
|
|
||||||
} usb_class_core;
|
|
||||||
|
|
||||||
typedef struct _usb_perp_dev
|
|
||||||
{
|
|
||||||
uint8_t config; /*!< configuration */
|
|
||||||
uint8_t dev_addr; /*!< device address */
|
|
||||||
|
|
||||||
__IO uint8_t cur_status; /*!< current status */
|
|
||||||
__IO uint8_t backup_status; /*!< backup status */
|
|
||||||
|
|
||||||
usb_transc transc_in[USBFS_MAX_TX_FIFOS]; /*!< endpoint IN transaction */
|
|
||||||
usb_transc transc_out[USBFS_MAX_TX_FIFOS]; /*!< endpoint OUT transaction */
|
|
||||||
|
|
||||||
usb_pm pm; /*!< power management */
|
|
||||||
usb_desc desc; /*!< USB descriptors */
|
|
||||||
usb_control control; /*!< USB control information */
|
|
||||||
|
|
||||||
usb_class_core *class_core; /*!< class driver */
|
|
||||||
} usb_perp_dev;
|
|
||||||
|
|
||||||
typedef struct _usb_core_driver
|
|
||||||
{
|
|
||||||
usb_core_basic bp; /*!< USB basic parameters */
|
|
||||||
usb_core_regs regs; /*!< USB registers */
|
|
||||||
usb_perp_dev dev; /*!< USB peripheral device */
|
|
||||||
} usb_core_driver;
|
|
||||||
|
|
||||||
/* function declarations */
|
|
||||||
|
|
||||||
/* initialize USB core registers for device mode */
|
|
||||||
usb_status usb_devcore_init (usb_core_driver *udev);
|
|
||||||
|
|
||||||
/* enable the USB device mode interrupts */
|
|
||||||
usb_status usb_devint_enable (usb_core_driver *udev);
|
|
||||||
|
|
||||||
/* active the usb transaction */
|
|
||||||
usb_status usb_transc_active (usb_core_driver *udev, usb_transc *transc);
|
|
||||||
|
|
||||||
/* deactive the usb transaction */
|
|
||||||
usb_status usb_transc_deactivate (usb_core_driver *udev, usb_transc *transc);
|
|
||||||
|
|
||||||
/* configure usb transaction to start IN transfer */
|
|
||||||
usb_status usb_transc_inxfer (usb_core_driver *udev, usb_transc *transc);
|
|
||||||
|
|
||||||
/* configure usb transaction to start OUT transfer */
|
|
||||||
usb_status usb_transc_outxfer (usb_core_driver *udev, usb_transc *transc);
|
|
||||||
|
|
||||||
/* set the usb transaction STALL status */
|
|
||||||
usb_status usb_transc_stall (usb_core_driver *udev, usb_transc *transc);
|
|
||||||
|
|
||||||
/* clear the usb transaction STALL status */
|
|
||||||
usb_status usb_transc_clrstall (usb_core_driver *udev, usb_transc *transc);
|
|
||||||
|
|
||||||
/* read device all OUT endpoint interrupt register */
|
|
||||||
uint32_t usb_oepintnum_read (usb_core_driver *udev);
|
|
||||||
|
|
||||||
/* read device OUT endpoint interrupt flag register */
|
|
||||||
uint32_t usb_oepintr_read (usb_core_driver *udev, uint8_t ep_num);
|
|
||||||
|
|
||||||
/* read device all IN endpoint interrupt register */
|
|
||||||
uint32_t usb_iepintnum_read (usb_core_driver *udev);
|
|
||||||
|
|
||||||
/* read device IN endpoint interrupt flag register */
|
|
||||||
uint32_t usb_iepintr_read (usb_core_driver *udev, uint8_t ep_num);
|
|
||||||
|
|
||||||
/* config the USB device to be disconnected */
|
|
||||||
void usb_dev_disconnect (usb_core_driver *udev);
|
|
||||||
|
|
||||||
/* config the USB device to be connected */
|
|
||||||
void usb_dev_connect (usb_core_driver *udev);
|
|
||||||
|
|
||||||
/* set the USB device address */
|
|
||||||
void usb_devaddr_set (usb_core_driver *pudev, uint8_t dev_addr);
|
|
||||||
|
|
||||||
/* configures OUT endpoint 0 to receive SETUP packets */
|
|
||||||
void usb_ctlep_startout (usb_core_driver *udev);
|
|
||||||
|
|
||||||
/* active remote wakeup signalling */
|
|
||||||
void usb_rwkup_active (usb_core_driver *udev);
|
|
||||||
|
|
||||||
/* reset remote wakeup signalling */
|
|
||||||
void usb_rwkup_reset (usb_core_driver *udev);
|
|
||||||
|
|
||||||
/* set remote wakeup signalling */
|
|
||||||
void usb_rwkup_set (usb_core_driver *udev);
|
|
||||||
|
|
||||||
/* active USB core clock */
|
|
||||||
void usb_clock_active (usb_core_driver *udev);
|
|
||||||
|
|
||||||
/* usb device suspend */
|
|
||||||
void usb_dev_suspend (usb_core_driver *udev);
|
|
||||||
|
|
||||||
/* stop the device and clean up fifos */
|
|
||||||
void usb_dev_stop (usb_core_driver *udev);
|
|
||||||
|
|
||||||
#endif /* __DRV_USB_DEV_H */
|
|
||||||
|
|
||||||
|
|
@ -1,175 +0,0 @@
|
||||||
/*!
|
|
||||||
\file drv_usb_host.h
|
|
||||||
\brief USB host mode low level driver header file
|
|
||||||
|
|
||||||
\version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __DRV_USB_HOST_H
|
|
||||||
#define __DRV_USB_HOST_H
|
|
||||||
|
|
||||||
#include "drv_usb_regs.h"
|
|
||||||
#include "usb_ch9_std.h"
|
|
||||||
#include "drv_usb_core.h"
|
|
||||||
|
|
||||||
typedef enum _usb_pipe_status
|
|
||||||
{
|
|
||||||
PIPE_IDLE = 0U,
|
|
||||||
PIPE_XF,
|
|
||||||
PIPE_HALTED,
|
|
||||||
PIPE_NAK,
|
|
||||||
PIPE_NYET,
|
|
||||||
PIPE_STALL,
|
|
||||||
PIPE_TRACERR,
|
|
||||||
PIPE_BBERR,
|
|
||||||
PIPE_REQOVR,
|
|
||||||
PIPE_DTGERR,
|
|
||||||
} usb_pipe_staus;
|
|
||||||
|
|
||||||
typedef enum _usb_pipe_mode
|
|
||||||
{
|
|
||||||
PIPE_PERIOD = 0U,
|
|
||||||
PIPE_NON_PERIOD = 1U
|
|
||||||
} usb_pipe_mode;
|
|
||||||
|
|
||||||
typedef enum _usb_urb_state
|
|
||||||
{
|
|
||||||
URB_IDLE = 0U,
|
|
||||||
URB_DONE,
|
|
||||||
URB_NOTREADY,
|
|
||||||
URB_ERROR,
|
|
||||||
URB_STALL
|
|
||||||
} usb_urb_state;
|
|
||||||
|
|
||||||
typedef struct _usb_pipe
|
|
||||||
{
|
|
||||||
uint8_t in_used;
|
|
||||||
uint8_t dev_addr;
|
|
||||||
uint32_t dev_speed;
|
|
||||||
|
|
||||||
struct {
|
|
||||||
uint8_t num;
|
|
||||||
uint8_t dir;
|
|
||||||
uint8_t type;
|
|
||||||
uint16_t mps;
|
|
||||||
} ep;
|
|
||||||
|
|
||||||
uint8_t ping;
|
|
||||||
uint32_t DPID;
|
|
||||||
|
|
||||||
uint8_t *xfer_buf;
|
|
||||||
uint32_t xfer_len;
|
|
||||||
uint32_t xfer_count;
|
|
||||||
|
|
||||||
uint8_t data_toggle_in;
|
|
||||||
uint8_t data_toggle_out;
|
|
||||||
|
|
||||||
__IO uint32_t err_count;
|
|
||||||
__IO usb_pipe_staus pp_status;
|
|
||||||
__IO usb_urb_state urb_state;
|
|
||||||
} usb_pipe;
|
|
||||||
|
|
||||||
|
|
||||||
typedef struct _usb_host_drv
|
|
||||||
{
|
|
||||||
uint8_t rx_buf[512U];
|
|
||||||
__IO uint32_t connect_status;
|
|
||||||
__IO uint32_t port_enabled;
|
|
||||||
__IO uint32_t backup_xfercount[USBFS_MAX_TX_FIFOS];
|
|
||||||
|
|
||||||
usb_pipe pipe[USBFS_MAX_TX_FIFOS];
|
|
||||||
} usb_host_drv;
|
|
||||||
|
|
||||||
typedef struct _usb_core_driver
|
|
||||||
{
|
|
||||||
usb_core_basic bp;
|
|
||||||
|
|
||||||
usb_core_regs regs;
|
|
||||||
|
|
||||||
usb_host_drv host;
|
|
||||||
} usb_core_driver;
|
|
||||||
|
|
||||||
/* initializes USB core for host mode */
|
|
||||||
usb_status usb_host_init (usb_core_driver *pudev);
|
|
||||||
|
|
||||||
/* initialize host pipe */
|
|
||||||
usb_status usb_pipe_init (usb_core_driver *pudev, uint8_t pipe_num);
|
|
||||||
|
|
||||||
/* prepare host pipe for transferring packets */
|
|
||||||
usb_status usb_pipe_xfer (usb_core_driver *pudev, uint8_t pipe_num);
|
|
||||||
|
|
||||||
/* halt host pipe */
|
|
||||||
usb_status usb_pipe_halt (usb_core_driver *pudev, uint8_t pipe_num);
|
|
||||||
|
|
||||||
/* configure host pipe to do ping operation */
|
|
||||||
usb_status usb_pipe_ping (usb_core_driver *pudev, uint8_t pipe_num);
|
|
||||||
|
|
||||||
/* reset host port */
|
|
||||||
uint32_t usb_port_reset (usb_core_driver *pudev);
|
|
||||||
|
|
||||||
/* control the VBUS to power */
|
|
||||||
void usb_portvbus_switch (usb_core_driver *pudev, uint8_t state);
|
|
||||||
|
|
||||||
/* stop the USB host and clean up FIFO */
|
|
||||||
void usb_host_stop (usb_core_driver *pudev);
|
|
||||||
|
|
||||||
//__STATIC_INLINE uint8_t usb_frame_even (usb_core_driver *pudev)
|
|
||||||
uint32_t usb_frame_even (usb_core_driver *pudev);
|
|
||||||
//{
|
|
||||||
// return !(pudev->regs.hr->HFINFR & 0x01U);
|
|
||||||
//}
|
|
||||||
|
|
||||||
//__STATIC_INLINE void usb_phyclock_config (usb_core_driver *pudev, uint8_t clock)
|
|
||||||
void usb_phyclock_config (usb_core_driver *pudev, uint8_t clock) ;
|
|
||||||
//{
|
|
||||||
//pudev->regs.hr->HCTL &= ~HCTL_CLKSEL;
|
|
||||||
// pudev->regs.hr->HCTL |= clock;
|
|
||||||
//}
|
|
||||||
|
|
||||||
uint32_t usb_port_read (usb_core_driver *pudev);
|
|
||||||
//inline uint32_t usb_port_read (usb_core_driver *pudev)
|
|
||||||
//{
|
|
||||||
// return *pudev->regs.HPCS & ~(HPCS_PE | HPCS_PCD | HPCS_PEDC);
|
|
||||||
//}
|
|
||||||
|
|
||||||
uint32_t usb_curspeed_get (usb_core_driver *pudev);
|
|
||||||
|
|
||||||
//inline uint32_t usb_curspeed_get (usb_core_driver *pudev)
|
|
||||||
//{
|
|
||||||
// return *pudev->regs.HPCS & HPCS_PS;
|
|
||||||
//}
|
|
||||||
|
|
||||||
//__STATIC_INLINE uint32_t usb_curframe_get (usb_core_driver *pudev)
|
|
||||||
uint32_t usb_curframe_get (usb_core_driver *pudev);
|
|
||||||
//{
|
|
||||||
// return (pudev->regs.hr->HFINFR & 0xFFFFU);
|
|
||||||
//}
|
|
||||||
|
|
||||||
#endif /* __DRV_USB_HOST_H */
|
|
||||||
|
|
@ -1,61 +0,0 @@
|
||||||
/*!
|
|
||||||
\file drv_usb_hw.h
|
|
||||||
\brief usb hardware configuration header file
|
|
||||||
|
|
||||||
\version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __DRV_USB_HW_H
|
|
||||||
#define __DRV_USB_HW_H
|
|
||||||
|
|
||||||
#include "usb_conf.h"
|
|
||||||
|
|
||||||
/* configure USB clock */
|
|
||||||
void usb_rcu_config (void);
|
|
||||||
|
|
||||||
/* configure USB interrupt */
|
|
||||||
void usb_intr_config (void);
|
|
||||||
|
|
||||||
/* initializes delay unit using Timer2 */
|
|
||||||
void usb_timer_init (void);
|
|
||||||
|
|
||||||
/* delay in micro seconds */
|
|
||||||
void usb_udelay (const uint32_t usec);
|
|
||||||
|
|
||||||
/* delay in milli seconds */
|
|
||||||
void usb_mdelay (const uint32_t msec);
|
|
||||||
|
|
||||||
// Functions for USE_HOST_MODE
|
|
||||||
/* configure USB VBus */
|
|
||||||
void usb_vbus_config (void);
|
|
||||||
/* drive usb VBus */
|
|
||||||
void usb_vbus_drive (uint8_t State);
|
|
||||||
|
|
||||||
#endif /* __DRV_USB_HW_H */
|
|
||||||
|
|
@ -1,666 +0,0 @@
|
||||||
/*!
|
|
||||||
\file drv_usb_regs.h
|
|
||||||
\brief USB cell registers definition and handle macros
|
|
||||||
|
|
||||||
\version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __DRV_USB_REGS_H
|
|
||||||
#define __DRV_USB_REGS_H
|
|
||||||
|
|
||||||
#include "usb_conf.h"
|
|
||||||
|
|
||||||
#define USBHS_REG_BASE 0x40040000L /*!< base address of USBHS registers */
|
|
||||||
#define USBFS_REG_BASE 0x50000000L /*!< base address of USBFS registers */
|
|
||||||
|
|
||||||
#define USBFS_MAX_TX_FIFOS 15 /*!< FIFO number */
|
|
||||||
|
|
||||||
#define USBFS_MAX_PACKET_SIZE 64U /*!< USBFS max packet size */
|
|
||||||
#define USBFS_MAX_CHANNEL_COUNT 8U /*!< USBFS host channel count */
|
|
||||||
#define USBFS_MAX_EP_COUNT 4U /*!< USBFS device endpoint count */
|
|
||||||
#define USBFS_MAX_FIFO_WORDLEN 320U /*!< USBFS max fifo size in words */
|
|
||||||
|
|
||||||
#define USBHS_MAX_PACKET_SIZE 512U /*!< USBHS max packet size */
|
|
||||||
#define USBHS_MAX_CHANNEL_COUNT 12U /*!< USBHS host channel count */
|
|
||||||
#define USBHS_MAX_EP_COUNT 6U /*!< USBHS device endpoint count */
|
|
||||||
#define USBHS_MAX_FIFO_WORDLEN 1280U /*!< USBHS max fifo size in words */
|
|
||||||
|
|
||||||
#define USB_DATA_FIFO_OFFSET 0x1000U /*!< USB data fifo offset */
|
|
||||||
#define USB_DATA_FIFO_SIZE 0x1000U /*!< USB data fifo size */
|
|
||||||
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
USB_CORE_ENUM_HS = 0, /*!< USB core type is HS */
|
|
||||||
USB_CORE_ENUM_FS = 1 /*!< USB core type is FS */
|
|
||||||
} usb_core_enum;
|
|
||||||
|
|
||||||
enum usb_reg_offset {
|
|
||||||
USB_REG_OFFSET_CORE = 0x0000U, /*!< global OTG control and status register */
|
|
||||||
USB_REG_OFFSET_DEV = 0x0800U, /*!< device mode control and status registers */
|
|
||||||
USB_REG_OFFSET_EP = 0x0020U,
|
|
||||||
USB_REG_OFFSET_EP_IN = 0x0900U, /*!< device IN endpoint 0 control register */
|
|
||||||
USB_REG_OFFSET_EP_OUT = 0x0B00U, /*!< device OUT endpoint 0 control register */
|
|
||||||
USB_REG_OFFSET_HOST = 0x0400U, /*!< host control register */
|
|
||||||
USB_REG_OFFSET_CH = 0x0020U,
|
|
||||||
USB_REG_OFFSET_PORT = 0x0440U, /*!< host port control and status register */
|
|
||||||
USB_REG_OFFSET_CH_INOUT = 0x0500U, /*!< Host channel-x control registers */
|
|
||||||
USB_REG_OFFSET_PWRCLKCTL = 0x0E00U, /*!< power and clock register */
|
|
||||||
};
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
__IO uint32_t GOTGCS; /*!< USB global OTG control and status register 000h */
|
|
||||||
__IO uint32_t GOTGINTF; /*!< USB global OTG interrupt flag register 004h */
|
|
||||||
__IO uint32_t GAHBCS; /*!< USB global AHB control and status register 008h */
|
|
||||||
__IO uint32_t GUSBCS; /*!< USB global USB control and status register 00Ch */
|
|
||||||
__IO uint32_t GRSTCTL; /*!< USB global reset control register 010h */
|
|
||||||
__IO uint32_t GINTF; /*!< USB global interrupt flag register 014h */
|
|
||||||
__IO uint32_t GINTEN; /*!< USB global interrupt enable register 018h */
|
|
||||||
__IO uint32_t GRSTATR; /*!< USB receive status debug read register 01Ch */
|
|
||||||
__IO uint32_t GRSTATP; /*!< USB receive status and pop register 020h */
|
|
||||||
__IO uint32_t GRFLEN; /*!< USB global receive FIFO length register 024h */
|
|
||||||
__IO uint32_t DIEP0TFLEN_HNPTFLEN; /*!< USB device IN endpoint 0/host non-periodic transmit FIFO length register 028h */
|
|
||||||
__IO uint32_t HNPTFQSTAT; /*!< USB host non-periodic FIFO/queue status register 02Ch */
|
|
||||||
uint32_t Reserved30[2]; /*!< Reserved 030h */
|
|
||||||
__IO uint32_t GCCFG; /*!< USB global core configuration register 038h */
|
|
||||||
__IO uint32_t CID; /*!< USB core ID register 03Ch */
|
|
||||||
uint32_t Reserved40[48]; /*!< Reserved 040h-0FFh */
|
|
||||||
__IO uint32_t HPTFLEN; /*!< USB host periodic transmit FIFO length register 100h */
|
|
||||||
__IO uint32_t DIEPTFLEN[15]; /*!< USB device IN endpoint transmit FIFO length register 104h */
|
|
||||||
} usb_gr;
|
|
||||||
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
__IO uint32_t HCTL; /*!< USB host control register 400h */
|
|
||||||
__IO uint32_t HFT; /*!< USB host frame interval register 404h */
|
|
||||||
__IO uint32_t HFINFR; /*!< USB host frame information remaining register 408h */
|
|
||||||
uint32_t Reserved40C; /*!< Reserved 40Ch */
|
|
||||||
__IO uint32_t HPTFQSTAT; /*!< USB host periodic transmit FIFO/queue status register 410h */
|
|
||||||
__IO uint32_t HACHINT; /*!< USB host all channels interrupt register 414h */
|
|
||||||
__IO uint32_t HACHINTEN; /*!< USB host all channels interrupt enable register 418h */
|
|
||||||
} usb_hr;
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
__IO uint32_t HCHCTL; /*!< USB host channel control register 500h */
|
|
||||||
__IO uint32_t HCHSTCTL; /*!< Reserved 504h */
|
|
||||||
__IO uint32_t HCHINTF; /*!< USB host channel interrupt flag register 508h */
|
|
||||||
__IO uint32_t HCHINTEN; /*!< USB host channel interrupt enable register 50Ch */
|
|
||||||
__IO uint32_t HCHLEN; /*!< USB host channel transfer length register 510h */
|
|
||||||
__IO uint32_t HCHDMAADDR; /*!< USB host channel-x DMA address register 514h*/
|
|
||||||
uint32_t Reserved[2];
|
|
||||||
} usb_pr;
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
__IO uint32_t DCFG; /*!< USB device configuration register 800h */
|
|
||||||
__IO uint32_t DCTL; /*!< USB device control register 804h */
|
|
||||||
__IO uint32_t DSTAT; /*!< USB device status register 808h */
|
|
||||||
uint32_t Reserved0C; /*!< Reserved 80Ch */
|
|
||||||
__IO uint32_t DIEPINTEN; /*!< USB device IN endpoint common interrupt enable register 810h */
|
|
||||||
__IO uint32_t DOEPINTEN; /*!< USB device OUT endpoint common interrupt enable register 814h */
|
|
||||||
__IO uint32_t DAEPINT; /*!< USB device all endpoints interrupt register 818h */
|
|
||||||
__IO uint32_t DAEPINTEN; /*!< USB device all endpoints interrupt enable register 81Ch */
|
|
||||||
uint32_t Reserved20; /*!< Reserved 820h */
|
|
||||||
uint32_t Reserved24; /*!< Reserved 824h */
|
|
||||||
__IO uint32_t DVBUSDT; /*!< USB device VBUS discharge time register 828h */
|
|
||||||
__IO uint32_t DVBUSPT; /*!< USB device VBUS pulsing time register 82Ch */
|
|
||||||
__IO uint32_t DTHRCTL; /*!< dev thr 830h */
|
|
||||||
__IO uint32_t DIEPFEINTEN; /*!< USB Device IN endpoint FIFO empty interrupt enable register 834h */
|
|
||||||
__IO uint32_t DEP1INT; /*!< USB device endpoint 1 interrupt register 838h */
|
|
||||||
__IO uint32_t DEP1INTEN; /*!< USB device endpoint 1 interrupt enable register 83Ch */
|
|
||||||
uint32_t Reserved40; /*!< Reserved 840h */
|
|
||||||
__IO uint32_t DIEP1INTEN; /*!< USB device IN endpoint-1 interrupt enable register 844h */
|
|
||||||
uint32_t Reserved48[15]; /*!< Reserved 848-880h */
|
|
||||||
__IO uint32_t DOEP1INTEN; /*!< USB device OUT endpoint-1 interrupt enable register 884h */
|
|
||||||
} usb_dr;
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
__IO uint32_t DIEPCTL; /*!< USB device IN endpoint control register 900h + (EpNum * 20h) + 00h */
|
|
||||||
uint32_t Reserved04; /*!< Reserved 900h + (EpNum * 20h) + 04h */
|
|
||||||
__IO uint32_t DIEPINTF; /*!< USB device IN endpoint interrupt flag register 900h + (EpNum * 20h) + 08h */
|
|
||||||
uint32_t Reserved0C; /*!< Reserved 900h + (EpNum * 20h) + 0Ch */
|
|
||||||
__IO uint32_t DIEPLEN; /*!< USB device IN endpoint transfer length register 900h + (EpNum * 20h) + 10h */
|
|
||||||
__IO uint32_t DIEPDMAADDR; /*!< Device IN endpoint-x DMA address register 900h + (EpNum * 20h) + 14h */
|
|
||||||
__IO uint32_t DIEPTFSTAT; /*!< USB device IN endpoint transmit FIFO status register 900h + (EpNum * 20h) + 18h */
|
|
||||||
} usb_erin;
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
__IO uint32_t DOEPCTL; /*!< USB device IN endpoint control register B00h + (EpNum * 20h) + 00h */
|
|
||||||
uint32_t Reserved04; /*!< Reserved B00h + (EpNum * 20h) + 04h */
|
|
||||||
__IO uint32_t DOEPINTF; /*!< USB device IN endpoint interrupt flag register B00h + (EpNum * 20h) + 08h */
|
|
||||||
uint32_t Reserved0C; /*!< Reserved B00h + (EpNum * 20h) + 0Ch */
|
|
||||||
__IO uint32_t DOEPLEN; /*!< USB device IN endpoint transfer length register B00h + (EpNum * 20h) + 10h */
|
|
||||||
__IO uint32_t DOEPDMAADDR; /*!< Device OUT endpoint-x DMA address register B00h + (EpNum * 20h) + 0Ch */
|
|
||||||
} usb_erout;
|
|
||||||
|
|
||||||
typedef struct _usb_regs
|
|
||||||
{
|
|
||||||
usb_gr *gr; /*!< USBFS global registers */
|
|
||||||
usb_dr *dr; /*!< Device control and status registers */
|
|
||||||
usb_hr *hr; /*!< Host control and status registers */
|
|
||||||
usb_erin *er_in[6]; /*!< USB device IN endpoint register */
|
|
||||||
usb_erout *er_out[6]; /*!< USB device OUT endpoint register */
|
|
||||||
usb_pr *pr[15]; /*!< USB Host channel-x control register */
|
|
||||||
|
|
||||||
__IO uint32_t *HPCS; /*!< USB host port control and status register */
|
|
||||||
__IO uint32_t *DFIFO[USBFS_MAX_TX_FIFOS];
|
|
||||||
__IO uint32_t *PWRCLKCTL; /*!< USB power and clock control register */
|
|
||||||
} usb_core_regs;
|
|
||||||
|
|
||||||
/* global OTG control and status register bits definitions */
|
|
||||||
#define GOTGCS_BSV BIT(19) /*!< B-Session Valid */
|
|
||||||
#define GOTGCS_ASV BIT(18) /*!< A-session valid */
|
|
||||||
#define GOTGCS_DI BIT(17) /*!< debounce interval */
|
|
||||||
#define GOTGCS_CIDPS BIT(16) /*!< id pin status */
|
|
||||||
#define GOTGCS_DHNPEN BIT(11) /*!< device HNP enable */
|
|
||||||
#define GOTGCS_HHNPEN BIT(10) /*!< host HNP enable */
|
|
||||||
#define GOTGCS_HNPREQ BIT(9) /*!< HNP request */
|
|
||||||
#define GOTGCS_HNPS BIT(8) /*!< HNP successes */
|
|
||||||
#define GOTGCS_SRPREQ BIT(1) /*!< SRP request */
|
|
||||||
#define GOTGCS_SRPS BIT(0) /*!< SRP successes */
|
|
||||||
|
|
||||||
/* global OTG interrupt flag register bits definitions */
|
|
||||||
#define GOTGINTF_DF BIT(19) /*!< debounce finish */
|
|
||||||
#define GOTGINTF_ADTO BIT(18) /*!< A-device timeout */
|
|
||||||
#define GOTGINTF_HNPDET BIT(17) /*!< host negotiation request detected */
|
|
||||||
#define GOTGINTF_HNPEND BIT(9) /*!< HNP end */
|
|
||||||
#define GOTGINTF_SRPEND BIT(8) /*!< SRP end */
|
|
||||||
#define GOTGINTF_SESEND BIT(2) /*!< session end */
|
|
||||||
|
|
||||||
/* global AHB control and status register bits definitions */
|
|
||||||
#define GAHBCS_PTXFTH BIT(8) /*!< periodic Tx FIFO threshold */
|
|
||||||
#define GAHBCS_TXFTH BIT(7) /*!< tx FIFO threshold */
|
|
||||||
#define GAHBCS_DMAEN BIT(5) /*!< DMA function Enable */
|
|
||||||
#define GAHBCS_BURST BITS(1, 4) /*!< the AHB burst type used by DMA */
|
|
||||||
#define GAHBCS_GINTEN BIT(0) /*!< global interrupt enable */
|
|
||||||
|
|
||||||
/* global USB control and status register bits definitions */
|
|
||||||
#define GUSBCS_FDM BIT(30) /*!< force device mode */
|
|
||||||
#define GUSBCS_FHM BIT(29) /*!< force host mode */
|
|
||||||
#define GUSBCS_ULPIEOI BIT(21) /*!< ULPI external over-current indicator */
|
|
||||||
#define GUSBCS_ULPIEVD BIT(20) /*!< ULPI external VBUS driver */
|
|
||||||
#define GUSBCS_UTT BITS(10, 13) /*!< USB turnaround time */
|
|
||||||
#define GUSBCS_HNPCEN BIT(9) /*!< HNP capability enable */
|
|
||||||
#define GUSBCS_SRPCEN BIT(8) /*!< SRP capability enable */
|
|
||||||
#define GUSBCS_EMBPHY BIT(6) /*!< embedded PHY selected */
|
|
||||||
#define GUSBCS_TOC BITS(0, 2) /*!< timeout calibration */
|
|
||||||
|
|
||||||
/* global reset control register bits definitions */
|
|
||||||
#define GRSTCTL_DMAIDL BIT(31) /*!< DMA idle state */
|
|
||||||
#define GRSTCTL_DMABSY BIT(30) /*!< DMA busy */
|
|
||||||
#define GRSTCTL_TXFNUM BITS(6, 10) /*!< tx FIFO number */
|
|
||||||
#define GRSTCTL_TXFF BIT(5) /*!< tx FIFO flush */
|
|
||||||
#define GRSTCTL_RXFF BIT(4) /*!< rx FIFO flush */
|
|
||||||
#define GRSTCTL_HFCRST BIT(2) /*!< host frame counter reset */
|
|
||||||
#define GRSTCTL_HCSRST BIT(1) /*!< HCLK soft reset */
|
|
||||||
#define GRSTCTL_CSRST BIT(0) /*!< core soft reset */
|
|
||||||
|
|
||||||
/* global interrupt flag register bits definitions */
|
|
||||||
#define GINTF_WKUPIF BIT(31) /*!< wakeup interrupt flag */
|
|
||||||
#define GINTF_SESIF BIT(30) /*!< session interrupt flag */
|
|
||||||
#define GINTF_DISCIF BIT(29) /*!< disconnect interrupt flag */
|
|
||||||
#define GINTF_IDPSC BIT(28) /*!< id pin status change */
|
|
||||||
#define GINTF_PTXFEIF BIT(26) /*!< periodic tx FIFO empty interrupt flag */
|
|
||||||
#define GINTF_HCIF BIT(25) /*!< host channels interrupt flag */
|
|
||||||
#define GINTF_HPIF BIT(24) /*!< host port interrupt flag */
|
|
||||||
#define GINTF_PXNCIF BIT(21) /*!< periodic transfer not complete interrupt flag */
|
|
||||||
#define GINTF_ISOONCIF BIT(21) /*!< isochronous OUT transfer not complete interrupt flag */
|
|
||||||
#define GINTF_ISOINCIF BIT(20) /*!< isochronous IN transfer not complete interrupt flag */
|
|
||||||
#define GINTF_OEPIF BIT(19) /*!< OUT endpoint interrupt flag */
|
|
||||||
#define GINTF_IEPIF BIT(18) /*!< IN endpoint interrupt flag */
|
|
||||||
#define GINTF_EOPFIF BIT(15) /*!< end of periodic frame interrupt flag */
|
|
||||||
#define GINTF_ISOOPDIF BIT(14) /*!< isochronous OUT packet dropped interrupt flag */
|
|
||||||
#define GINTF_ENUMFIF BIT(13) /*!< enumeration finished */
|
|
||||||
#define GINTF_RST BIT(12) /*!< USB reset */
|
|
||||||
#define GINTF_SP BIT(11) /*!< USB suspend */
|
|
||||||
#define GINTF_ESP BIT(10) /*!< early suspend */
|
|
||||||
#define GINTF_GONAK BIT(7) /*!< global OUT NAK effective */
|
|
||||||
#define GINTF_GNPINAK BIT(6) /*!< global IN non-periodic NAK effective */
|
|
||||||
#define GINTF_NPTXFEIF BIT(5) /*!< non-periodic tx FIFO empty interrupt flag */
|
|
||||||
#define GINTF_RXFNEIF BIT(4) /*!< rx FIFO non-empty interrupt flag */
|
|
||||||
#define GINTF_SOF BIT(3) /*!< start of frame */
|
|
||||||
#define GINTF_OTGIF BIT(2) /*!< OTG interrupt flag */
|
|
||||||
#define GINTF_MFIF BIT(1) /*!< mode fault interrupt flag */
|
|
||||||
#define GINTF_COPM BIT(0) /*!< current operation mode */
|
|
||||||
|
|
||||||
/* global interrupt enable register bits definitions */
|
|
||||||
#define GINTEN_WKUPIE BIT(31) /*!< wakeup interrupt enable */
|
|
||||||
#define GINTEN_SESIE BIT(30) /*!< session interrupt enable */
|
|
||||||
#define GINTEN_DISCIE BIT(29) /*!< disconnect interrupt enable */
|
|
||||||
#define GINTEN_IDPSCIE BIT(28) /*!< id pin status change interrupt enable */
|
|
||||||
#define GINTEN_PTXFEIE BIT(26) /*!< periodic tx FIFO empty interrupt enable */
|
|
||||||
#define GINTEN_HCIE BIT(25) /*!< host channels interrupt enable */
|
|
||||||
#define GINTEN_HPIE BIT(24) /*!< host port interrupt enable */
|
|
||||||
#define GINTEN_IPXIE BIT(21) /*!< periodic transfer not complete interrupt enable */
|
|
||||||
#define GINTEN_ISOONCIE BIT(21) /*!< isochronous OUT transfer not complete interrupt enable */
|
|
||||||
#define GINTEN_ISOINCIE BIT(20) /*!< isochronous IN transfer not complete interrupt enable */
|
|
||||||
#define GINTEN_OEPIE BIT(19) /*!< OUT endpoints interrupt enable */
|
|
||||||
#define GINTEN_IEPIE BIT(18) /*!< IN endpoints interrupt enable */
|
|
||||||
#define GINTEN_EOPFIE BIT(15) /*!< end of periodic frame interrupt enable */
|
|
||||||
#define GINTEN_ISOOPDIE BIT(14) /*!< isochronous OUT packet dropped interrupt enable */
|
|
||||||
#define GINTEN_ENUMFIE BIT(13) /*!< enumeration finish enable */
|
|
||||||
#define GINTEN_RSTIE BIT(12) /*!< USB reset interrupt enable */
|
|
||||||
#define GINTEN_SPIE BIT(11) /*!< USB suspend interrupt enable */
|
|
||||||
#define GINTEN_ESPIE BIT(10) /*!< early suspend interrupt enable */
|
|
||||||
#define GINTEN_GONAKIE BIT(7) /*!< global OUT NAK effective interrupt enable */
|
|
||||||
#define GINTEN_GNPINAKIE BIT(6) /*!< global non-periodic IN NAK effective interrupt enable */
|
|
||||||
#define GINTEN_NPTXFEIE BIT(5) /*!< non-periodic Tx FIFO empty interrupt enable */
|
|
||||||
#define GINTEN_RXFNEIE BIT(4) /*!< receive FIFO non-empty interrupt enable */
|
|
||||||
#define GINTEN_SOFIE BIT(3) /*!< start of frame interrupt enable */
|
|
||||||
#define GINTEN_OTGIE BIT(2) /*!< OTG interrupt enable */
|
|
||||||
#define GINTEN_MFIE BIT(1) /*!< mode fault interrupt enable */
|
|
||||||
|
|
||||||
/* global receive status read and pop register bits definitions */
|
|
||||||
#define GRSTATRP_RPCKST BITS(17, 20) /*!< received packet status */
|
|
||||||
#define GRSTATRP_DPID BITS(15, 16) /*!< data PID */
|
|
||||||
#define GRSTATRP_BCOUNT BITS(4, 14) /*!< byte count */
|
|
||||||
#define GRSTATRP_CNUM BITS(0, 3) /*!< channel number */
|
|
||||||
#define GRSTATRP_EPNUM BITS(0, 3) /*!< endpoint number */
|
|
||||||
|
|
||||||
/* global receive FIFO length register bits definitions */
|
|
||||||
#define GRFLEN_RXFD BITS(0, 15) /*!< rx FIFO depth */
|
|
||||||
|
|
||||||
/* host non-periodic transmit FIFO length register bits definitions */
|
|
||||||
#define HNPTFLEN_HNPTXFD BITS(16, 31) /*!< non-periodic Tx FIFO depth */
|
|
||||||
#define HNPTFLEN_HNPTXRSAR BITS(0, 15) /*!< non-periodic Tx RAM start address */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief USB IN endpoint 0 transmit FIFO length register bits definitions
|
|
||||||
*/
|
|
||||||
#define DIEP0TFLEN_IEP0TXFD BITS(16, 31) /*!< IN Endpoint 0 Tx FIFO depth */
|
|
||||||
#define DIEP0TFLEN_IEP0TXRSAR BITS(0, 15) /*!< IN Endpoint 0 TX RAM start address */
|
|
||||||
|
|
||||||
/* host non-periodic transmit FIFO/queue status register bits definitions */
|
|
||||||
#define HNPTFQSTAT_NPTXRQTOP BITS(24, 30) /*!< top entry of the non-periodic Tx request queue */
|
|
||||||
#define HNPTFQSTAT_NPTXRQS BITS(16, 23) /*!< non-periodic Tx request queue space */
|
|
||||||
#define HNPTFQSTAT_NPTXFS BITS(0, 15) /*!< non-periodic Tx FIFO space */
|
|
||||||
#define HNPTFQSTAT_CNUM BITS(27, 30) /*!< channel number*/
|
|
||||||
#define HNPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */
|
|
||||||
#define HNPTFQSTAT_TYPE BITS(25, 26) /*!< token type */
|
|
||||||
#define HNPTFQSTAT_TMF BIT(24) /*!< terminate flag */
|
|
||||||
|
|
||||||
/* global core configuration register bits definitions */
|
|
||||||
#define GCCFG_VBUSIG BIT(21) /*!< vbus ignored */
|
|
||||||
#define GCCFG_SOFOEN BIT(20) /*!< SOF output enable */
|
|
||||||
#define GCCFG_VBUSBCEN BIT(19) /*!< the VBUS B-device comparer enable */
|
|
||||||
#define GCCFG_VBUSACEN BIT(18) /*!< the VBUS A-device comparer enable */
|
|
||||||
#define GCCFG_PWRON BIT(16) /*!< power on */
|
|
||||||
|
|
||||||
/* core ID register bits definitions */
|
|
||||||
#define CID_CID BITS(0, 31) /*!< core ID */
|
|
||||||
|
|
||||||
/* host periodic transmit FIFO length register bits definitions */
|
|
||||||
#define HPTFLEN_HPTXFD BITS(16, 31) /*!< host periodic Tx FIFO depth */
|
|
||||||
#define HPTFLEN_HPTXFSAR BITS(0, 15) /*!< host periodic Tx RAM start address */
|
|
||||||
|
|
||||||
/* device IN endpoint transmit FIFO length register bits definitions */
|
|
||||||
#define DIEPTFLEN_IEPTXFD BITS(16, 31) /*!< IN endpoint Tx FIFO x depth */
|
|
||||||
#define DIEPTFLEN_IEPTXRSAR BITS(0, 15) /*!< IN endpoint FIFOx Tx x RAM start address */
|
|
||||||
|
|
||||||
/* host control register bits definitions */
|
|
||||||
#define HCTL_SPDFSLS BIT(2) /*!< speed limited to FS and LS */
|
|
||||||
#define HCTL_CLKSEL BITS(0, 1) /*!< clock select for USB clock */
|
|
||||||
|
|
||||||
/* host frame interval register bits definitions */
|
|
||||||
#define HFT_FRI BITS(0, 15) /*!< frame interval */
|
|
||||||
|
|
||||||
/* host frame information remaining register bits definitions */
|
|
||||||
#define HFINFR_FRT BITS(16, 31) /*!< frame remaining time */
|
|
||||||
#define HFINFR_FRNUM BITS(0, 15) /*!< frame number */
|
|
||||||
|
|
||||||
/* host periodic transmit FIFO/queue status register bits definitions */
|
|
||||||
#define HPTFQSTAT_PTXREQT BITS(24, 31) /*!< top entry of the periodic Tx request queue */
|
|
||||||
#define HPTFQSTAT_PTXREQS BITS(16, 23) /*!< periodic Tx request queue space */
|
|
||||||
#define HPTFQSTAT_PTXFS BITS(0, 15) /*!< periodic Tx FIFO space */
|
|
||||||
#define HPTFQSTAT_OEFRM BIT(31) /*!< odd/eveb frame */
|
|
||||||
#define HPTFQSTAT_CNUM BITS(27, 30) /*!< channel number */
|
|
||||||
#define HPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */
|
|
||||||
#define HPTFQSTAT_TYPE BITS(25, 26) /*!< token type */
|
|
||||||
#define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */
|
|
||||||
|
|
||||||
|
|
||||||
#define TFQSTAT_TXFS BITS(0, 15)
|
|
||||||
#define TFQSTAT_CNUM BITS(27, 30)
|
|
||||||
|
|
||||||
/* host all channels interrupt register bits definitions */
|
|
||||||
#define HACHINT_HACHINT BITS(0, 11) /*!< host all channel interrupts */
|
|
||||||
|
|
||||||
/* host all channels interrupt enable register bits definitions */
|
|
||||||
#define HACHINTEN_CINTEN BITS(0, 11) /*!< channel interrupt enable */
|
|
||||||
|
|
||||||
/* host port control and status register bits definitions */
|
|
||||||
#define HPCS_PS BITS(17, 18) /*!< port speed */
|
|
||||||
#define HPCS_PP BIT(12) /*!< port power */
|
|
||||||
#define HPCS_PLST BITS(10, 11) /*!< port line status */
|
|
||||||
#define HPCS_PRST BIT(8) /*!< port reset */
|
|
||||||
#define HPCS_PSP BIT(7) /*!< port suspend */
|
|
||||||
#define HPCS_PREM BIT(6) /*!< port resume */
|
|
||||||
#define HPCS_PEDC BIT(3) /*!< port enable/disable change */
|
|
||||||
#define HPCS_PE BIT(2) /*!< port enable */
|
|
||||||
#define HPCS_PCD BIT(1) /*!< port connect detected */
|
|
||||||
#define HPCS_PCST BIT(0) /*!< port connect status */
|
|
||||||
|
|
||||||
/* host channel-x control register bits definitions */
|
|
||||||
#define HCHCTL_CEN BIT(31) /*!< channel enable */
|
|
||||||
#define HCHCTL_CDIS BIT(30) /*!< channel disable */
|
|
||||||
#define HCHCTL_ODDFRM BIT(29) /*!< odd frame */
|
|
||||||
#define HCHCTL_DAR BITS(22, 28) /*!< device address */
|
|
||||||
#define HCHCTL_MPC BITS(20, 21) /*!< multiple packet count */
|
|
||||||
#define HCHCTL_EPTYPE BITS(18, 19) /*!< endpoint type */
|
|
||||||
#define HCHCTL_LSD BIT(17) /*!< low-speed device */
|
|
||||||
#define HCHCTL_EPDIR BIT(15) /*!< endpoint direction */
|
|
||||||
#define HCHCTL_EPNUM BITS(11, 14) /*!< endpoint number */
|
|
||||||
#define HCHCTL_MPL BITS(0, 10) /*!< maximum packet length */
|
|
||||||
|
|
||||||
/* host channel-x split transaction register bits definitions */
|
|
||||||
#define HCHSTCTL_SPLEN BIT(31) /*!< enable high-speed split transaction */
|
|
||||||
#define HCHSTCTL_CSPLT BIT(16) /*!< complete-split enable */
|
|
||||||
#define HCHSTCTL_ISOPCE BITS(14, 15) /*!< isochronous OUT payload continuation encoding */
|
|
||||||
#define HCHSTCTL_HADDR BITS(7, 13) /*!< HUB address */
|
|
||||||
#define HCHSTCTL_PADDR BITS(0, 6) /*!< port address */
|
|
||||||
|
|
||||||
/* host channel-x interrupt flag register bits definitions */
|
|
||||||
#define HCHINTF_DTER BIT(10) /*!< data toggle error */
|
|
||||||
#define HCHINTF_REQOVR BIT(9) /*!< request queue overrun */
|
|
||||||
#define HCHINTF_BBER BIT(8) /*!< babble error */
|
|
||||||
#define HCHINTF_USBER BIT(7) /*!< USB bus Error */
|
|
||||||
#define HCHINTF_NYET BIT(6) /*!< NYET */
|
|
||||||
#define HCHINTF_ACK BIT(5) /*!< ACK */
|
|
||||||
#define HCHINTF_NAK BIT(4) /*!< NAK */
|
|
||||||
#define HCHINTF_STALL BIT(3) /*!< STALL */
|
|
||||||
#define HCHINTF_DMAER BIT(2) /*!< DMA error */
|
|
||||||
#define HCHINTF_CH BIT(1) /*!< channel halted */
|
|
||||||
#define HCHINTF_TF BIT(0) /*!< transfer finished */
|
|
||||||
|
|
||||||
/* host channel-x interrupt enable register bits definitions */
|
|
||||||
#define HCHINTEN_DTERIE BIT(10) /*!< data toggle error interrupt enable */
|
|
||||||
#define HCHINTEN_REQOVRIE BIT(9) /*!< request queue overrun interrupt enable */
|
|
||||||
#define HCHINTEN_BBERIE BIT(8) /*!< babble error interrupt enable */
|
|
||||||
#define HCHINTEN_USBERIE BIT(7) /*!< USB bus error interrupt enable */
|
|
||||||
#define HCHINTEN_NYETIE BIT(6) /*!< NYET interrupt enable */
|
|
||||||
#define HCHINTEN_ACKIE BIT(5) /*!< ACK interrupt enable */
|
|
||||||
#define HCHINTEN_NAKIE BIT(4) /*!< NAK interrupt enable */
|
|
||||||
#define HCHINTEN_STALLIE BIT(3) /*!< STALL interrupt enable */
|
|
||||||
#define HCHINTEN_DMAERIE BIT(2) /*!< DMA error interrupt enable */
|
|
||||||
#define HCHINTEN_CHIE BIT(1) /*!< channel halted interrupt enable */
|
|
||||||
#define HCHINTEN_TFIE BIT(0) /*!< transfer finished interrupt enable */
|
|
||||||
|
|
||||||
/* host channel-x transfer length register bits definitions */
|
|
||||||
#define HCHLEN_PING BIT(31) /*!< PING token request */
|
|
||||||
#define HCHLEN_DPID BITS(29, 30) /*!< data PID */
|
|
||||||
#define HCHLEN_PCNT BITS(19, 28) /*!< packet count */
|
|
||||||
#define HCHLEN_TLEN BITS(0, 18) /*!< transfer length */
|
|
||||||
|
|
||||||
/* host channel-x DMA address register bits definitions */
|
|
||||||
#define HCHDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */
|
|
||||||
|
|
||||||
|
|
||||||
#define PORT_SPEED(x) (((uint32_t)(x) << 17) & HPCS_PS) /*!< Port speed */
|
|
||||||
|
|
||||||
#define PORT_SPEED_HIGH PORT_SPEED(0) /*!< high speed */
|
|
||||||
#define PORT_SPEED_FULL PORT_SPEED(1) /*!< full speed */
|
|
||||||
#define PORT_SPEED_LOW PORT_SPEED(2) /*!< low speed */
|
|
||||||
|
|
||||||
#define PIPE_CTL_DAR(x) (((uint32_t)(x) << 22) & HCHCTL_DAR) /*!< device address */
|
|
||||||
#define PIPE_CTL_EPTYPE(x) (((uint32_t)(x) << 18) & HCHCTL_EPTYPE) /*!< endpoint type */
|
|
||||||
#define PIPE_CTL_EPNUM(x) (((uint32_t)(x) << 11) & HCHCTL_EPNUM) /*!< endpoint number */
|
|
||||||
#define PIPE_CTL_EPDIR(x) (((uint32_t)(x) << 15) & HCHCTL_EPDIR) /*!< endpoint direction */
|
|
||||||
#define PIPE_CTL_EPMPL(x) (((uint32_t)(x) << 0) & HCHCTL_MPL) /*!< maximum packet length */
|
|
||||||
#define PIPE_CTL_LSD(x) (((uint32_t)(x) << 17) & HCHCTL_LSD) /*!< low-Speed device */
|
|
||||||
|
|
||||||
#define PIPE_XFER_PCNT(x) (((uint32_t)(x) << 19) & HCHLEN_PCNT) /*!< packet count */
|
|
||||||
#define PIPE_XFER_DPID(x) (((uint32_t)(x) << 29) & HCHLEN_DPID) /*!< data PID */
|
|
||||||
|
|
||||||
#define PIPE_DPID_DATA0 PIPE_XFER_DPID(0) /*!< DATA0 */
|
|
||||||
#define PIPE_DPID_DATA1 PIPE_XFER_DPID(2) /*!< DATA1 */
|
|
||||||
#define PIPE_DPID_DATA2 PIPE_XFER_DPID(1) /*!< DATA2 */
|
|
||||||
#define PIPE_DPID_SETUP PIPE_XFER_DPID(3) /*!< MDATA (non-control)/SETUP (control) */
|
|
||||||
|
|
||||||
extern const uint32_t PIPE_DPID[];
|
|
||||||
|
|
||||||
/* device configuration registers bits definitions */
|
|
||||||
#define DCFG_EOPFT BITS(11, 12) /*!< end of periodic frame time */
|
|
||||||
#define DCFG_DAR BITS(4, 10) /*!< device address */
|
|
||||||
#define DCFG_NZLSOH BIT(2) /*!< non-zero-length status OUT handshake */
|
|
||||||
#define DCFG_DS BITS(0, 1) /*!< device speed */
|
|
||||||
|
|
||||||
/* device control registers bits definitions */
|
|
||||||
#define DCTL_POIF BIT(11) /*!< power-on initialization finished */
|
|
||||||
#define DCTL_CGONAK BIT(10) /*!< clear global OUT NAK */
|
|
||||||
#define DCTL_SGONAK BIT(9) /*!< set global OUT NAK */
|
|
||||||
#define DCTL_CGINAK BIT(8) /*!< clear global IN NAK */
|
|
||||||
#define DCTL_SGINAK BIT(7) /*!< set global IN NAK */
|
|
||||||
#define DCTL_GONS BIT(3) /*!< global OUT NAK status */
|
|
||||||
#define DCTL_GINS BIT(2) /*!< global IN NAK status */
|
|
||||||
#define DCTL_SD BIT(1) /*!< soft disconnect */
|
|
||||||
#define DCTL_RWKUP BIT(0) /*!< remote wakeup */
|
|
||||||
|
|
||||||
/* device status registers bits definitions */
|
|
||||||
#define DSTAT_FNRSOF BITS(8, 21) /*!< the frame number of the received SOF. */
|
|
||||||
#define DSTAT_ES BITS(1, 2) /*!< enumerated speed */
|
|
||||||
#define DSTAT_SPST BIT(0) /*!< suspend status */
|
|
||||||
|
|
||||||
/* device IN endpoint common interrupt enable registers bits definitions */
|
|
||||||
#define DIEPINTEN_NAKEN BIT(13) /*!< NAK handshake sent by USBHS interrupt enable bit */
|
|
||||||
#define DIEPINTEN_TXFEEN BIT(7) /*!< transmit FIFO empty interrupt enable bit */
|
|
||||||
#define DIEPINTEN_IEPNEEN BIT(6) /*!< IN endpoint NAK effective interrupt enable bit */
|
|
||||||
#define DIEPINTEN_EPTXFUDEN BIT(4) /*!< endpoint Tx FIFO underrun interrupt enable bit */
|
|
||||||
#define DIEPINTEN_CITOEN BIT(3) /*!< control In Timeout interrupt enable bit */
|
|
||||||
#define DIEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */
|
|
||||||
#define DIEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */
|
|
||||||
|
|
||||||
/* device OUT endpoint common interrupt enable registers bits definitions */
|
|
||||||
#define DOEPINTEN_NYETEN BIT(14) /*!< NYET handshake is sent interrupt enable bit */
|
|
||||||
#define DOEPINTEN_BTBSTPEN BIT(6) /*!< back-to-back SETUP packets interrupt enable bit */
|
|
||||||
#define DOEPINTEN_EPRXFOVREN BIT(4) /*!< endpoint Rx FIFO overrun interrupt enable bit */
|
|
||||||
#define DOEPINTEN_STPFEN BIT(3) /*!< SETUP phase finished interrupt enable bit */
|
|
||||||
#define DOEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */
|
|
||||||
#define DOEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */
|
|
||||||
|
|
||||||
/* device all endpoints interrupt registers bits definitions */
|
|
||||||
#define DAEPINT_OEPITB BITS(16, 21) /*!< device all OUT endpoint interrupt bits */
|
|
||||||
#define DAEPINT_IEPITB BITS(0, 5) /*!< device all IN endpoint interrupt bits */
|
|
||||||
|
|
||||||
/* device all endpoints interrupt enable registers bits definitions */
|
|
||||||
#define DAEPINTEN_OEPIE BITS(16, 21) /*!< OUT endpoint interrupt enable */
|
|
||||||
#define DAEPINTEN_IEPIE BITS(0, 3) /*!< IN endpoint interrupt enable */
|
|
||||||
|
|
||||||
/* device Vbus discharge time registers bits definitions */
|
|
||||||
#define DVBUSDT_DVBUSDT BITS(0, 15) /*!< device VBUS discharge time */
|
|
||||||
|
|
||||||
/* device Vbus pulsing time registers bits definitions */
|
|
||||||
#define DVBUSPT_DVBUSPT BITS(0, 11) /*!< device VBUS pulsing time */
|
|
||||||
|
|
||||||
/* device IN endpoint FIFO empty interrupt enable register bits definitions */
|
|
||||||
#define DIEPFEINTEN_IEPTXFEIE BITS(0, 5) /*!< IN endpoint Tx FIFO empty interrupt enable bits */
|
|
||||||
|
|
||||||
/* device endpoint 0 control register bits definitions */
|
|
||||||
#define DEP0CTL_EPEN BIT(31) /*!< endpoint enable */
|
|
||||||
#define DEP0CTL_EPD BIT(30) /*!< endpoint disable */
|
|
||||||
#define DEP0CTL_SNAK BIT(27) /*!< set NAK */
|
|
||||||
#define DEP0CTL_CNAK BIT(26) /*!< clear NAK */
|
|
||||||
#define DIEP0CTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */
|
|
||||||
#define DEP0CTL_STALL BIT(21) /*!< STALL handshake */
|
|
||||||
#define DOEP0CTL_SNOOP BIT(20) /*!< snoop mode */
|
|
||||||
#define DEP0CTL_EPTYPE BITS(18, 19) /*!< endpoint type */
|
|
||||||
#define DEP0CTL_NAKS BIT(17) /*!< NAK status */
|
|
||||||
#define DEP0CTL_EPACT BIT(15) /*!< endpoint active */
|
|
||||||
#define DEP0CTL_MPL BITS(0, 1) /*!< maximum packet length */
|
|
||||||
|
|
||||||
/* device endpoint x control register bits definitions */
|
|
||||||
#define DEPCTL_EPEN BIT(31) /*!< endpoint enable */
|
|
||||||
#define DEPCTL_EPD BIT(30) /*!< endpoint disable */
|
|
||||||
#define DEPCTL_SODDFRM BIT(29) /*!< set odd frame */
|
|
||||||
#define DEPCTL_SD1PID BIT(29) /*!< set DATA1 PID */
|
|
||||||
#define DEPCTL_SEVNFRM BIT(28) /*!< set even frame */
|
|
||||||
#define DEPCTL_SD0PID BIT(28) /*!< set DATA0 PID */
|
|
||||||
#define DEPCTL_SNAK BIT(27) /*!< set NAK */
|
|
||||||
#define DEPCTL_CNAK BIT(26) /*!< clear NAK */
|
|
||||||
#define DIEPCTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */
|
|
||||||
#define DEPCTL_STALL BIT(21) /*!< STALL handshake */
|
|
||||||
#define DOEPCTL_SNOOP BIT(20) /*!< snoop mode */
|
|
||||||
#define DEPCTL_EPTYPE BITS(18, 19) /*!< endpoint type */
|
|
||||||
#define DEPCTL_NAKS BIT(17) /*!< NAK status */
|
|
||||||
#define DEPCTL_EOFRM BIT(16) /*!< even/odd frame */
|
|
||||||
#define DEPCTL_DPID BIT(16) /*!< endpoint data PID */
|
|
||||||
#define DEPCTL_EPACT BIT(15) /*!< endpoint active */
|
|
||||||
#define DEPCTL_MPL BITS(0, 10) /*!< maximum packet length */
|
|
||||||
|
|
||||||
/* device IN endpoint-x interrupt flag register bits definitions */
|
|
||||||
#define DIEPINTF_NAK BIT(13) /*!< NAK handshake sent by USBHS */
|
|
||||||
#define DIEPINTF_TXFE BIT(7) /*!< transmit FIFO empty */
|
|
||||||
#define DIEPINTF_IEPNE BIT(6) /*!< IN endpoint NAK effective */
|
|
||||||
#define DIEPINTF_EPTXFUD BIT(4) /*!< endpoint Tx FIFO underrun */
|
|
||||||
#define DIEPINTF_CITO BIT(3) /*!< control In Timeout interrupt */
|
|
||||||
#define DIEPINTF_EPDIS BIT(1) /*!< endpoint disabled */
|
|
||||||
#define DIEPINTF_TF BIT(0) /*!< transfer finished */
|
|
||||||
|
|
||||||
/* device OUT endpoint-x interrupt flag register bits definitions */
|
|
||||||
#define DOEPINTF_NYET BIT(14) /*!< NYET handshake is sent */
|
|
||||||
#define DOEPINTF_BTBSTP BIT(6) /*!< back-to-back SETUP packets */
|
|
||||||
#define DOEPINTF_EPRXFOVR BIT(4) /*!< endpoint Rx FIFO overrun */
|
|
||||||
#define DOEPINTF_STPF BIT(3) /*!< SETUP phase finished */
|
|
||||||
#define DOEPINTF_EPDIS BIT(1) /*!< endpoint disabled */
|
|
||||||
#define DOEPINTF_TF BIT(0) /*!< transfer finished */
|
|
||||||
|
|
||||||
/* device IN endpoint 0 transfer length register bits definitions */
|
|
||||||
#define DIEP0LEN_PCNT BITS(19, 20) /*!< packet count */
|
|
||||||
#define DIEP0LEN_TLEN BITS(0, 6) /*!< transfer length */
|
|
||||||
|
|
||||||
/* device OUT endpoint 0 transfer length register bits definitions */
|
|
||||||
#define DOEP0LEN_STPCNT BITS(29, 30) /*!< SETUP packet count */
|
|
||||||
#define DOEP0LEN_PCNT BIT(19) /*!< packet count */
|
|
||||||
#define DOEP0LEN_TLEN BITS(0, 6) /*!< transfer length */
|
|
||||||
|
|
||||||
/* device OUT endpoint-x transfer length register bits definitions */
|
|
||||||
#define DOEPLEN_RXDPID BITS(29, 30) /*!< received data PID */
|
|
||||||
#define DOEPLEN_STPCNT BITS(29, 30) /*!< SETUP packet count */
|
|
||||||
#define DIEPLEN_MCNT BITS(29, 30) /*!< multi count */
|
|
||||||
#define DEPLEN_PCNT BITS(19, 28) /*!< packet count */
|
|
||||||
#define DEPLEN_TLEN BITS(0, 18) /*!< transfer length */
|
|
||||||
|
|
||||||
/* device IN endpoint-x DMA address register bits definitions */
|
|
||||||
#define DIEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */
|
|
||||||
|
|
||||||
/* device OUT endpoint-x DMA address register bits definitions */
|
|
||||||
#define DOEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */
|
|
||||||
|
|
||||||
/* device IN endpoint-x transmit FIFO status register bits definitions */
|
|
||||||
#define DIEPTFSTAT_IEPTFS BITS(0, 15) /*!< IN endpoint Tx FIFO space remaining */
|
|
||||||
|
|
||||||
/* USB power and clock registers bits definition */
|
|
||||||
#define PWRCLKCTL_SHCLK BIT(1) /*!< stop HCLK */
|
|
||||||
#define PWRCLKCTL_SUCLK BIT(0) /*!< stop the USB clock */
|
|
||||||
|
|
||||||
#define RSTAT_GOUT_NAK 1U /* global OUT NAK (triggers an interrupt) */
|
|
||||||
#define RSTAT_DATA_UPDT 2U /* OUT data packet received */
|
|
||||||
#define RSTAT_XFER_COMP 3U /* OUT transfer completed (triggers an interrupt) */
|
|
||||||
#define RSTAT_SETUP_COMP 4U /* SETUP transaction completed (triggers an interrupt) */
|
|
||||||
#define RSTAT_SETUP_UPDT 6U /* SETUP data packet received */
|
|
||||||
|
|
||||||
#define DSTAT_EM_HS_PHY_30MHZ_60MHZ 0U /* USB enumerate speed use high-speed PHY clock in 30MHz or 60MHz */
|
|
||||||
#define DSTAT_EM_FS_PHY_30MHZ_60MHZ 1U /* USB enumerate speed use full-speed PHY clock in 30MHz or 60MHz */
|
|
||||||
#define DSTAT_EM_LS_PHY_6MHZ 2U /* USB enumerate speed use low-speed PHY clock in 6MHz */
|
|
||||||
#define DSTAT_EM_FS_PHY_48MHZ 3U /* USB enumerate speed use full-speed PHY clock in 48MHz */
|
|
||||||
|
|
||||||
#define DPID_DATA0 0U /* device endpoint data PID is DATA0 */
|
|
||||||
#define DPID_DATA1 2U /* device endpoint data PID is DATA1 */
|
|
||||||
#define DPID_DATA2 1U /* device endpoint data PID is DATA2 */
|
|
||||||
#define DPID_MDATA 3U /* device endpoint data PID is MDATA */
|
|
||||||
|
|
||||||
#define GAHBCS_DMAINCR(regval) (GAHBCS_BURST & ((regval) << 1U)) /*!< AHB burst type used by DMA*/
|
|
||||||
|
|
||||||
#define DMA_INCR0 GAHBCS_DMAINCR(0U) /*!< single burst type used by DMA*/
|
|
||||||
#define DMA_INCR1 GAHBCS_DMAINCR(1U) /*!< 4-beat incrementing burst type used by DMA*/
|
|
||||||
#define DMA_INCR4 GAHBCS_DMAINCR(3U) /*!< 8-beat incrementing burst type used by DMA*/
|
|
||||||
#define DMA_INCR8 GAHBCS_DMAINCR(5U) /*!< 16-beat incrementing burst type used by DMA*/
|
|
||||||
#define DMA_INCR16 GAHBCS_DMAINCR(7U) /*!< 32-beat incrementing burst type used by DMA*/
|
|
||||||
|
|
||||||
#define DCFG_PFRI(regval) (DCFG_EOPFT & ((regval) << 11U)) /*!< end of periodic frame time configuration */
|
|
||||||
|
|
||||||
#define FRAME_INTERVAL_80 DCFG_PFRI(0U) /*!< 80% of the frame time */
|
|
||||||
#define FRAME_INTERVAL_85 DCFG_PFRI(1U) /*!< 85% of the frame time */
|
|
||||||
#define FRAME_INTERVAL_90 DCFG_PFRI(2U) /*!< 90% of the frame time */
|
|
||||||
#define FRAME_INTERVAL_95 DCFG_PFRI(3U) /*!< 95% of the frame time */
|
|
||||||
|
|
||||||
#define DCFG_DEVSPEED(regval) (DCFG_DS & ((regval) << 0U)) /*!< device speed configuration */
|
|
||||||
|
|
||||||
#define USB_SPEED_EXP_HIGH DCFG_DEVSPEED(0U) /*!< device external PHY high speed */
|
|
||||||
#define USB_SPEED_EXP_FULL DCFG_DEVSPEED(1U) /*!< device external PHY full speed */
|
|
||||||
#define USB_SPEED_INP_FULL DCFG_DEVSPEED(3U) /*!< device internal PHY full speed */
|
|
||||||
|
|
||||||
#define DEP0_MPL(regval) (DEP0CTL_MPL & ((regval) << 0U)) /*!< maximum packet length configuration */
|
|
||||||
|
|
||||||
#define EP0MPL_64 DEP0_MPL(0U) /*!< maximum packet length 64 bytes */
|
|
||||||
#define EP0MPL_32 DEP0_MPL(1U) /*!< maximum packet length 32 bytes */
|
|
||||||
#define EP0MPL_16 DEP0_MPL(2U) /*!< maximum packet length 16 bytes */
|
|
||||||
#define EP0MPL_8 DEP0_MPL(3U) /*!< maximum packet length 8 bytes */
|
|
||||||
|
|
||||||
#define DOEP0_TLEN(regval) (DOEP0LEN_TLEN & ((regval) << 0)) /*!< Transfer length */
|
|
||||||
#define DOEP0_PCNT(regval) (DOEP0LEN_PCNT & ((regval) << 19)) /*!< Packet count */
|
|
||||||
#define DOEP0_STPCNT(regval) (DOEP0LEN_STPCNT & ((regval) << 29)) /*!< SETUP packet count */
|
|
||||||
|
|
||||||
#define USB_ULPI_PHY 1 /*!< ULPI interface external PHY */
|
|
||||||
#define USB_EMBEDDED_PHY 2 /*!< Embedded PHY */
|
|
||||||
|
|
||||||
#define GRXSTS_PKTSTS_IN 2
|
|
||||||
#define GRXSTS_PKTSTS_IN_XFER_COMP 3
|
|
||||||
#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5
|
|
||||||
#define GRXSTS_PKTSTS_CH_HALTED 7
|
|
||||||
|
|
||||||
#define DEVICE_MODE 0 /*!< device mode */
|
|
||||||
#define HOST_MODE 1 /*!< host mode */
|
|
||||||
#define OTG_MODE 2 /*!< OTG mode */
|
|
||||||
|
|
||||||
#define HCTL_30_60MHZ 0 /*!< USB clock 30-60MHZ */
|
|
||||||
#define HCTL_48MHZ 1 /*!< USB clock 48MHZ */
|
|
||||||
#define HCTL_6MHZ 2 /*!< USB clock 6MHZ */
|
|
||||||
|
|
||||||
enum USB_SPEED {
|
|
||||||
USB_SPEED_UNKNOWN = 0, /*!< USB speed unknown */
|
|
||||||
USB_SPEED_LOW, /*!< USB speed low */
|
|
||||||
USB_SPEED_FULL, /*!< USB speed full */
|
|
||||||
USB_SPEED_HIGH /*!< USB speed high */
|
|
||||||
};
|
|
||||||
|
|
||||||
#define EP0_OUT ((uint8_t)0x00) /*!< endpoint out 0 */
|
|
||||||
#define EP0_IN ((uint8_t)0x80) /*!< endpoint in 0 */
|
|
||||||
#define EP1_OUT ((uint8_t)0x01) /*!< endpoint out 1 */
|
|
||||||
#define EP1_IN ((uint8_t)0x81) /*!< endpoint in 1 */
|
|
||||||
#define EP2_OUT ((uint8_t)0x02) /*!< endpoint out 2 */
|
|
||||||
#define EP2_IN ((uint8_t)0x82) /*!< endpoint in 2 */
|
|
||||||
#define EP3_OUT ((uint8_t)0x03) /*!< endpoint out 3 */
|
|
||||||
#define EP3_IN ((uint8_t)0x83) /*!< endpoint in 3 */
|
|
||||||
|
|
||||||
#endif /* __DRV_USB_REGS_H */
|
|
||||||
|
|
@ -1,52 +0,0 @@
|
||||||
/*!
|
|
||||||
\file drv_usbd_int.h
|
|
||||||
\brief USB device mode interrupt header file
|
|
||||||
|
|
||||||
\version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __DRV_USBD_INT_H
|
|
||||||
#define __DRV_USBD_INT_H
|
|
||||||
|
|
||||||
#include "drv_usb_core.h"
|
|
||||||
#include "drv_usb_dev.h"
|
|
||||||
|
|
||||||
/* USB device-mode interrupts global service routine handler */
|
|
||||||
void usbd_isr (usb_core_driver *udev);
|
|
||||||
|
|
||||||
#ifdef USB_HS_DEDICATED_EP1_ENABLED
|
|
||||||
|
|
||||||
uint32_t USBD_OTG_EP1IN_ISR_Handler (usb_core_driver *udev);
|
|
||||||
uint32_t USBD_OTG_EP1OUT_ISR_Handler (usb_core_driver *udev);
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* __DRV_USBD_INT_H */
|
|
||||||
|
|
||||||
|
|
@ -1,49 +0,0 @@
|
||||||
/*!
|
|
||||||
\file drv_usbh_int.h.h
|
|
||||||
\brief USB host mode interrupt management header file
|
|
||||||
|
|
||||||
\version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __DRV_USBH_INT_H
|
|
||||||
#define __DRV_USBH_INT_H
|
|
||||||
|
|
||||||
#include "drv_usb_host.h"
|
|
||||||
|
|
||||||
typedef struct _usbh_int_cb
|
|
||||||
{
|
|
||||||
uint8_t (*SOF) (usb_core_driver *pudev);
|
|
||||||
} usbh_int_cb;
|
|
||||||
|
|
||||||
extern usbh_int_cb *usbh_int_fop;
|
|
||||||
|
|
||||||
uint32_t usbh_isr (usb_core_driver *pudev);
|
|
||||||
|
|
||||||
#endif /* __DRV_USBH_INT_H */
|
|
||||||
|
|
@ -1,250 +0,0 @@
|
||||||
/*!
|
|
||||||
\file usb_ch9_std.h
|
|
||||||
\brief USB 2.0 standard defines
|
|
||||||
|
|
||||||
\version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __USB_CH9_STD_H
|
|
||||||
#define __USB_CH9_STD_H
|
|
||||||
|
|
||||||
#include "usb_conf.h"
|
|
||||||
|
|
||||||
#define USB_DEV_QUALIFIER_DESC_LEN 0x0AU /*!< USB device qualifier descriptor length */
|
|
||||||
#define USB_DEV_DESC_LEN 0x12U /*!< USB device descriptor length */
|
|
||||||
#define USB_CFG_DESC_LEN 0x09U /*!< USB configuration descriptor length */
|
|
||||||
#define USB_ITF_DESC_LEN 0x09U /*!< USB interface descriptor length */
|
|
||||||
#define USB_EP_DESC_LEN 0x07U /*!< USB endpoint descriptor length */
|
|
||||||
#define USB_OTG_DESC_LEN 0x03U /*!< USB device OTG descriptor length */
|
|
||||||
#define USB_ITF_ASSOCIATION_DESC_LEN 0x08U /*!< USB interface association descriptor length */
|
|
||||||
|
|
||||||
#define USB_SETUP_PACKET_LEN 0x08U /*!< USB setup packet length */
|
|
||||||
|
|
||||||
/* bit 7 of bmRequestType: data phase transfer direction */
|
|
||||||
#define USB_TRX_MASK 0x80U /*!< USB transfer direction mask */
|
|
||||||
#define USB_TRX_OUT 0x00U /*!< USB transfer OUT direction */
|
|
||||||
#define USB_TRX_IN 0x80U /*!< USB transfer IN direction */
|
|
||||||
|
|
||||||
/* bit 6..5 of bmRequestType: request type */
|
|
||||||
#define USB_REQTYPE_STRD 0x00U /*!< USB standard request */
|
|
||||||
#define USB_REQTYPE_CLASS 0x20U /*!< USB class request */
|
|
||||||
#define USB_REQTYPE_VENDOR 0x40U /*!< USB vendor request */
|
|
||||||
#define USB_REQTYPE_MASK 0x60U /*!< USB request mask */
|
|
||||||
|
|
||||||
#define USBD_BUS_POWERED 0x00U /*!< USB bus power supply */
|
|
||||||
#define USBD_SELF_POWERED 0x01U /*!< USB self power supply */
|
|
||||||
|
|
||||||
#define USB_STATUS_REMOTE_WAKEUP 2U /*!< USB is in remote wakeup status */
|
|
||||||
#define USB_STATUS_SELF_POWERED 1U /*!< USB is in self powered status */
|
|
||||||
|
|
||||||
/* bit 4..0 of bmRequestType: recipient type */
|
|
||||||
enum _usb_recp_type {
|
|
||||||
USB_RECPTYPE_DEV = 0x0U, /*!< USB device request type */
|
|
||||||
USB_RECPTYPE_ITF = 0x1U, /*!< USB interface request type */
|
|
||||||
USB_RECPTYPE_EP = 0x2U, /*!< USB endpoint request type */
|
|
||||||
USB_RECPTYPE_MASK = 0x3U /*!< USB request type mask */
|
|
||||||
};
|
|
||||||
|
|
||||||
/* bRequest value */
|
|
||||||
enum _usb_request {
|
|
||||||
USB_GET_STATUS = 0x0U, /*!< USB get status request */
|
|
||||||
USB_CLEAR_FEATURE = 0x1U, /*!< USB clear feature request */
|
|
||||||
USB_RESERVED2 = 0x2U,
|
|
||||||
USB_SET_FEATURE = 0x3U, /*!< USB set feature request */
|
|
||||||
USB_RESERVED4 = 0x4U,
|
|
||||||
USB_SET_ADDRESS = 0x5U, /*!< USB set address request */
|
|
||||||
USB_GET_DESCRIPTOR = 0x6U, /*!< USB get descriptor request */
|
|
||||||
USB_SET_DESCRIPTOR = 0x7U, /*!< USB set descriptor request */
|
|
||||||
USB_GET_CONFIGURATION = 0x8U, /*!< USB get configuration request */
|
|
||||||
USB_SET_CONFIGURATION = 0x9U, /*!< USB set configuration request */
|
|
||||||
USB_GET_INTERFACE = 0xAU, /*!< USB get interface request */
|
|
||||||
USB_SET_INTERFACE = 0xBU, /*!< USB set interface request */
|
|
||||||
USB_SYNCH_FRAME = 0xCU /*!< USB synchronize frame request */
|
|
||||||
};
|
|
||||||
|
|
||||||
/* descriptor types of USB specifications */
|
|
||||||
enum _usb_desctype {
|
|
||||||
USB_DESCTYPE_DEV = 0x1U, /*!< USB device descriptor type */
|
|
||||||
USB_DESCTYPE_CONFIG = 0x2U, /*!< USB configuration descriptor type */
|
|
||||||
USB_DESCTYPE_STR = 0x3U, /*!< USB string descriptor type */
|
|
||||||
USB_DESCTYPE_ITF = 0x4U, /*!< USB interface descriptor type */
|
|
||||||
USB_DESCTYPE_EP = 0x5U, /*!< USB endpoint descriptor type */
|
|
||||||
USB_DESCTYPE_DEV_QUALIFIER = 0x6U, /*!< USB device qualtfier descriptor type */
|
|
||||||
USB_DESCTYPE_OTHER_SPD_CONFIG = 0x7U, /*!< USB other speed configuration descriptor type */
|
|
||||||
USB_DESCTYPE_ITF_POWER = 0x8U, /*!< USB interface power descriptor type */
|
|
||||||
USB_DESCTYPE_ITF_ASSOCIATION = 0xBU, /*!< USB interface association descriptor type */
|
|
||||||
USB_DESCTYPE_BOS = 0xFU /*!< USB BOS descriptor type */
|
|
||||||
};
|
|
||||||
|
|
||||||
/* USB Endpoint Descriptor bmAttributes bit definitions */
|
|
||||||
/* bits 1..0 : transfer type */
|
|
||||||
enum _usbx_type {
|
|
||||||
USB_EP_ATTR_CTL = 0x0U, /*!< USB control transfer type */
|
|
||||||
USB_EP_ATTR_ISO = 0x1U, /*!< USB Isochronous transfer type */
|
|
||||||
USB_EP_ATTR_BULK = 0x2U, /*!< USB Bulk transfer type */
|
|
||||||
USB_EP_ATTR_INT = 0x3U /*!< USB Interrupt transfer type */
|
|
||||||
};
|
|
||||||
|
|
||||||
/* bits 3..2 : Sync type (only if ISOCHRONOUS) */
|
|
||||||
#define USB_EP_ATTR_NOSYNC 0x00 /* No Synchronization */
|
|
||||||
#define USB_EP_ATTR_ASYNC 0x04 /* Asynchronous */
|
|
||||||
#define USB_EP_ATTR_ADAPTIVE 0x08 /* Adaptive */
|
|
||||||
#define USB_EP_ATTR_SYNC 0x0C /* Synchronous */
|
|
||||||
#define USB_EP_ATTR_SYNCTYPE 0x0C /* Synchronous type */
|
|
||||||
|
|
||||||
/* bits 5..4 : usage type (only if ISOCHRONOUS) */
|
|
||||||
#define USB_EP_ATTR_DATA 0x00 /* Data endpoint */
|
|
||||||
#define USB_EP_ATTR_FEEDBACK 0x10 /* Feedback endpoint */
|
|
||||||
#define USB_EP_ATTR_IMPLICIT_FEEDBACK_DATA 0x20 /* Implicit feedback Data endpoint */
|
|
||||||
#define USB_EP_ATTR_USAGETYPE 0x30 /* Usage type */
|
|
||||||
|
|
||||||
#define FEATURE_SELECTOR_EP 0x00 /* USB endpoint feature selector */
|
|
||||||
#define FEATURE_SELECTOR_DEV 0x01 /* USB device feature selector */
|
|
||||||
|
|
||||||
#define BYTE_SWAP(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \
|
|
||||||
(uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U))
|
|
||||||
|
|
||||||
#define BYTE_LOW(x) ((uint8_t)((x) & 0x00FFU))
|
|
||||||
#define BYTE_HIGH(x) ((uint8_t)(((x) & 0xFF00U) >> 8U))
|
|
||||||
|
|
||||||
#define USB_MIN(a, b) (((a) < (b)) ? (a) : (b))
|
|
||||||
|
|
||||||
#define USB_DEFAULT_CONFIG 0U
|
|
||||||
|
|
||||||
/* USB classes */
|
|
||||||
#define USB_CLASS_HID 0x03U /*!< USB HID class */
|
|
||||||
#define USB_CLASS_MSC 0x08U /*!< USB MSC class */
|
|
||||||
|
|
||||||
/* use the following values when USB host need to get descriptor */
|
|
||||||
#define USBH_DESC(x) (((x)<< 8U) & 0xFF00U)
|
|
||||||
|
|
||||||
/* as per usb specs 9.2.6.4 :standard request with data request timeout: 5sec
|
|
||||||
standard request with no data stage timeout : 50ms */
|
|
||||||
#define DATA_STAGE_TIMEOUT 5000U /*!< USB data stage timeout*/
|
|
||||||
#define NODATA_STAGE_TIMEOUT 50U /*!< USB no data stage timeout*/
|
|
||||||
|
|
||||||
#pragma pack(1)
|
|
||||||
|
|
||||||
/* USB standard device request structure */
|
|
||||||
typedef struct _usb_req {
|
|
||||||
uint8_t bmRequestType; /*!< type of request */
|
|
||||||
uint8_t bRequest; /*!< request of setup packet */
|
|
||||||
uint16_t wValue; /*!< value of setup packet */
|
|
||||||
uint16_t wIndex; /*!< index of setup packet */
|
|
||||||
uint16_t wLength; /*!< length of setup packet */
|
|
||||||
} usb_req;
|
|
||||||
|
|
||||||
/* USB setup packet define */
|
|
||||||
typedef union _usb_setup {
|
|
||||||
uint8_t data[8];
|
|
||||||
|
|
||||||
usb_req req;
|
|
||||||
} usb_setup;
|
|
||||||
|
|
||||||
/* USB descriptor defines */
|
|
||||||
|
|
||||||
typedef struct _usb_desc_header {
|
|
||||||
uint8_t bLength; /*!< size of the descriptor */
|
|
||||||
uint8_t bDescriptorType; /*!< type of the descriptor */
|
|
||||||
} usb_desc_header;
|
|
||||||
|
|
||||||
typedef struct _usb_desc_dev {
|
|
||||||
usb_desc_header header; /*!< descriptor header, including type and size */
|
|
||||||
|
|
||||||
uint16_t bcdUSB; /*!< BCD of the supported USB specification */
|
|
||||||
uint8_t bDeviceClass; /*!< USB device class */
|
|
||||||
uint8_t bDeviceSubClass; /*!< USB device subclass */
|
|
||||||
uint8_t bDeviceProtocol; /*!< USB device protocol */
|
|
||||||
uint8_t bMaxPacketSize0; /*!< size of the control (address 0) endpoint's bank in bytes */
|
|
||||||
uint16_t idVendor; /*!< vendor ID for the USB product */
|
|
||||||
uint16_t idProduct; /*!< unique product ID for the USB product */
|
|
||||||
uint16_t bcdDevice; /*!< product release (version) number */
|
|
||||||
uint8_t iManufacturer; /*!< string index for the manufacturer's name */
|
|
||||||
uint8_t iProduct; /*!< string index for the product name/details */
|
|
||||||
uint8_t iSerialNumber; /*!< string index for the product's globally unique hexadecimal serial number */
|
|
||||||
uint8_t bNumberConfigurations; /*!< total number of configurations supported by the device */
|
|
||||||
} usb_desc_dev;
|
|
||||||
|
|
||||||
typedef struct _usb_desc_config {
|
|
||||||
usb_desc_header header; /*!< descriptor header, including type and size */
|
|
||||||
|
|
||||||
uint16_t wTotalLength; /*!< size of the configuration descriptor header,and all sub descriptors inside the configuration */
|
|
||||||
uint8_t bNumInterfaces; /*!< total number of interfaces in the configuration */
|
|
||||||
uint8_t bConfigurationValue; /*!< configuration index of the current configuration */
|
|
||||||
uint8_t iConfiguration; /*!< index of a string descriptor describing the configuration */
|
|
||||||
uint8_t bmAttributes; /*!< configuration attributes */
|
|
||||||
uint8_t bMaxPower; /*!< maximum power consumption of the device while in the current configuration */
|
|
||||||
} usb_desc_config;
|
|
||||||
|
|
||||||
typedef struct _usb_desc_itf {
|
|
||||||
usb_desc_header header; /*!< descriptor header, including type and size */
|
|
||||||
|
|
||||||
uint8_t bInterfaceNumber; /*!< index of the interface in the current configuration */
|
|
||||||
uint8_t bAlternateSetting; /*!< alternate setting for the interface number */
|
|
||||||
uint8_t bNumEndpoints; /*!< total number of endpoints in the interface */
|
|
||||||
uint8_t bInterfaceClass; /*!< interface class ID */
|
|
||||||
uint8_t bInterfaceSubClass; /*!< interface subclass ID */
|
|
||||||
uint8_t bInterfaceProtocol; /*!< interface protocol ID */
|
|
||||||
uint8_t iInterface; /*!< index of the string descriptor describing the interface */
|
|
||||||
} usb_desc_itf;
|
|
||||||
|
|
||||||
typedef struct _usb_desc_itf_association {
|
|
||||||
usb_desc_header header; /*!< descriptor header, including type and size */
|
|
||||||
|
|
||||||
uint8_t bFirstInterface; /*!< Interface number of the first interface that is associated with this function */
|
|
||||||
uint8_t bInterfaceCount; /*!< Number of contiguous interfaces that are associated with this function */
|
|
||||||
uint8_t bFunctoinClass; /*!< Class code */
|
|
||||||
uint8_t bFunctionSubClass; /*!< Subclass code */
|
|
||||||
uint8_t bFunctionProtocol; /*!< Protocol */
|
|
||||||
uint8_t iFunction; /*!< Index of string descriptor describing this function */
|
|
||||||
} usb_desc_itf_association;
|
|
||||||
|
|
||||||
typedef struct _usb_desc_ep {
|
|
||||||
usb_desc_header header; /*!< descriptor header, including type and size. */
|
|
||||||
|
|
||||||
uint8_t bEndpointAddress; /*!< logical address of the endpoint */
|
|
||||||
uint8_t bmAttributes; /*!< endpoint attributes */
|
|
||||||
uint16_t wMaxPacketSize; /*!< size of the endpoint bank, in bytes */
|
|
||||||
|
|
||||||
uint8_t bInterval; /*!< polling interval in milliseconds for the endpoint if it is an INTERRUPT or ISOCHRONOUS type */
|
|
||||||
#ifdef AUDIO_ENDPOINT
|
|
||||||
uint8_t bRefresh; /*!< reset to 0 */
|
|
||||||
uint8_t bSynchAddress; /*!< reset to 0 */
|
|
||||||
#endif
|
|
||||||
} usb_desc_ep;
|
|
||||||
|
|
||||||
typedef struct _usb_desc_LANGID {
|
|
||||||
usb_desc_header header; /*!< descriptor header, including type and size. */
|
|
||||||
uint16_t wLANGID; /*!< LANGID code */
|
|
||||||
} usb_desc_LANGID;
|
|
||||||
|
|
||||||
#pragma pack()
|
|
||||||
|
|
||||||
#endif /* __USB_CH9_STD_H */
|
|
||||||
|
|
@ -1,101 +0,0 @@
|
||||||
#ifndef __USB_CONF_H
|
|
||||||
#define __USB_CONF_H
|
|
||||||
|
|
||||||
#include <stddef.h>
|
|
||||||
#include "gd32vf103.h"
|
|
||||||
|
|
||||||
//#ifndef USE_USB_FS
|
|
||||||
//#define USE_USB_HS
|
|
||||||
//#endif
|
|
||||||
|
|
||||||
#define USE_USB_FS
|
|
||||||
|
|
||||||
#ifdef USE_USB_FS
|
|
||||||
#define USB_FS_CORE
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef USE_USB_HS
|
|
||||||
#define USB_HS_CORE
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef USB_FS_CORE
|
|
||||||
#define RX_FIFO_FS_SIZE 128
|
|
||||||
#define TX0_FIFO_FS_SIZE 64
|
|
||||||
#define TX1_FIFO_FS_SIZE 128
|
|
||||||
#define TX2_FIFO_FS_SIZE 0
|
|
||||||
#define TX3_FIFO_FS_SIZE 0
|
|
||||||
#define USB_RX_FIFO_FS_SIZE 128
|
|
||||||
#define USB_HTX_NPFIFO_FS_SIZE 96
|
|
||||||
#define USB_HTX_PFIFO_FS_SIZE 96
|
|
||||||
#endif /* USB_FS_CORE */
|
|
||||||
|
|
||||||
#ifdef USB_HS_CORE
|
|
||||||
#define RX_FIFO_HS_SIZE 512
|
|
||||||
#define TX0_FIFO_HS_SIZE 128
|
|
||||||
#define TX1_FIFO_HS_SIZE 372
|
|
||||||
#define TX2_FIFO_HS_SIZE 0
|
|
||||||
#define TX3_FIFO_HS_SIZE 0
|
|
||||||
#define TX4_FIFO_HS_SIZE 0
|
|
||||||
#define TX5_FIFO_HS_SIZE 0
|
|
||||||
|
|
||||||
#ifdef USE_ULPI_PHY
|
|
||||||
#define USB_OTG_ULPI_PHY_ENABLED
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef USE_EMBEDDED_PHY
|
|
||||||
#define USB_OTG_EMBEDDED_PHY_ENABLED
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define USB_OTG_HS_INTERNAL_DMA_ENABLED
|
|
||||||
#define USB_OTG_HS_DEDICATED_EP1_ENABLED
|
|
||||||
#endif /* USB_HS_CORE */
|
|
||||||
|
|
||||||
#ifndef USB_SOF_OUTPUT
|
|
||||||
#define USB_SOF_OUTPUT 0
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifndef USB_LOW_POWER
|
|
||||||
#define USB_LOW_POWER 0
|
|
||||||
#endif
|
|
||||||
|
|
||||||
//#define USE_HOST_MODE
|
|
||||||
//#define USE_DEVICE_MODE
|
|
||||||
//#define USE_OTG_MODE
|
|
||||||
|
|
||||||
#ifndef USE_HOST_MODE
|
|
||||||
#define USE_DEVICE_MODE
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifndef USB_FS_CORE
|
|
||||||
#ifndef USB_HS_CORE
|
|
||||||
#error "USB_HS_CORE or USB_FS_CORE should be defined"
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifndef USE_DEVICE_MODE
|
|
||||||
#ifndef USE_HOST_MODE
|
|
||||||
#error "USE_DEVICE_MODE or USE_HOST_MODE should be defined"
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifndef USE_USB_HS
|
|
||||||
#ifndef USE_USB_FS
|
|
||||||
#error "USE_USB_HS or USE_USB_FS should be defined"
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************** C Compilers dependent keywords ****************************/
|
|
||||||
/* In HS mode and when the DMA is used, all variables and data structures dealing
|
|
||||||
with the DMA during the transaction process should be 4-bytes aligned */
|
|
||||||
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
|
|
||||||
#if defined (__GNUC__) /* GNU Compiler */
|
|
||||||
#define __ALIGN_END __attribute__ ((aligned(4)))
|
|
||||||
#define __ALIGN_BEGIN
|
|
||||||
#endif /* __GNUC__ */
|
|
||||||
#else
|
|
||||||
#define __ALIGN_BEGIN
|
|
||||||
#define __ALIGN_END
|
|
||||||
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
|
|
||||||
|
|
||||||
#endif /* __USB_CONF_H */
|
|
||||||
|
|
||||||
|
|
@ -1,10 +0,0 @@
|
||||||
#ifndef __USBD_CONF_H
|
|
||||||
#define __USBD_CONF_H
|
|
||||||
|
|
||||||
#include "usb_conf.h"
|
|
||||||
|
|
||||||
#define USBD_CFG_MAX_NUM 1
|
|
||||||
#define USBD_ITF_MAX_NUM 1
|
|
||||||
|
|
||||||
#endif /* __USBD_CONF_H */
|
|
||||||
|
|
||||||
|
|
@ -1,95 +0,0 @@
|
||||||
/*!
|
|
||||||
\file usbd_core.h
|
|
||||||
\brief USB device mode core functions protype
|
|
||||||
|
|
||||||
\version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __USBD_CORE_H
|
|
||||||
#define __USBD_CORE_H
|
|
||||||
|
|
||||||
|
|
||||||
#include "drv_usb_core.h"
|
|
||||||
#include "drv_usb_dev.h"
|
|
||||||
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
USBD_OK = 0, /*!< status OK */
|
|
||||||
USBD_BUSY, /*!< status busy */
|
|
||||||
USBD_FAIL, /*!< status fail */
|
|
||||||
} usbd_status;
|
|
||||||
|
|
||||||
enum _usbd_status {
|
|
||||||
USBD_DEFAULT = 1, /*!< default status */
|
|
||||||
USBD_ADDRESSED = 2, /*!< address send status */
|
|
||||||
USBD_CONFIGURED = 3, /*!< configured status */
|
|
||||||
USBD_SUSPENDED = 4 /*!< suspended status */
|
|
||||||
};
|
|
||||||
|
|
||||||
/* function declarations */
|
|
||||||
|
|
||||||
/* device connect */
|
|
||||||
void usbd_connect (usb_core_driver *udev);
|
|
||||||
|
|
||||||
/* device disconnect */
|
|
||||||
void usbd_disconnect (usb_core_driver *udev);
|
|
||||||
|
|
||||||
/* set USB device address */
|
|
||||||
void usbd_addr_set (usb_core_driver *udev, uint8_t addr);
|
|
||||||
|
|
||||||
/* initailizes the USB device-mode stack and load the class driver */
|
|
||||||
void usbd_init (usb_core_driver *udev, usb_core_enum core, usb_class_core *class_core);
|
|
||||||
|
|
||||||
/* endpoint initialization */
|
|
||||||
uint32_t usbd_ep_setup (usb_core_driver *udev, const usb_desc_ep *ep_desc);
|
|
||||||
|
|
||||||
/* configure the endpoint when it is disabled */
|
|
||||||
uint32_t usbd_ep_clear (usb_core_driver *udev, uint8_t ep_addr);
|
|
||||||
|
|
||||||
/* endpoint prepare to receive data */
|
|
||||||
uint32_t usbd_ep_recev (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint16_t len);
|
|
||||||
|
|
||||||
/* endpoint prepare to transmit data */
|
|
||||||
uint32_t usbd_ep_send (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint16_t len);
|
|
||||||
|
|
||||||
/* set an endpoint to STALL status */
|
|
||||||
uint32_t usbd_ep_stall (usb_core_driver *udev, uint8_t ep_addr);
|
|
||||||
|
|
||||||
/* clear endpoint STALLed status */
|
|
||||||
uint32_t usbd_ep_stall_clear (usb_core_driver *udev, uint8_t ep_addr);
|
|
||||||
|
|
||||||
/* flush the endpoint FIFOs */
|
|
||||||
uint32_t usbd_fifo_flush (usb_core_driver *udev, uint8_t ep_addr);
|
|
||||||
|
|
||||||
/* get the received data length */
|
|
||||||
uint16_t usbd_rxcount_get (usb_core_driver *udev, uint8_t ep_num);
|
|
||||||
|
|
||||||
#endif /* __USBD_CORE_H */
|
|
||||||
|
|
||||||
|
|
@ -1,114 +0,0 @@
|
||||||
/*!
|
|
||||||
\file usbd_enum.h
|
|
||||||
\brief USB enumeration definitions
|
|
||||||
|
|
||||||
\version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __USBD_ENUM_H
|
|
||||||
#define __USBD_ENUM_H
|
|
||||||
|
|
||||||
#include "usbd_core.h"
|
|
||||||
#include "usbd_conf.h"
|
|
||||||
#include <wchar.h>
|
|
||||||
|
|
||||||
#ifndef NULL
|
|
||||||
#define NULL 0U
|
|
||||||
#endif
|
|
||||||
|
|
||||||
typedef enum _usb_reqsta {
|
|
||||||
REQ_SUPP = 0x0U, /* request support */
|
|
||||||
REQ_NOTSUPP = 0x1U /* request not support */
|
|
||||||
} usb_reqsta;
|
|
||||||
|
|
||||||
/* string descriptor index */
|
|
||||||
enum _str_index
|
|
||||||
{
|
|
||||||
STR_IDX_LANGID = 0x0U, /* language ID string index */
|
|
||||||
STR_IDX_MFC = 0x1U, /* manufacturer string index */
|
|
||||||
STR_IDX_PRODUCT = 0x2U, /* product string index */
|
|
||||||
STR_IDX_SERIAL = 0x3U, /* serial string index */
|
|
||||||
STR_IDX_CONFIG = 0x4U, /* configuration string index */
|
|
||||||
STR_IDX_ITF = 0x5U, /* interface string index */
|
|
||||||
STR_IDX_MAX = 0x6U /* string maximum index */
|
|
||||||
};
|
|
||||||
|
|
||||||
typedef enum _usb_pwrsta {
|
|
||||||
USB_PWRSTA_SELF_POWERED = 0x1U, /* USB is in self powered status */
|
|
||||||
USB_PWRSTA_REMOTE_WAKEUP = 0x2U, /* USB is in remote wakeup status */
|
|
||||||
} usb_pwrsta;
|
|
||||||
|
|
||||||
typedef enum _usb_feature
|
|
||||||
{
|
|
||||||
USB_FEATURE_EP_HALT = 0x0U, /* USB has endpoint halt feature */
|
|
||||||
USB_FEATURE_REMOTE_WAKEUP = 0x1U, /* USB has endpoint remote wakeup feature */
|
|
||||||
USB_FEATURE_TEST_MODE = 0x2U /* USB has endpoint test mode feature */
|
|
||||||
} usb_feature;
|
|
||||||
|
|
||||||
#define ENG_LANGID 0x0409U /* english language ID */
|
|
||||||
#define CHN_LANGID 0x0804U /* chinese language ID */
|
|
||||||
|
|
||||||
/* USB device exported macros */
|
|
||||||
#define CTL_EP(ep) (((ep) == 0x00U) || ((ep) == 0x80U))
|
|
||||||
|
|
||||||
#define WIDE_STRING(string) _WIDE_STRING(string)
|
|
||||||
#define _WIDE_STRING(string) L##string
|
|
||||||
|
|
||||||
#define USBD_STRING_DESC(string) \
|
|
||||||
(void *)&(const struct { \
|
|
||||||
uint8_t _len; \
|
|
||||||
uint8_t _type; \
|
|
||||||
wchar_t _data[sizeof(string)]; \
|
|
||||||
}) { \
|
|
||||||
sizeof(WIDE_STRING(string)) + 2U - 2U, \
|
|
||||||
USB_DESCTYPE_STR, \
|
|
||||||
WIDE_STRING(string) \
|
|
||||||
}
|
|
||||||
|
|
||||||
/* function declarations */
|
|
||||||
|
|
||||||
/* handle USB standard device request */
|
|
||||||
usb_reqsta usbd_standard_request (usb_core_driver *udev, usb_req *req);
|
|
||||||
|
|
||||||
/* handle USB device class request */
|
|
||||||
usb_reqsta usbd_class_request (usb_core_driver *udev, usb_req *req);
|
|
||||||
|
|
||||||
/* handle USB vendor request */
|
|
||||||
usb_reqsta usbd_vendor_request (usb_core_driver *udev, usb_req *req);
|
|
||||||
|
|
||||||
/* handle USB enumeration error */
|
|
||||||
void usbd_enum_error (usb_core_driver *udev, usb_req *req);
|
|
||||||
|
|
||||||
/* convert hex 32bits value into unicode char */
|
|
||||||
void int_to_unicode (uint32_t value, uint8_t *pbuf, uint8_t len);
|
|
||||||
|
|
||||||
#endif /* __USBD_ENUM_H */
|
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -1,64 +0,0 @@
|
||||||
/*!
|
|
||||||
\file usbd_transc.h
|
|
||||||
\brief USB transaction core functions prototype
|
|
||||||
|
|
||||||
\version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __USBD_TRANSC_H
|
|
||||||
#define __USBD_TRANSC_H
|
|
||||||
|
|
||||||
#include "usbd_core.h"
|
|
||||||
|
|
||||||
/* function declarations */
|
|
||||||
|
|
||||||
/* USB send data in the control transaction */
|
|
||||||
usbd_status usbd_ctl_send (usb_core_driver *udev);
|
|
||||||
|
|
||||||
/* USB receive data in control transaction */
|
|
||||||
usbd_status usbd_ctl_recev (usb_core_driver *udev);
|
|
||||||
|
|
||||||
/* USB send control transaction status */
|
|
||||||
usbd_status usbd_ctl_status_send (usb_core_driver *udev);
|
|
||||||
|
|
||||||
/* USB control receive status */
|
|
||||||
usbd_status usbd_ctl_status_recev (usb_core_driver *udev);
|
|
||||||
|
|
||||||
/* USB setup stage processing */
|
|
||||||
uint8_t usbd_setup_transc (usb_core_driver *udev);
|
|
||||||
|
|
||||||
/* data out stage processing */
|
|
||||||
uint8_t usbd_out_transc (usb_core_driver *udev, uint8_t ep_num)__attribute__((optimize("O0")));
|
|
||||||
|
|
||||||
/* data in stage processing */
|
|
||||||
uint8_t usbd_in_transc (usb_core_driver *udev, uint8_t ep_num)__attribute__((optimize("O0")));
|
|
||||||
|
|
||||||
#endif /* __USBD_TRANSC_H */
|
|
||||||
|
|
||||||
|
|
@ -1,9 +0,0 @@
|
||||||
#ifndef __USBH_CONF_H
|
|
||||||
#define __USBH_CONF_H
|
|
||||||
|
|
||||||
#define USBH_MAX_EP_NUM 2
|
|
||||||
#define USBH_MAX_INTERFACES_NUM 2
|
|
||||||
#define USBH_MSC_MPS_SIZE 0x200
|
|
||||||
|
|
||||||
#endif /* __USBH_CONF_H */
|
|
||||||
|
|
||||||
|
|
@ -1,219 +0,0 @@
|
||||||
/*!
|
|
||||||
\file usbh_core.h
|
|
||||||
\brief USB host core state machine header file
|
|
||||||
|
|
||||||
\version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __USBH_CORE_H
|
|
||||||
#define __USBH_CORE_H
|
|
||||||
|
|
||||||
#include "usbh_conf.h"
|
|
||||||
#include "drv_usb_host.h"
|
|
||||||
|
|
||||||
#define MSC_CLASS 0x08U
|
|
||||||
#define HID_CLASS 0x03U
|
|
||||||
#define MSC_PROTOCOL 0x50U
|
|
||||||
#define CBI_PROTOCOL 0x01U
|
|
||||||
|
|
||||||
#define USBH_MAX_ERROR_COUNT 3U
|
|
||||||
|
|
||||||
#define USBH_DEV_ADDR_DEFAULT 0U
|
|
||||||
#define USBH_DEV_ADDR 1U
|
|
||||||
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
USBH_OK = 0U,
|
|
||||||
USBH_BUSY,
|
|
||||||
USBH_FAIL,
|
|
||||||
USBH_NOT_SUPPORTED,
|
|
||||||
USBH_UNRECOVERED_ERROR,
|
|
||||||
USBH_SPEED_UNKNOWN_ERROR,
|
|
||||||
USBH_APPLY_DEINIT
|
|
||||||
} usbh_status;
|
|
||||||
|
|
||||||
/* USB host global operation state */
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HOST_DEFAULT = 0U,
|
|
||||||
HOST_DETECT_DEV_SPEED,
|
|
||||||
HOST_DEV_ATTACHED,
|
|
||||||
HOST_DEV_DETACHED,
|
|
||||||
HOST_ENUM,
|
|
||||||
HOST_CLASS_ENUM,
|
|
||||||
HOST_CLASS_HANDLER,
|
|
||||||
HOST_USER_INPUT,
|
|
||||||
HOST_SUSPENDED,
|
|
||||||
HOST_ERROR
|
|
||||||
} usb_host_state;
|
|
||||||
|
|
||||||
/* USB host enumeration state */
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
ENUM_DEFAULT = 0U,
|
|
||||||
ENUM_GET_DEV_DESC,
|
|
||||||
ENUM_SET_ADDR,
|
|
||||||
ENUM_GET_CFG_DESC,
|
|
||||||
ENUM_GET_CFG_DESC_SET,
|
|
||||||
ENUM_GET_STR_DESC,
|
|
||||||
ENUM_SET_CONFIGURATION,
|
|
||||||
ENUM_DEV_CONFIGURED
|
|
||||||
} usbh_enum_state;
|
|
||||||
|
|
||||||
/* USB host control transfer state */
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
CTL_IDLE = 0U,
|
|
||||||
CTL_SETUP,
|
|
||||||
CTL_DATA_IN,
|
|
||||||
CTL_DATA_OUT,
|
|
||||||
CTL_STATUS_IN,
|
|
||||||
CTL_STATUS_OUT,
|
|
||||||
CTL_ERROR,
|
|
||||||
CTL_FINISH
|
|
||||||
} usbh_ctl_state;
|
|
||||||
|
|
||||||
/* user action state */
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
USBH_USER_NO_RESP = 0U,
|
|
||||||
USBH_USER_RESP_OK = 1U,
|
|
||||||
} usbh_user_status;
|
|
||||||
|
|
||||||
/* control transfer information */
|
|
||||||
typedef struct _usbh_control
|
|
||||||
{
|
|
||||||
uint8_t pipe_in_num;
|
|
||||||
uint8_t pipe_out_num;
|
|
||||||
uint8_t max_len;
|
|
||||||
uint8_t error_count;
|
|
||||||
|
|
||||||
uint8_t *buf;
|
|
||||||
uint16_t ctl_len;
|
|
||||||
uint16_t timer;
|
|
||||||
|
|
||||||
usb_setup setup;
|
|
||||||
usbh_ctl_state ctl_state;
|
|
||||||
} usbh_control;
|
|
||||||
|
|
||||||
/* USB device property */
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint8_t addr;
|
|
||||||
uint32_t speed;
|
|
||||||
|
|
||||||
usb_desc_dev dev_desc;
|
|
||||||
usb_desc_config cfg_desc;
|
|
||||||
usb_desc_itf itf_desc[USBH_MAX_INTERFACES_NUM];
|
|
||||||
usb_desc_ep ep_desc[USBH_MAX_INTERFACES_NUM][USBH_MAX_EP_NUM];
|
|
||||||
} usb_dev_prop;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Device class callbacks
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
usbh_status (*class_init) (usb_core_driver *pudev, void *phost);
|
|
||||||
void (*class_deinit) (usb_core_driver *pudev, void *phost);
|
|
||||||
usbh_status (*class_requests) (usb_core_driver *pudev, void *phost);
|
|
||||||
usbh_status (*class_machine) (usb_core_driver *pudev, void *phost);
|
|
||||||
} usbh_class_cb;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief User callbacks
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
void (*dev_init) (void);
|
|
||||||
void (*dev_deinit) (void);
|
|
||||||
void (*dev_attach) (void);
|
|
||||||
void (*dev_reset) (void);
|
|
||||||
void (*dev_detach) (void);
|
|
||||||
void (*dev_over_currented) (void);
|
|
||||||
void (*dev_speed_detected) (uint32_t dev_speed);
|
|
||||||
void (*dev_devdesc_assigned) (void *dev_desc);
|
|
||||||
void (*dev_address_set) (void);
|
|
||||||
|
|
||||||
void (*dev_cfgdesc_assigned) (usb_desc_config *cfg_desc,
|
|
||||||
usb_desc_itf *itf_desc,
|
|
||||||
usb_desc_ep *ep_desc);
|
|
||||||
|
|
||||||
void (*dev_mfc_str) (void *mfc_str);
|
|
||||||
void (*dev_prod_str) (void *prod_str);
|
|
||||||
void (*dev_seral_str) (void *serial_str);
|
|
||||||
void (*dev_enumerated) (void);
|
|
||||||
usbh_user_status (*dev_user_input) (void);
|
|
||||||
int (*dev_user_app) (void);
|
|
||||||
void (*dev_not_supported) (void);
|
|
||||||
void (*dev_error) (void);
|
|
||||||
} usbh_user_cb;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Host information
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
usb_host_state cur_state; /*!< host state machine value */
|
|
||||||
usb_host_state backup_state; /*!< backup of previous state machine value */
|
|
||||||
usbh_enum_state enum_state; /*!< enumeration state machine */
|
|
||||||
usbh_control control; /*!< USB host control state machine */
|
|
||||||
usb_dev_prop dev_prop; /*!< USB device properity */
|
|
||||||
|
|
||||||
usbh_class_cb *class_cb; /*!< USB class callback */
|
|
||||||
usbh_user_cb *usr_cb; /*!< USB user callback */
|
|
||||||
} usbh_host;
|
|
||||||
|
|
||||||
|
|
||||||
/* USB host stack initializations */
|
|
||||||
void usbh_init (usb_core_driver *pudev, usb_core_enum core, usbh_host *puhost);
|
|
||||||
|
|
||||||
/* de-initialize USB host */
|
|
||||||
usbh_status usbh_deinit (usb_core_driver *pudev, usbh_host *puhost);
|
|
||||||
|
|
||||||
/* USB host core main state machine process */
|
|
||||||
void usbh_core_task (usb_core_driver *pudev, usbh_host *puhost);
|
|
||||||
|
|
||||||
/* handle the error on USB host side */
|
|
||||||
void usbh_error_handler (usbh_host *puhost, usbh_status ErrType);
|
|
||||||
|
|
||||||
/* get USB URB state */
|
|
||||||
static inline usb_urb_state usbh_urbstate_get (usb_core_driver *pudev, uint8_t pp_num)
|
|
||||||
{
|
|
||||||
return pudev->host.pipe[pp_num].urb_state;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* get USB transfer data count */
|
|
||||||
static inline uint32_t usbh_xfercount_get (usb_core_driver *pudev, uint8_t pp_num)
|
|
||||||
{
|
|
||||||
return pudev->host.backup_xfercount[pp_num];
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* __USBH_CORE_H */
|
|
||||||
|
|
||||||
|
|
@ -1,78 +0,0 @@
|
||||||
/*!
|
|
||||||
\file usbh_enum.h
|
|
||||||
\brief USB host mode USB enumeration header file
|
|
||||||
|
|
||||||
\version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __USBH_ENUM_H
|
|
||||||
#define __USBH_ENUM_H
|
|
||||||
|
|
||||||
#include "usb_conf.h"
|
|
||||||
#include "usbh_core.h"
|
|
||||||
|
|
||||||
/* get the next descriptor header */
|
|
||||||
usb_desc_header *usbh_nextdesc_get (uint8_t *pbuf, uint16_t *ptr);
|
|
||||||
|
|
||||||
/* configure USB control status parameters */
|
|
||||||
void usbh_ctlstate_config (usbh_host *puhost, uint8_t *buf, uint16_t len);
|
|
||||||
|
|
||||||
/* get device descriptor from the USB device */
|
|
||||||
usbh_status usbh_devdesc_get (usb_core_driver *pudev, usbh_host *puhost, uint8_t len);
|
|
||||||
|
|
||||||
/* get configuration descriptor from the USB device */
|
|
||||||
usbh_status usbh_cfgdesc_get (usb_core_driver *pudev, usbh_host *puhost, uint16_t len);
|
|
||||||
|
|
||||||
/* get string descriptor from the USB device */
|
|
||||||
usbh_status usbh_strdesc_get (usb_core_driver *pudev,
|
|
||||||
usbh_host *puhost,
|
|
||||||
uint8_t str_index,
|
|
||||||
uint8_t *buf,
|
|
||||||
uint16_t len);
|
|
||||||
|
|
||||||
/* set the configuration value to the connected device */
|
|
||||||
usbh_status usbh_setcfg (usb_core_driver *pudev, usbh_host *puhost, uint16_t config);
|
|
||||||
|
|
||||||
/* set the address to the connected device */
|
|
||||||
usbh_status usbh_setaddress (usb_core_driver *pudev, usbh_host *puhost, uint8_t dev_addr);
|
|
||||||
|
|
||||||
/* clear or disable a specific feature */
|
|
||||||
usbh_status usbh_clrfeature (usb_core_driver *pudev,
|
|
||||||
usbh_host *puhost,
|
|
||||||
uint8_t ep_num,
|
|
||||||
uint8_t pp_num);
|
|
||||||
|
|
||||||
/* set the interface value to the connected device */
|
|
||||||
usbh_status usbh_setinterface (usb_core_driver *pudev,
|
|
||||||
usbh_host *puhost,
|
|
||||||
uint8_t ep_num,
|
|
||||||
uint8_t alter_setting);
|
|
||||||
|
|
||||||
#endif /* __USBH_ENUM_H */
|
|
||||||
|
|
@ -1,70 +0,0 @@
|
||||||
/*!
|
|
||||||
\file usbh_pipe.h
|
|
||||||
\brief USB host mode pipe header file
|
|
||||||
|
|
||||||
\version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __USBH_PIPE_H
|
|
||||||
#define __USBH_PIPE_H
|
|
||||||
|
|
||||||
#include "usbh_core.h"
|
|
||||||
|
|
||||||
#define HC_MAX 8U
|
|
||||||
|
|
||||||
#define HC_OK 0x0000U
|
|
||||||
#define HC_USED 0x8000U
|
|
||||||
#define HC_ERROR 0xFFFFU
|
|
||||||
#define HC_USED_MASK 0x7FFFU
|
|
||||||
|
|
||||||
/* allocate a new pipe */
|
|
||||||
uint8_t usbh_pipe_allocate (usb_core_driver *pudev, uint8_t ep_addr);
|
|
||||||
|
|
||||||
/* delete all USB host pipe */
|
|
||||||
uint8_t usbh_pipe_delete (usb_core_driver *pudev);
|
|
||||||
|
|
||||||
/* free a pipe */
|
|
||||||
uint8_t usbh_pipe_free (usb_core_driver *pudev, uint8_t pp_num);
|
|
||||||
|
|
||||||
/* create a pipe */
|
|
||||||
uint8_t usbh_pipe_create (usb_core_driver *pudev,
|
|
||||||
usb_dev_prop *udev,
|
|
||||||
uint8_t pp_num,
|
|
||||||
uint8_t ep_type,
|
|
||||||
uint16_t ep_mpl);
|
|
||||||
|
|
||||||
/* modify a pipe */
|
|
||||||
uint8_t usbh_pipe_update (usb_core_driver *pudev,
|
|
||||||
uint8_t pp_num,
|
|
||||||
uint8_t dev_addr,
|
|
||||||
uint32_t dev_speed,
|
|
||||||
uint16_t ep_mpl);
|
|
||||||
|
|
||||||
#endif /* __USBH_PIPE_H */
|
|
||||||
|
|
@ -1,54 +0,0 @@
|
||||||
/*!
|
|
||||||
\file usbh_transc.h
|
|
||||||
\brief USB host mode transactions header file
|
|
||||||
|
|
||||||
\version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __USBH_TRANSC_H
|
|
||||||
#define __USBH_TRANSC_H
|
|
||||||
|
|
||||||
#include "usb_conf.h"
|
|
||||||
#include "usbh_core.h"
|
|
||||||
|
|
||||||
/* send the setup packet to the USB device */
|
|
||||||
usbh_status usbh_ctlsetup_send (usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num);
|
|
||||||
|
|
||||||
/* send a data packet to the USB device */
|
|
||||||
usbh_status usbh_data_send (usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num, uint16_t len);
|
|
||||||
|
|
||||||
/* receive a data packet from the USB device */
|
|
||||||
usbh_status usbh_data_recev (usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num, uint16_t len);
|
|
||||||
|
|
||||||
/* USB control transfer handler */
|
|
||||||
usbh_status usbh_ctl_handler (usb_core_driver *pudev, usbh_host *puhost);
|
|
||||||
|
|
||||||
#endif /* __USBH_TRANSC_H */
|
|
||||||
|
|
||||||
|
|
@ -1,390 +0,0 @@
|
||||||
/******************************************************************************
|
|
||||||
* @file gd32vf103.h
|
|
||||||
* @brief NMSIS Core Peripheral Access Layer Header File for GD32VF103 series
|
|
||||||
*
|
|
||||||
* @version V1.00
|
|
||||||
* @date 4. Jan 2020
|
|
||||||
******************************************************************************/
|
|
||||||
/*
|
|
||||||
* Copyright (c) 2019 Nuclei Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
|
||||||
* not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
|
||||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __GD32VF103_H__
|
|
||||||
#define __GD32VF103_H__
|
|
||||||
|
|
||||||
#include <stddef.h>
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/** @addtogroup gd32
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/** @addtogroup gd32vf103
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/** @addtogroup Configuration_of_NMSIS
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/* =========================================================================================================================== */
|
|
||||||
/* ================ Interrupt Number Definition ================ */
|
|
||||||
/* =========================================================================================================================== */
|
|
||||||
|
|
||||||
typedef enum IRQn
|
|
||||||
{
|
|
||||||
/* ======================================= Nuclei Core Specific Interrupt Numbers ======================================== */
|
|
||||||
|
|
||||||
Reserved0_IRQn = 0, /*!< Internal reserved */
|
|
||||||
Reserved1_IRQn = 1, /*!< Internal reserved */
|
|
||||||
Reserved2_IRQn = 2, /*!< Internal reserved */
|
|
||||||
SysTimerSW_IRQn = 3, /*!< System Timer SW interrupt */
|
|
||||||
Reserved3_IRQn = 4, /*!< Internal reserved */
|
|
||||||
Reserved4_IRQn = 5, /*!< Internal reserved */
|
|
||||||
Reserved5_IRQn = 6, /*!< Internal reserved */
|
|
||||||
SysTimer_IRQn = 7, /*!< System Timer Interrupt */
|
|
||||||
Reserved6_IRQn = 8, /*!< Internal reserved */
|
|
||||||
Reserved7_IRQn = 9, /*!< Internal reserved */
|
|
||||||
Reserved8_IRQn = 10, /*!< Internal reserved */
|
|
||||||
Reserved9_IRQn = 11, /*!< Internal reserved */
|
|
||||||
Reserved10_IRQn = 12, /*!< Internal reserved */
|
|
||||||
Reserved11_IRQn = 13, /*!< Internal reserved */
|
|
||||||
Reserved12_IRQn = 14, /*!< Internal reserved */
|
|
||||||
Reserved13_IRQn = 15, /*!< Internal reserved */
|
|
||||||
Reserved14_IRQn = 16, /*!< Internal reserved */
|
|
||||||
BusError_IRQn = 17, /*!< Bus Error interrupt */
|
|
||||||
PerfMon_IRQn = 18, /*!< Performance Monitor */
|
|
||||||
|
|
||||||
/* =========================================== GD32VF103 Specific Interrupt Numbers ========================================= */
|
|
||||||
/* ToDo: add here your device specific external interrupt numbers. 19~1023 is reserved number for user. Maxmum interrupt supported
|
|
||||||
could get from clicinfo.NUM_INTERRUPT. According the interrupt handlers defined in startup_Device.s
|
|
||||||
eg.: Interrupt for Timer#1 TIM1_IRQHandler -> TIM1_IRQn */
|
|
||||||
/* interruput numbers */
|
|
||||||
WWDGT_IRQn = 19, /*!< window watchDog timer interrupt */
|
|
||||||
LVD_IRQn = 20, /*!< LVD through EXTI line detect interrupt */
|
|
||||||
TAMPER_IRQn = 21, /*!< tamper through EXTI line detect */
|
|
||||||
RTC_IRQn = 22, /*!< RTC alarm interrupt */
|
|
||||||
FMC_IRQn = 23, /*!< FMC interrupt */
|
|
||||||
RCU_CTC_IRQn = 24, /*!< RCU and CTC interrupt */
|
|
||||||
EXTI0_IRQn = 25, /*!< EXTI line 0 interrupts */
|
|
||||||
EXTI1_IRQn = 26, /*!< EXTI line 1 interrupts */
|
|
||||||
EXTI2_IRQn = 27, /*!< EXTI line 2 interrupts */
|
|
||||||
EXTI3_IRQn = 28, /*!< EXTI line 3 interrupts */
|
|
||||||
EXTI4_IRQn = 29, /*!< EXTI line 4 interrupts */
|
|
||||||
DMA0_Channel0_IRQn = 30, /*!< DMA0 channel0 interrupt */
|
|
||||||
DMA0_Channel1_IRQn = 31, /*!< DMA0 channel1 interrupt */
|
|
||||||
DMA0_Channel2_IRQn = 32, /*!< DMA0 channel2 interrupt */
|
|
||||||
DMA0_Channel3_IRQn = 33, /*!< DMA0 channel3 interrupt */
|
|
||||||
DMA0_Channel4_IRQn = 34, /*!< DMA0 channel4 interrupt */
|
|
||||||
DMA0_Channel5_IRQn = 35, /*!< DMA0 channel5 interrupt */
|
|
||||||
DMA0_Channel6_IRQn = 36, /*!< DMA0 channel6 interrupt */
|
|
||||||
ADC0_1_IRQn = 37, /*!< ADC0 and ADC1 interrupt */
|
|
||||||
CAN0_TX_IRQn = 38, /*!< CAN0 TX interrupts */
|
|
||||||
CAN0_RX0_IRQn = 39, /*!< CAN0 RX0 interrupts */
|
|
||||||
CAN0_RX1_IRQn = 40, /*!< CAN0 RX1 interrupts */
|
|
||||||
CAN0_EWMC_IRQn = 41, /*!< CAN0 EWMC interrupts */
|
|
||||||
EXTI5_9_IRQn = 42, /*!< EXTI[9:5] interrupts */
|
|
||||||
TIMER0_BRK_IRQn = 43, /*!< TIMER0 break interrupts */
|
|
||||||
TIMER0_UP_IRQn = 44, /*!< TIMER0 update interrupts */
|
|
||||||
TIMER0_TRG_CMT_IRQn = 45, /*!< TIMER0 trigger and commutation interrupts */
|
|
||||||
TIMER0_Channel_IRQn = 46, /*!< TIMER0 channel capture compare interrupts */
|
|
||||||
TIMER1_IRQn = 47, /*!< TIMER1 interrupt */
|
|
||||||
TIMER2_IRQn = 48, /*!< TIMER2 interrupt */
|
|
||||||
TIMER3_IRQn = 49, /*!< TIMER3 interrupts */
|
|
||||||
I2C0_EV_IRQn = 50, /*!< I2C0 event interrupt */
|
|
||||||
I2C0_ER_IRQn = 51, /*!< I2C0 error interrupt */
|
|
||||||
I2C1_EV_IRQn = 52, /*!< I2C1 event interrupt */
|
|
||||||
I2C1_ER_IRQn = 53, /*!< I2C1 error interrupt */
|
|
||||||
SPI0_IRQn = 54, /*!< SPI0 interrupt */
|
|
||||||
SPI1_IRQn = 55, /*!< SPI1 interrupt */
|
|
||||||
USART0_IRQn = 56, /*!< USART0 interrupt */
|
|
||||||
USART1_IRQn = 57, /*!< USART1 interrupt */
|
|
||||||
USART2_IRQn = 58, /*!< USART2 interrupt */
|
|
||||||
EXTI10_15_IRQn = 59, /*!< EXTI[15:10] interrupts */
|
|
||||||
RTC_ALARM_IRQn = 60, /*!< RTC alarm interrupt EXTI */
|
|
||||||
USBFS_WKUP_IRQn = 61, /*!< USBFS wakeup interrupt */
|
|
||||||
|
|
||||||
EXMC_IRQn = 67, /*!< EXMC global interrupt */
|
|
||||||
|
|
||||||
TIMER4_IRQn = 69, /*!< TIMER4 global interrupt */
|
|
||||||
SPI2_IRQn = 70, /*!< SPI2 global interrupt */
|
|
||||||
UART3_IRQn = 71, /*!< UART3 global interrupt */
|
|
||||||
UART4_IRQn = 72, /*!< UART4 global interrupt */
|
|
||||||
TIMER5_IRQn = 73, /*!< TIMER5 global interrupt */
|
|
||||||
TIMER6_IRQn = 74, /*!< TIMER6 global interrupt */
|
|
||||||
DMA1_Channel0_IRQn = 75, /*!< DMA1 channel0 global interrupt */
|
|
||||||
DMA1_Channel1_IRQn = 76, /*!< DMA1 channel1 global interrupt */
|
|
||||||
DMA1_Channel2_IRQn = 77, /*!< DMA1 channel2 global interrupt */
|
|
||||||
DMA1_Channel3_IRQn = 78, /*!< DMA1 channel3 global interrupt */
|
|
||||||
DMA1_Channel4_IRQn = 79, /*!< DMA1 channel3 global interrupt */
|
|
||||||
|
|
||||||
CAN1_TX_IRQn = 82, /*!< CAN1 TX interrupt */
|
|
||||||
CAN1_RX0_IRQn = 83, /*!< CAN1 RX0 interrupt */
|
|
||||||
CAN1_RX1_IRQn = 84, /*!< CAN1 RX1 interrupt */
|
|
||||||
CAN1_EWMC_IRQn = 85, /*!< CAN1 EWMC interrupt */
|
|
||||||
USBFS_IRQn = 86, /*!< USBFS global interrupt */
|
|
||||||
|
|
||||||
SOC_INT_MAX,
|
|
||||||
|
|
||||||
} IRQn_Type;
|
|
||||||
|
|
||||||
/* =========================================================================================================================== */
|
|
||||||
/* ================ Exception Code Definition ================ */
|
|
||||||
/* =========================================================================================================================== */
|
|
||||||
|
|
||||||
typedef enum EXCn {
|
|
||||||
/* ======================================= Nuclei N/NX Specific Exception Code ======================================== */
|
|
||||||
InsUnalign_EXCn = 0, /*!< Instruction address misaligned */
|
|
||||||
InsAccFault_EXCn = 1, /*!< Instruction access fault */
|
|
||||||
IlleIns_EXCn = 2, /*!< Illegal instruction */
|
|
||||||
Break_EXCn = 3, /*!< Beakpoint */
|
|
||||||
LdAddrUnalign_EXCn = 4, /*!< Load address misaligned */
|
|
||||||
LdFault_EXCn = 5, /*!< Load access fault */
|
|
||||||
StAddrUnalign_EXCn = 6, /*!< Store or AMO address misaligned */
|
|
||||||
StAccessFault_EXCn = 7, /*!< Store or AMO access fault */
|
|
||||||
UmodeEcall_EXCn = 8, /*!< Environment call from User mode */
|
|
||||||
MmodeEcall_EXCn = 11, /*!< Environment call from Machine mode */
|
|
||||||
NMI_EXCn = 0xfff, /*!< NMI interrupt*/
|
|
||||||
} EXCn_Type;
|
|
||||||
|
|
||||||
/* =========================================================================================================================== */
|
|
||||||
/* ================ Processor and Core Peripheral Section ================ */
|
|
||||||
/* =========================================================================================================================== */
|
|
||||||
|
|
||||||
/* ToDo: set the defines according your Device */
|
|
||||||
/* ToDo: define the correct core revision */
|
|
||||||
#define __NUCLEI_N_REV 0x0100 /*!< Core Revision r1p0 */
|
|
||||||
|
|
||||||
/* ToDo: define the correct core features for the nuclei_soc */
|
|
||||||
#define __ECLIC_PRESENT 1 /*!< Set to 1 if ECLIC is present */
|
|
||||||
#define __ECLIC_BASEADDR 0xD2000000UL /*!< Set to ECLIC baseaddr of your device */
|
|
||||||
|
|
||||||
#define __ECLIC_INTCTLBITS 4 /*!< Set to 1 - 8, the number of hardware bits are actually implemented in the clicintctl registers. */
|
|
||||||
#define __ECLIC_INTNUM 86 /*!< Set to 1 - 1005, the external interrupt number of ECLIC Unit */
|
|
||||||
#define __SYSTIMER_PRESENT 1 /*!< Set to 1 if System Timer is present */
|
|
||||||
#define __SYSTIMER_BASEADDR 0xD1000000UL /*!< Set to SysTimer baseaddr of your device */
|
|
||||||
|
|
||||||
/*!< Set to 0, 1, or 2, 0 not present, 1 single floating point unit present, 2 double floating point unit present */
|
|
||||||
#define __FPU_PRESENT 0
|
|
||||||
|
|
||||||
#define __DSP_PRESENT 0 /*!< Set to 1 if DSP is present */
|
|
||||||
#define __PMP_PRESENT 1 /*!< Set to 1 if PMP is present */
|
|
||||||
#define __PMP_ENTRY_NUM 8 /*!< Set to 8 or 16, the number of PMP entries */
|
|
||||||
#define __ICACHE_PRESENT 0 /*!< Set to 1 if I-Cache is present */
|
|
||||||
#define __DCACHE_PRESENT 0 /*!< Set to 1 if D-Cache is present */
|
|
||||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
|
||||||
#define __Vendor_EXCEPTION 0 /*!< Set to 1 if vendor exception handler is present */
|
|
||||||
|
|
||||||
/** @} */ /* End of group Configuration_of_CMSIS */
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
#include <nmsis_core.h> /*!< Nuclei N/NX class processor and core peripherals */
|
|
||||||
/* ToDo: include your system_nuclei_soc.h file
|
|
||||||
replace 'Device' with your device name */
|
|
||||||
#include "system_gd32vf103.h" /*!< gd32vf103 System */
|
|
||||||
|
|
||||||
|
|
||||||
/* ======================================== Start of section using anonymous unions ======================================== */
|
|
||||||
#if defined (__GNUC__)
|
|
||||||
/* anonymous unions are enabled by default */
|
|
||||||
#else
|
|
||||||
#warning Not supported compiler type
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
/* system frequency define */
|
|
||||||
#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */
|
|
||||||
#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */
|
|
||||||
#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */
|
|
||||||
|
|
||||||
#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000)
|
|
||||||
|
|
||||||
|
|
||||||
#define RTC_FREQ LXTAL_VALUE
|
|
||||||
// The TIMER frequency is just the RTC frequency
|
|
||||||
#define SOC_TIMER_FREQ ((uint32_t)SystemCoreClock/4) //LXTAL_VALUE units HZ
|
|
||||||
|
|
||||||
|
|
||||||
/* enum definitions */
|
|
||||||
typedef enum {
|
|
||||||
DISABLE = 0,
|
|
||||||
ENABLE = !DISABLE
|
|
||||||
} EventStatus, ControlStatus;
|
|
||||||
|
|
||||||
// Already defined
|
|
||||||
// typedef enum {
|
|
||||||
// FALSE = 0,
|
|
||||||
// TRUE = !FALSE
|
|
||||||
// } BOOL;
|
|
||||||
|
|
||||||
typedef enum {
|
|
||||||
RESET = 0,
|
|
||||||
SET = 1,
|
|
||||||
MAX = 0X7FFFFFFF
|
|
||||||
} FlagStatus;
|
|
||||||
|
|
||||||
typedef enum {
|
|
||||||
ERROR = 0,
|
|
||||||
SUCCESS = !ERROR
|
|
||||||
} ErrStatus;
|
|
||||||
|
|
||||||
/* =========================================================================================================================== */
|
|
||||||
/* ================ Device Specific Peripheral Section ================ */
|
|
||||||
/* =========================================================================================================================== */
|
|
||||||
|
|
||||||
|
|
||||||
/** @addtogroup Device_Peripheral_peripherals
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Platform definitions
|
|
||||||
*****************************************************************************/
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/* ToDo: add here your device specific peripheral access structure typedefs
|
|
||||||
following is an example for Systick Timer*/
|
|
||||||
|
|
||||||
/* =========================================================================================================================== */
|
|
||||||
/* ================ SysTick Timer ================ */
|
|
||||||
/* =========================================================================================================================== */
|
|
||||||
|
|
||||||
/*@}*/ /* end of group nuclei_soc_Peripherals */
|
|
||||||
|
|
||||||
|
|
||||||
/* ========================================= End of section using anonymous unions ========================================= */
|
|
||||||
#if defined (__GNUC__)
|
|
||||||
/* anonymous unions are enabled by default */
|
|
||||||
#else
|
|
||||||
#warning Not supported compiler type
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
/* =========================================================================================================================== */
|
|
||||||
/* ================ Device Specific Peripheral Address Map ================ */
|
|
||||||
/* =========================================================================================================================== */
|
|
||||||
|
|
||||||
|
|
||||||
/* ToDo: add here your device peripherals base addresses
|
|
||||||
following is an example for timer */
|
|
||||||
/** @addtogroup Device_Peripheral_peripheralAddr
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* main flash and SRAM memory map */
|
|
||||||
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
|
|
||||||
#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */
|
|
||||||
#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */
|
|
||||||
#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */
|
|
||||||
#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */
|
|
||||||
|
|
||||||
/* peripheral memory map */
|
|
||||||
#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
|
|
||||||
#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
|
|
||||||
#define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */
|
|
||||||
#define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */
|
|
||||||
|
|
||||||
/* advanced peripheral bus 1 memory map */
|
|
||||||
#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
|
|
||||||
#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
|
|
||||||
#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
|
|
||||||
#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
|
|
||||||
#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
|
|
||||||
#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
|
|
||||||
#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
|
|
||||||
#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */
|
|
||||||
#define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */
|
|
||||||
#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
|
|
||||||
#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */
|
|
||||||
|
|
||||||
/* advanced peripheral bus 2 memory map */
|
|
||||||
#define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */
|
|
||||||
#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */
|
|
||||||
#define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */
|
|
||||||
#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */
|
|
||||||
|
|
||||||
/* advanced high performance bus 1 memory map */
|
|
||||||
#define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */
|
|
||||||
#define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */
|
|
||||||
#define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */
|
|
||||||
#define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */
|
|
||||||
#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */
|
|
||||||
|
|
||||||
|
|
||||||
/** @} */ /* End of group Device_Peripheral_peripheralAddr */
|
|
||||||
|
|
||||||
|
|
||||||
/* =========================================================================================================================== */
|
|
||||||
/* ================ Peripheral declaration ================ */
|
|
||||||
/* =========================================================================================================================== */
|
|
||||||
|
|
||||||
|
|
||||||
/* ToDo: add here your device peripherals pointer definitions
|
|
||||||
following is an example for timer */
|
|
||||||
/** @addtogroup Device_Peripheral_declaration
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* bit operations */
|
|
||||||
#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
|
|
||||||
#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
|
|
||||||
#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
|
|
||||||
#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
|
|
||||||
#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
|
|
||||||
#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
|
|
||||||
|
|
||||||
// Interrupt Numbers
|
|
||||||
#define SOC_ECLIC_NUM_INTERRUPTS 86
|
|
||||||
#define SOC_ECLIC_INT_GPIO_BASE 19
|
|
||||||
|
|
||||||
|
|
||||||
// Interrupt Handler Definitions
|
|
||||||
#define SOC_MTIMER_HANDLER eclic_mtip_handler
|
|
||||||
#define SOC_SOFTINT_HANDLER eclic_msip_handler
|
|
||||||
|
|
||||||
#define NUM_GPIO 32
|
|
||||||
|
|
||||||
extern uint32_t get_cpu_freq(void);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* \brief delay a time in milliseconds
|
|
||||||
* \param[in] count: count in milliseconds
|
|
||||||
* \param[out] none
|
|
||||||
* \retval none
|
|
||||||
*/
|
|
||||||
extern void delay_1ms(uint32_t count);
|
|
||||||
|
|
||||||
|
|
||||||
/** @} */ /* End of group gd32vf103_soc */
|
|
||||||
|
|
||||||
/** @} */ /* End of group gd32vf103 */
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* __GD32VF103_SOC_H__ */
|
|
||||||
|
|
@ -1,399 +0,0 @@
|
||||||
/*!
|
|
||||||
\file gd32vf103_adc.h
|
|
||||||
\brief definitions for the ADC
|
|
||||||
|
|
||||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef GD32VF103_ADC_H
|
|
||||||
#define GD32VF103_ADC_H
|
|
||||||
|
|
||||||
#include "gd32vf103.h"
|
|
||||||
#include "gd32vf103_rcu.h"
|
|
||||||
#include "gd32vf103_dbg.h"
|
|
||||||
|
|
||||||
/* ADC definitions */
|
|
||||||
#define ADC0 ADC_BASE
|
|
||||||
#define ADC1 (ADC_BASE + 0x400U)
|
|
||||||
|
|
||||||
|
|
||||||
/* registers definitions */
|
|
||||||
#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */
|
|
||||||
#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */
|
|
||||||
#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */
|
|
||||||
#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */
|
|
||||||
#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */
|
|
||||||
#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */
|
|
||||||
#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */
|
|
||||||
#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */
|
|
||||||
#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */
|
|
||||||
#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */
|
|
||||||
#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */
|
|
||||||
#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */
|
|
||||||
#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */
|
|
||||||
#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */
|
|
||||||
#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */
|
|
||||||
#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */
|
|
||||||
#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */
|
|
||||||
#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */
|
|
||||||
#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */
|
|
||||||
#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */
|
|
||||||
#define ADC_OVSCR(adcx) REG32((adcx) + 0x80U) /*!< ADC oversample control register */
|
|
||||||
|
|
||||||
/* bits definitions */
|
|
||||||
/* ADC_STAT */
|
|
||||||
#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */
|
|
||||||
#define ADC_STAT_EOC BIT(1) /*!< end of conversion */
|
|
||||||
#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */
|
|
||||||
#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */
|
|
||||||
#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */
|
|
||||||
|
|
||||||
/* ADC_CTL0 */
|
|
||||||
#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */
|
|
||||||
#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */
|
|
||||||
#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */
|
|
||||||
#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */
|
|
||||||
#define ADC_CTL0_SM BIT(8) /*!< scan mode */
|
|
||||||
#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */
|
|
||||||
#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */
|
|
||||||
#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */
|
|
||||||
#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */
|
|
||||||
#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */
|
|
||||||
#define ADC_CTL0_SYNCM BITS(16,19) /*!< sync mode selection */
|
|
||||||
#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */
|
|
||||||
#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */
|
|
||||||
|
|
||||||
/* ADC_CTL1 */
|
|
||||||
#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */
|
|
||||||
#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */
|
|
||||||
#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */
|
|
||||||
#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */
|
|
||||||
#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */
|
|
||||||
#define ADC_CTL1_DAL BIT(11) /*!< data alignment */
|
|
||||||
#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */
|
|
||||||
#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */
|
|
||||||
#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */
|
|
||||||
#define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */
|
|
||||||
#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */
|
|
||||||
#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */
|
|
||||||
#define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */
|
|
||||||
|
|
||||||
/* ADC_SAMPTx x=0..1 */
|
|
||||||
#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n sample time selection */
|
|
||||||
|
|
||||||
/* ADC_IOFFx x=0..3 */
|
|
||||||
#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */
|
|
||||||
|
|
||||||
/* ADC_WDHT */
|
|
||||||
#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */
|
|
||||||
|
|
||||||
/* ADC_WDLT */
|
|
||||||
#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */
|
|
||||||
|
|
||||||
/* ADC_RSQx x=0..2 */
|
|
||||||
#define ADC_RSQX_RSQN BITS(0,4) /*!< nth conversion in regular sequence */
|
|
||||||
#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */
|
|
||||||
|
|
||||||
/* ADC_ISQ */
|
|
||||||
#define ADC_ISQ_ISQN BITS(0,4) /*!< nth conversion in inserted sequence */
|
|
||||||
#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */
|
|
||||||
|
|
||||||
/* ADC_IDATAx x=0..3*/
|
|
||||||
#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data n */
|
|
||||||
|
|
||||||
/* ADC_RDATA */
|
|
||||||
#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */
|
|
||||||
#define ADC_RDATA_ADC1RDTR BITS(16,31) /*!< ADC1 regular channel data */
|
|
||||||
|
|
||||||
/* ADC_OVSCR */
|
|
||||||
#define ADC_OVSCR_OVSEN BIT(0) /*!< oversampling enable */
|
|
||||||
#define ADC_OVSCR_OVSR BITS(2,4) /*!< oversampling ratio */
|
|
||||||
#define ADC_OVSCR_OVSS BITS(5,8) /*!< oversampling shift */
|
|
||||||
#define ADC_OVSCR_TOVS BIT(9) /*!< triggered oversampling */
|
|
||||||
#define ADC_OVSCR_DRES BITS(12,13) /*!< ADC data resolution */
|
|
||||||
|
|
||||||
/* constants definitions */
|
|
||||||
/* adc_stat register value */
|
|
||||||
#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */
|
|
||||||
#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */
|
|
||||||
#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */
|
|
||||||
#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */
|
|
||||||
#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */
|
|
||||||
|
|
||||||
/* adc_ctl0 register value */
|
|
||||||
#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */
|
|
||||||
|
|
||||||
/* scan mode */
|
|
||||||
#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */
|
|
||||||
|
|
||||||
/* inserted channel group convert automatically */
|
|
||||||
#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */
|
|
||||||
|
|
||||||
/* ADC sync mode */
|
|
||||||
#define CTL0_SYNCM(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */
|
|
||||||
#define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */
|
|
||||||
#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */
|
|
||||||
#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */
|
|
||||||
#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(3) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode */
|
|
||||||
#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(4) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode */
|
|
||||||
#define ADC_DAUL_INSERTED_PARALLEL CTL0_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode only */
|
|
||||||
#define ADC_DAUL_REGULAL_PARALLEL CTL0_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode only */
|
|
||||||
#define ADC_DAUL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up fast mode only */
|
|
||||||
#define ADC_DAUL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(8) /*!< ADC0 and ADC1 work in follow-up slow mode only */
|
|
||||||
#define ADC_DAUL_INSERTED_TRIGGER_ROTATION CTL0_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode only */
|
|
||||||
|
|
||||||
/* adc_ctl1 register value */
|
|
||||||
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */
|
|
||||||
#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */
|
|
||||||
|
|
||||||
/* continuous mode */
|
|
||||||
#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */
|
|
||||||
|
|
||||||
/* external trigger select for regular channel */
|
|
||||||
#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */
|
|
||||||
/* for ADC0 and ADC1 regular channel */
|
|
||||||
#define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */
|
|
||||||
#define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */
|
|
||||||
#define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */
|
|
||||||
#define ADC0_1_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< TIMER1 CH1 event select */
|
|
||||||
#define ADC0_1_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */
|
|
||||||
#define ADC0_1_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(5) /*!< TIMER3 CH3 event select */
|
|
||||||
#define ADC0_1_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */
|
|
||||||
#define ADC0_1_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */
|
|
||||||
|
|
||||||
/* external trigger mode for inserted channel */
|
|
||||||
#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */
|
|
||||||
/* for ADC0 and ADC1 inserted channel */
|
|
||||||
#define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */
|
|
||||||
#define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */
|
|
||||||
#define ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< TIMER1 TRGO event select */
|
|
||||||
#define ADC0_1_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< TIMER1 CH0 event select */
|
|
||||||
#define ADC0_1_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */
|
|
||||||
#define ADC0_1_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(5) /*!< TIMER3 TRGO event select */
|
|
||||||
#define ADC0_1_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */
|
|
||||||
#define ADC0_1_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */
|
|
||||||
|
|
||||||
/* adc_samptx register value */
|
|
||||||
#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */
|
|
||||||
#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */
|
|
||||||
#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */
|
|
||||||
#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */
|
|
||||||
#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */
|
|
||||||
#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */
|
|
||||||
#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */
|
|
||||||
#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */
|
|
||||||
#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */
|
|
||||||
|
|
||||||
/* adc_ioffx register value */
|
|
||||||
#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */
|
|
||||||
|
|
||||||
/* adc_wdht register value */
|
|
||||||
#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */
|
|
||||||
|
|
||||||
/* adc_wdlt register value */
|
|
||||||
#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */
|
|
||||||
|
|
||||||
/* adc_rsqx register value */
|
|
||||||
#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */
|
|
||||||
|
|
||||||
/* adc_isq register value */
|
|
||||||
#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */
|
|
||||||
|
|
||||||
/* ADC channel group definitions */
|
|
||||||
#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */
|
|
||||||
#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */
|
|
||||||
#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */
|
|
||||||
|
|
||||||
#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */
|
|
||||||
|
|
||||||
/* ADC inserted channel definitions */
|
|
||||||
#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */
|
|
||||||
#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */
|
|
||||||
#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */
|
|
||||||
#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */
|
|
||||||
|
|
||||||
/* ADC channel definitions */
|
|
||||||
#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */
|
|
||||||
#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */
|
|
||||||
#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */
|
|
||||||
#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */
|
|
||||||
#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */
|
|
||||||
#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */
|
|
||||||
#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */
|
|
||||||
#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */
|
|
||||||
#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */
|
|
||||||
#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */
|
|
||||||
#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */
|
|
||||||
#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */
|
|
||||||
#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */
|
|
||||||
#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */
|
|
||||||
#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */
|
|
||||||
#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */
|
|
||||||
#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */
|
|
||||||
#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */
|
|
||||||
|
|
||||||
/* ADC interrupt */
|
|
||||||
#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */
|
|
||||||
#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */
|
|
||||||
#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */
|
|
||||||
|
|
||||||
/* ADC interrupt flag */
|
|
||||||
#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */
|
|
||||||
#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */
|
|
||||||
#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */
|
|
||||||
|
|
||||||
/* ADC resolution definitions */
|
|
||||||
#define OVSCR_DRES(regval) (BITS(12,13) & ((uint32_t)(regval) << 12))
|
|
||||||
#define ADC_RESOLUTION_12B OVSCR_DRES(0) /*!< 12-bit ADC resolution */
|
|
||||||
#define ADC_RESOLUTION_10B OVSCR_DRES(1) /*!< 10-bit ADC resolution */
|
|
||||||
#define ADC_RESOLUTION_8B OVSCR_DRES(2) /*!< 8-bit ADC resolution */
|
|
||||||
#define ADC_RESOLUTION_6B OVSCR_DRES(3) /*!< 6-bit ADC resolution */
|
|
||||||
|
|
||||||
/* ADC oversampling mode */
|
|
||||||
#define ADC_OVERSAMPLING_ALL_CONVERT 0 /*!< all oversampled conversions for a channel are done consecutively after a trigger */
|
|
||||||
#define ADC_OVERSAMPLING_ONE_CONVERT 1 /*!< each oversampled conversion for a channel needs a trigger */
|
|
||||||
|
|
||||||
/* ADC oversampling shift */
|
|
||||||
#define OVSCR_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5))
|
|
||||||
#define ADC_OVERSAMPLING_SHIFT_NONE OVSCR_OVSS(0) /*!< no oversampling shift */
|
|
||||||
#define ADC_OVERSAMPLING_SHIFT_1B OVSCR_OVSS(1) /*!< 1-bit oversampling shift */
|
|
||||||
#define ADC_OVERSAMPLING_SHIFT_2B OVSCR_OVSS(2) /*!< 2-bit oversampling shift */
|
|
||||||
#define ADC_OVERSAMPLING_SHIFT_3B OVSCR_OVSS(3) /*!< 3-bit oversampling shift */
|
|
||||||
#define ADC_OVERSAMPLING_SHIFT_4B OVSCR_OVSS(4) /*!< 4-bit oversampling shift */
|
|
||||||
#define ADC_OVERSAMPLING_SHIFT_5B OVSCR_OVSS(5) /*!< 5-bit oversampling shift */
|
|
||||||
#define ADC_OVERSAMPLING_SHIFT_6B OVSCR_OVSS(6) /*!< 6-bit oversampling shift */
|
|
||||||
#define ADC_OVERSAMPLING_SHIFT_7B OVSCR_OVSS(7) /*!< 7-bit oversampling shift */
|
|
||||||
#define ADC_OVERSAMPLING_SHIFT_8B OVSCR_OVSS(8) /*!< 8-bit oversampling shift */
|
|
||||||
|
|
||||||
/* ADC oversampling ratio */
|
|
||||||
#define OVSCR_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2))
|
|
||||||
#define ADC_OVERSAMPLING_RATIO_MUL2 OVSCR_OVSR(0) /*!< oversampling ratio X2 */
|
|
||||||
#define ADC_OVERSAMPLING_RATIO_MUL4 OVSCR_OVSR(1) /*!< oversampling ratio X4 */
|
|
||||||
#define ADC_OVERSAMPLING_RATIO_MUL8 OVSCR_OVSR(2) /*!< oversampling ratio X8 */
|
|
||||||
#define ADC_OVERSAMPLING_RATIO_MUL16 OVSCR_OVSR(3) /*!< oversampling ratio X16 */
|
|
||||||
#define ADC_OVERSAMPLING_RATIO_MUL32 OVSCR_OVSR(4) /*!< oversampling ratio X32 */
|
|
||||||
#define ADC_OVERSAMPLING_RATIO_MUL64 OVSCR_OVSR(5) /*!< oversampling ratio X64 */
|
|
||||||
#define ADC_OVERSAMPLING_RATIO_MUL128 OVSCR_OVSR(6) /*!< oversampling ratio X128 */
|
|
||||||
#define ADC_OVERSAMPLING_RATIO_MUL256 OVSCR_OVSR(7) /*!< oversampling ratio X256 */
|
|
||||||
|
|
||||||
/* function declarations */
|
|
||||||
/* initialization config */
|
|
||||||
/* reset ADC */
|
|
||||||
void adc_deinit(uint32_t adc_periph);
|
|
||||||
/* configure the ADC sync mode */
|
|
||||||
void adc_mode_config(uint32_t adc_periph, uint32_t mode);
|
|
||||||
/* enable or disable ADC special function */
|
|
||||||
void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue);
|
|
||||||
/* configure ADC data alignment */
|
|
||||||
void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment);
|
|
||||||
/* enable ADC interface */
|
|
||||||
void adc_enable(uint32_t adc_periph);
|
|
||||||
/* disable ADC interface */
|
|
||||||
void adc_disable(uint32_t adc_periph);
|
|
||||||
/* ADC calibration and reset calibration */
|
|
||||||
void adc_calibration_enable(uint32_t adc_periph);
|
|
||||||
/* enable the temperature sensor and Vrefint channel */
|
|
||||||
void adc_tempsensor_vrefint_enable(void);
|
|
||||||
/* disable the temperature sensor and Vrefint channel */
|
|
||||||
void adc_tempsensor_vrefint_disable(void);
|
|
||||||
|
|
||||||
/* DMA config */
|
|
||||||
/* enable DMA request */
|
|
||||||
void adc_dma_mode_enable(uint32_t adc_periph);
|
|
||||||
/* disable DMA request */
|
|
||||||
void adc_dma_mode_disable(uint32_t adc_periph);
|
|
||||||
|
|
||||||
/* regular group and inserted group config */
|
|
||||||
/* configure ADC discontinuous mode */
|
|
||||||
void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length);
|
|
||||||
|
|
||||||
/* configure the length of regular channel group or inserted channel group */
|
|
||||||
void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length);
|
|
||||||
/* configure ADC regular channel */
|
|
||||||
void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time);
|
|
||||||
/* configure ADC inserted channel */
|
|
||||||
void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time);
|
|
||||||
/* configure ADC inserted channel offset */
|
|
||||||
void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset);
|
|
||||||
|
|
||||||
/* configure ADC external trigger source */
|
|
||||||
void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source);
|
|
||||||
/* configure ADC external trigger */
|
|
||||||
void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue);
|
|
||||||
/* enable ADC software trigger */
|
|
||||||
void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group);
|
|
||||||
|
|
||||||
/* get channel data */
|
|
||||||
/* read ADC regular group data register */
|
|
||||||
uint16_t adc_regular_data_read(uint32_t adc_periph);
|
|
||||||
/* read ADC inserted group data register */
|
|
||||||
uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel);
|
|
||||||
/* read the last ADC0 and ADC1 conversion result data in sync mode */
|
|
||||||
uint32_t adc_sync_mode_convert_value_read(void);
|
|
||||||
|
|
||||||
/* watchdog config */
|
|
||||||
/* configure ADC analog watchdog single channel */
|
|
||||||
void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel);
|
|
||||||
/* configure ADC analog watchdog group channel */
|
|
||||||
void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group);
|
|
||||||
/* disable ADC analog watchdog */
|
|
||||||
void adc_watchdog_disable(uint32_t adc_periph);
|
|
||||||
/* configure ADC analog watchdog threshold */
|
|
||||||
void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold);
|
|
||||||
|
|
||||||
/* interrupt & flag functions */
|
|
||||||
/* get the ADC flag bits */
|
|
||||||
FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag);
|
|
||||||
/* clear the ADC flag bits */
|
|
||||||
void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag);
|
|
||||||
/* get the bit state of ADCx software start conversion */
|
|
||||||
FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph);
|
|
||||||
/* get the bit state of ADCx software inserted channel start conversion */
|
|
||||||
FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph);
|
|
||||||
/* get the ADC interrupt bits */
|
|
||||||
FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt);
|
|
||||||
/* clear the ADC flag */
|
|
||||||
void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt);
|
|
||||||
/* enable ADC interrupt */
|
|
||||||
void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt);
|
|
||||||
/* disable ADC interrupt */
|
|
||||||
void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt);
|
|
||||||
|
|
||||||
/* ADC resolution & oversample */
|
|
||||||
/* ADC resolution config */
|
|
||||||
void adc_resolution_config(uint32_t adc_periph, uint32_t resolution);
|
|
||||||
/* ADC oversample mode config */
|
|
||||||
void adc_oversample_mode_config(uint32_t adc_periph, uint8_t mode, uint16_t shift, uint8_t ratio);
|
|
||||||
/* enable ADC oversample mode */
|
|
||||||
void adc_oversample_mode_enable(uint32_t adc_periph);
|
|
||||||
/* disable ADC oversample mode */
|
|
||||||
void adc_oversample_mode_disable(uint32_t adc_periph);
|
|
||||||
|
|
||||||
#endif /* GD32VF103_ADC_H */
|
|
||||||
|
|
@ -1,229 +0,0 @@
|
||||||
/*!
|
|
||||||
\file gd32vf103_bkp.h
|
|
||||||
\brief definitions for the BKP
|
|
||||||
|
|
||||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef GD32VF103_BKP_H
|
|
||||||
#define GD32VF103_BKP_H
|
|
||||||
|
|
||||||
#include "gd32vf103.h"
|
|
||||||
#include "gd32vf103_rcu.h"
|
|
||||||
#include "gd32vf103_dbg.h"
|
|
||||||
|
|
||||||
/* BKP definitions */
|
|
||||||
#define BKP BKP_BASE /*!< BKP base address */
|
|
||||||
|
|
||||||
/* registers definitions */
|
|
||||||
#define BKP_DATA0 REG16((BKP) + 0x04U) /*!< BKP data register 0 */
|
|
||||||
#define BKP_DATA1 REG16((BKP) + 0x08U) /*!< BKP data register 1 */
|
|
||||||
#define BKP_DATA2 REG16((BKP) + 0x0CU) /*!< BKP data register 2 */
|
|
||||||
#define BKP_DATA3 REG16((BKP) + 0x10U) /*!< BKP data register 3 */
|
|
||||||
#define BKP_DATA4 REG16((BKP) + 0x14U) /*!< BKP data register 4 */
|
|
||||||
#define BKP_DATA5 REG16((BKP) + 0x18U) /*!< BKP data register 5 */
|
|
||||||
#define BKP_DATA6 REG16((BKP) + 0x1CU) /*!< BKP data register 6 */
|
|
||||||
#define BKP_DATA7 REG16((BKP) + 0x20U) /*!< BKP data register 7 */
|
|
||||||
#define BKP_DATA8 REG16((BKP) + 0x24U) /*!< BKP data register 8 */
|
|
||||||
#define BKP_DATA9 REG16((BKP) + 0x28U) /*!< BKP data register 9 */
|
|
||||||
#define BKP_DATA10 REG16((BKP) + 0x40U) /*!< BKP data register 10 */
|
|
||||||
#define BKP_DATA11 REG16((BKP) + 0x44U) /*!< BKP data register 11 */
|
|
||||||
#define BKP_DATA12 REG16((BKP) + 0x48U) /*!< BKP data register 12 */
|
|
||||||
#define BKP_DATA13 REG16((BKP) + 0x4CU) /*!< BKP data register 13 */
|
|
||||||
#define BKP_DATA14 REG16((BKP) + 0x50U) /*!< BKP data register 14 */
|
|
||||||
#define BKP_DATA15 REG16((BKP) + 0x54U) /*!< BKP data register 15 */
|
|
||||||
#define BKP_DATA16 REG16((BKP) + 0x58U) /*!< BKP data register 16 */
|
|
||||||
#define BKP_DATA17 REG16((BKP) + 0x5CU) /*!< BKP data register 17 */
|
|
||||||
#define BKP_DATA18 REG16((BKP) + 0x60U) /*!< BKP data register 18 */
|
|
||||||
#define BKP_DATA19 REG16((BKP) + 0x64U) /*!< BKP data register 19 */
|
|
||||||
#define BKP_DATA20 REG16((BKP) + 0x68U) /*!< BKP data register 20 */
|
|
||||||
#define BKP_DATA21 REG16((BKP) + 0x6CU) /*!< BKP data register 21 */
|
|
||||||
#define BKP_DATA22 REG16((BKP) + 0x70U) /*!< BKP data register 22 */
|
|
||||||
#define BKP_DATA23 REG16((BKP) + 0x74U) /*!< BKP data register 23 */
|
|
||||||
#define BKP_DATA24 REG16((BKP) + 0x78U) /*!< BKP data register 24 */
|
|
||||||
#define BKP_DATA25 REG16((BKP) + 0x7CU) /*!< BKP data register 25 */
|
|
||||||
#define BKP_DATA26 REG16((BKP) + 0x80U) /*!< BKP data register 26 */
|
|
||||||
#define BKP_DATA27 REG16((BKP) + 0x84U) /*!< BKP data register 27 */
|
|
||||||
#define BKP_DATA28 REG16((BKP) + 0x88U) /*!< BKP data register 28 */
|
|
||||||
#define BKP_DATA29 REG16((BKP) + 0x8CU) /*!< BKP data register 29 */
|
|
||||||
#define BKP_DATA30 REG16((BKP) + 0x90U) /*!< BKP data register 30 */
|
|
||||||
#define BKP_DATA31 REG16((BKP) + 0x94U) /*!< BKP data register 31 */
|
|
||||||
#define BKP_DATA32 REG16((BKP) + 0x98U) /*!< BKP data register 32 */
|
|
||||||
#define BKP_DATA33 REG16((BKP) + 0x9CU) /*!< BKP data register 33 */
|
|
||||||
#define BKP_DATA34 REG16((BKP) + 0xA0U) /*!< BKP data register 34 */
|
|
||||||
#define BKP_DATA35 REG16((BKP) + 0xA4U) /*!< BKP data register 35 */
|
|
||||||
#define BKP_DATA36 REG16((BKP) + 0xA8U) /*!< BKP data register 36 */
|
|
||||||
#define BKP_DATA37 REG16((BKP) + 0xACU) /*!< BKP data register 37 */
|
|
||||||
#define BKP_DATA38 REG16((BKP) + 0xB0U) /*!< BKP data register 38 */
|
|
||||||
#define BKP_DATA39 REG16((BKP) + 0xB4U) /*!< BKP data register 39 */
|
|
||||||
#define BKP_DATA40 REG16((BKP) + 0xB8U) /*!< BKP data register 40 */
|
|
||||||
#define BKP_DATA41 REG16((BKP) + 0xBCU) /*!< BKP data register 41 */
|
|
||||||
#define BKP_OCTL REG16((BKP) + 0x2CU) /*!< RTC signal output control register */
|
|
||||||
#define BKP_TPCTL REG16((BKP) + 0x30U) /*!< tamper pin control register */
|
|
||||||
#define BKP_TPCS REG16((BKP) + 0x34U) /*!< tamper control and status register */
|
|
||||||
|
|
||||||
/* bits definitions */
|
|
||||||
/* BKP_DATA */
|
|
||||||
#define BKP_DATA BITS(0,15) /*!< backup data */
|
|
||||||
|
|
||||||
/* BKP_OCTL */
|
|
||||||
#define BKP_OCTL_RCCV BITS(0,6) /*!< RTC clock calibration value */
|
|
||||||
#define BKP_OCTL_COEN BIT(7) /*!< RTC clock calibration output enable */
|
|
||||||
#define BKP_OCTL_ASOEN BIT(8) /*!< RTC alarm or second signal output enable */
|
|
||||||
#define BKP_OCTL_ROSEL BIT(9) /*!< RTC output selection */
|
|
||||||
|
|
||||||
/* BKP_TPCTL */
|
|
||||||
#define BKP_TPCTL_TPEN BIT(0) /*!< tamper detection enable */
|
|
||||||
#define BKP_TPCTL_TPAL BIT(1) /*!< tamper pin active level */
|
|
||||||
|
|
||||||
/* BKP_TPCS */
|
|
||||||
#define BKP_TPCS_TER BIT(0) /*!< tamper event reset */
|
|
||||||
#define BKP_TPCS_TIR BIT(1) /*!< tamper interrupt reset */
|
|
||||||
#define BKP_TPCS_TPIE BIT(2) /*!< tamper interrupt enable */
|
|
||||||
#define BKP_TPCS_TEF BIT(8) /*!< tamper event flag */
|
|
||||||
#define BKP_TPCS_TIF BIT(9) /*!< tamper interrupt flag */
|
|
||||||
|
|
||||||
/* constants definitions */
|
|
||||||
/* BKP data register number */
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
BKP_DATA_0 = 1, /*!< BKP data register 0 */
|
|
||||||
BKP_DATA_1, /*!< BKP data register 1 */
|
|
||||||
BKP_DATA_2, /*!< BKP data register 2 */
|
|
||||||
BKP_DATA_3, /*!< BKP data register 3 */
|
|
||||||
BKP_DATA_4, /*!< BKP data register 4 */
|
|
||||||
BKP_DATA_5, /*!< BKP data register 5 */
|
|
||||||
BKP_DATA_6, /*!< BKP data register 6 */
|
|
||||||
BKP_DATA_7, /*!< BKP data register 7 */
|
|
||||||
BKP_DATA_8, /*!< BKP data register 8 */
|
|
||||||
BKP_DATA_9, /*!< BKP data register 9 */
|
|
||||||
BKP_DATA_10, /*!< BKP data register 10 */
|
|
||||||
BKP_DATA_11, /*!< BKP data register 11 */
|
|
||||||
BKP_DATA_12, /*!< BKP data register 12 */
|
|
||||||
BKP_DATA_13, /*!< BKP data register 13 */
|
|
||||||
BKP_DATA_14, /*!< BKP data register 14 */
|
|
||||||
BKP_DATA_15, /*!< BKP data register 15 */
|
|
||||||
BKP_DATA_16, /*!< BKP data register 16 */
|
|
||||||
BKP_DATA_17, /*!< BKP data register 17 */
|
|
||||||
BKP_DATA_18, /*!< BKP data register 18 */
|
|
||||||
BKP_DATA_19, /*!< BKP data register 19 */
|
|
||||||
BKP_DATA_20, /*!< BKP data register 20 */
|
|
||||||
BKP_DATA_21, /*!< BKP data register 21 */
|
|
||||||
BKP_DATA_22, /*!< BKP data register 22 */
|
|
||||||
BKP_DATA_23, /*!< BKP data register 23 */
|
|
||||||
BKP_DATA_24, /*!< BKP data register 24 */
|
|
||||||
BKP_DATA_25, /*!< BKP data register 25 */
|
|
||||||
BKP_DATA_26, /*!< BKP data register 26 */
|
|
||||||
BKP_DATA_27, /*!< BKP data register 27 */
|
|
||||||
BKP_DATA_28, /*!< BKP data register 28 */
|
|
||||||
BKP_DATA_29, /*!< BKP data register 29 */
|
|
||||||
BKP_DATA_30, /*!< BKP data register 30 */
|
|
||||||
BKP_DATA_31, /*!< BKP data register 31 */
|
|
||||||
BKP_DATA_32, /*!< BKP data register 32 */
|
|
||||||
BKP_DATA_33, /*!< BKP data register 33 */
|
|
||||||
BKP_DATA_34, /*!< BKP data register 34 */
|
|
||||||
BKP_DATA_35, /*!< BKP data register 35 */
|
|
||||||
BKP_DATA_36, /*!< BKP data register 36 */
|
|
||||||
BKP_DATA_37, /*!< BKP data register 37 */
|
|
||||||
BKP_DATA_38, /*!< BKP data register 38 */
|
|
||||||
BKP_DATA_39, /*!< BKP data register 39 */
|
|
||||||
BKP_DATA_40, /*!< BKP data register 40 */
|
|
||||||
BKP_DATA_41, /*!< BKP data register 41 */
|
|
||||||
}bkp_data_register_enum;
|
|
||||||
|
|
||||||
/* BKP register */
|
|
||||||
#define BKP_DATA0_9(number) REG16((BKP) + 0x04U + (number) * 0x04U)
|
|
||||||
#define BKP_DATA10_41(number) REG16((BKP) + 0x40U + ((number)-10U) * 0x04U)
|
|
||||||
|
|
||||||
/* get data of BKP data register */
|
|
||||||
#define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15)
|
|
||||||
|
|
||||||
/* RTC clock calibration value */
|
|
||||||
#define OCTL_RCCV(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
|
|
||||||
|
|
||||||
/* RTC output selection */
|
|
||||||
#define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U) /*!< RTC alarm pulse is selected as the RTC output */
|
|
||||||
#define RTC_OUTPUT_SECOND_PULSE ((uint16_t)0x0200U) /*!< RTC second pulse is selected as the RTC output */
|
|
||||||
|
|
||||||
/* tamper pin active level */
|
|
||||||
#define TAMPER_PIN_ACTIVE_HIGH ((uint16_t)0x0000U) /*!< the tamper pin is active high */
|
|
||||||
#define TAMPER_PIN_ACTIVE_LOW ((uint16_t)0x0002U) /*!< the tamper pin is active low */
|
|
||||||
|
|
||||||
/* tamper flag */
|
|
||||||
#define BKP_FLAG_TAMPER BKP_TPCS_TEF /*!< tamper event flag */
|
|
||||||
|
|
||||||
/* tamper interrupt flag */
|
|
||||||
#define BKP_INT_FLAG_TAMPER BKP_TPCS_TIF /*!< tamper interrupt flag */
|
|
||||||
|
|
||||||
/* function declarations */
|
|
||||||
/* reset BKP registers */
|
|
||||||
void bkp_deinit(void);
|
|
||||||
/* write BKP data register */
|
|
||||||
void bkp_data_write(bkp_data_register_enum register_number, uint16_t data);
|
|
||||||
/* read BKP data register */
|
|
||||||
uint16_t bkp_data_read(bkp_data_register_enum register_number);
|
|
||||||
|
|
||||||
/* RTC related functions */
|
|
||||||
/* enable RTC clock calibration output */
|
|
||||||
void bkp_rtc_calibration_output_enable(void);
|
|
||||||
/* disable RTC clock calibration output */
|
|
||||||
void bkp_rtc_calibration_output_disable(void);
|
|
||||||
/* enable RTC alarm or second signal output */
|
|
||||||
void bkp_rtc_signal_output_enable(void);
|
|
||||||
/* disable RTC alarm or second signal output */
|
|
||||||
void bkp_rtc_signal_output_disable(void);
|
|
||||||
/* select RTC output */
|
|
||||||
void bkp_rtc_output_select(uint16_t outputsel);
|
|
||||||
/* set RTC clock calibration value */
|
|
||||||
void bkp_rtc_calibration_value_set(uint8_t value);
|
|
||||||
|
|
||||||
/* tamper pin related functions */
|
|
||||||
/* enable tamper pin detection */
|
|
||||||
void bkp_tamper_detection_enable(void);
|
|
||||||
/* disable tamper pin detection */
|
|
||||||
void bkp_tamper_detection_disable(void);
|
|
||||||
/* set tamper pin active level */
|
|
||||||
void bkp_tamper_active_level_set(uint16_t level);
|
|
||||||
|
|
||||||
/* interrupt & flag functions */
|
|
||||||
/* enable tamper interrupt */
|
|
||||||
void bkp_interrupt_enable(void);
|
|
||||||
/* disable tamper interrupt */
|
|
||||||
void bkp_interrupt_disable(void);
|
|
||||||
/* get tamper flag state */
|
|
||||||
FlagStatus bkp_flag_get(void);
|
|
||||||
/* clear tamper flag state */
|
|
||||||
void bkp_flag_clear(void);
|
|
||||||
/* get tamper interrupt flag state */
|
|
||||||
FlagStatus bkp_interrupt_flag_get(void);
|
|
||||||
/* clear tamper interrupt flag state */
|
|
||||||
void bkp_interrupt_flag_clear(void);
|
|
||||||
|
|
||||||
#endif /* GD32VF103_BKP_H */
|
|
||||||
|
|
@ -1,720 +0,0 @@
|
||||||
/*!
|
|
||||||
\file gd32vf103_can.h
|
|
||||||
\brief definitions for the CAN
|
|
||||||
|
|
||||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef GD32VF103_CAN_H
|
|
||||||
#define GD32VF103_CAN_H
|
|
||||||
|
|
||||||
#include "gd32vf103.h"
|
|
||||||
#include "gd32vf103_rcu.h"
|
|
||||||
#include "gd32vf103_dbg.h"
|
|
||||||
|
|
||||||
/* CAN definitions */
|
|
||||||
#define CAN0 CAN_BASE /*!< CAN0 base address */
|
|
||||||
#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */
|
|
||||||
|
|
||||||
|
|
||||||
/* registers definitions */
|
|
||||||
#define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register */
|
|
||||||
#define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */
|
|
||||||
#define CAN_TSTAT(canx) REG32((canx) + 0x08U) /*!< CAN transmit status register*/
|
|
||||||
#define CAN_RFIFO0(canx) REG32((canx) + 0x0CU) /*!< CAN receive FIFO0 register */
|
|
||||||
#define CAN_RFIFO1(canx) REG32((canx) + 0x10U) /*!< CAN receive FIFO1 register */
|
|
||||||
#define CAN_INTEN(canx) REG32((canx) + 0x14U) /*!< CAN interrupt enable register */
|
|
||||||
#define CAN_ERR(canx) REG32((canx) + 0x18U) /*!< CAN error register */
|
|
||||||
#define CAN_BT(canx) REG32((canx) + 0x1CU) /*!< CAN bit timing register */
|
|
||||||
#define CAN_TMI0(canx) REG32((canx) + 0x180U) /*!< CAN transmit mailbox0 identifier register */
|
|
||||||
#define CAN_TMP0(canx) REG32((canx) + 0x184U) /*!< CAN transmit mailbox0 property register */
|
|
||||||
#define CAN_TMDATA00(canx) REG32((canx) + 0x188U) /*!< CAN transmit mailbox0 data0 register */
|
|
||||||
#define CAN_TMDATA10(canx) REG32((canx) + 0x18CU) /*!< CAN transmit mailbox0 data1 register */
|
|
||||||
#define CAN_TMI1(canx) REG32((canx) + 0x190U) /*!< CAN transmit mailbox1 identifier register */
|
|
||||||
#define CAN_TMP1(canx) REG32((canx) + 0x194U) /*!< CAN transmit mailbox1 property register */
|
|
||||||
#define CAN_TMDATA01(canx) REG32((canx) + 0x198U) /*!< CAN transmit mailbox1 data0 register */
|
|
||||||
#define CAN_TMDATA11(canx) REG32((canx) + 0x19CU) /*!< CAN transmit mailbox1 data1 register */
|
|
||||||
#define CAN_TMI2(canx) REG32((canx) + 0x1A0U) /*!< CAN transmit mailbox2 identifier register */
|
|
||||||
#define CAN_TMP2(canx) REG32((canx) + 0x1A4U) /*!< CAN transmit mailbox2 property register */
|
|
||||||
#define CAN_TMDATA02(canx) REG32((canx) + 0x1A8U) /*!< CAN transmit mailbox2 data0 register */
|
|
||||||
#define CAN_TMDATA12(canx) REG32((canx) + 0x1ACU) /*!< CAN transmit mailbox2 data1 register */
|
|
||||||
#define CAN_RFIFOMI0(canx) REG32((canx) + 0x1B0U) /*!< CAN receive FIFO0 mailbox identifier register */
|
|
||||||
#define CAN_RFIFOMP0(canx) REG32((canx) + 0x1B4U) /*!< CAN receive FIFO0 mailbox property register */
|
|
||||||
#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x1B8U) /*!< CAN receive FIFO0 mailbox data0 register */
|
|
||||||
#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1BCU) /*!< CAN receive FIFO0 mailbox data1 register */
|
|
||||||
#define CAN_RFIFOMI1(canx) REG32((canx) + 0x1C0U) /*!< CAN receive FIFO1 mailbox identifier register */
|
|
||||||
#define CAN_RFIFOMP1(canx) REG32((canx) + 0x1C4U) /*!< CAN receive FIFO1 mailbox property register */
|
|
||||||
#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x1C8U) /*!< CAN receive FIFO1 mailbox data0 register */
|
|
||||||
#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO1 mailbox data1 register */
|
|
||||||
#define CAN_FCTL(canx) REG32((canx) + 0x200U) /*!< CAN filter control register */
|
|
||||||
#define CAN_FMCFG(canx) REG32((canx) + 0x204U) /*!< CAN filter mode register */
|
|
||||||
#define CAN_FSCFG(canx) REG32((canx) + 0x20CU) /*!< CAN filter scale register */
|
|
||||||
#define CAN_FAFIFO(canx) REG32((canx) + 0x214U) /*!< CAN filter associated FIFO register */
|
|
||||||
#define CAN_FW(canx) REG32((canx) + 0x21CU) /*!< CAN filter working register */
|
|
||||||
#define CAN_F0DATA0(canx) REG32((canx) + 0x240U) /*!< CAN filter 0 data 0 register */
|
|
||||||
#define CAN_F1DATA0(canx) REG32((canx) + 0x248U) /*!< CAN filter 1 data 0 register */
|
|
||||||
#define CAN_F2DATA0(canx) REG32((canx) + 0x250U) /*!< CAN filter 2 data 0 register */
|
|
||||||
#define CAN_F3DATA0(canx) REG32((canx) + 0x258U) /*!< CAN filter 3 data 0 register */
|
|
||||||
#define CAN_F4DATA0(canx) REG32((canx) + 0x260U) /*!< CAN filter 4 data 0 register */
|
|
||||||
#define CAN_F5DATA0(canx) REG32((canx) + 0x268U) /*!< CAN filter 5 data 0 register */
|
|
||||||
#define CAN_F6DATA0(canx) REG32((canx) + 0x270U) /*!< CAN filter 6 data 0 register */
|
|
||||||
#define CAN_F7DATA0(canx) REG32((canx) + 0x278U) /*!< CAN filter 7 data 0 register */
|
|
||||||
#define CAN_F8DATA0(canx) REG32((canx) + 0x280U) /*!< CAN filter 8 data 0 register */
|
|
||||||
#define CAN_F9DATA0(canx) REG32((canx) + 0x288U) /*!< CAN filter 9 data 0 register */
|
|
||||||
#define CAN_F10DATA0(canx) REG32((canx) + 0x290U) /*!< CAN filter 10 data 0 register */
|
|
||||||
#define CAN_F11DATA0(canx) REG32((canx) + 0x298U) /*!< CAN filter 11 data 0 register */
|
|
||||||
#define CAN_F12DATA0(canx) REG32((canx) + 0x2A0U) /*!< CAN filter 12 data 0 register */
|
|
||||||
#define CAN_F13DATA0(canx) REG32((canx) + 0x2A8U) /*!< CAN filter 13 data 0 register */
|
|
||||||
#define CAN_F14DATA0(canx) REG32((canx) + 0x2B0U) /*!< CAN filter 14 data 0 register */
|
|
||||||
#define CAN_F15DATA0(canx) REG32((canx) + 0x2B8U) /*!< CAN filter 15 data 0 register */
|
|
||||||
#define CAN_F16DATA0(canx) REG32((canx) + 0x2C0U) /*!< CAN filter 16 data 0 register */
|
|
||||||
#define CAN_F17DATA0(canx) REG32((canx) + 0x2C8U) /*!< CAN filter 17 data 0 register */
|
|
||||||
#define CAN_F18DATA0(canx) REG32((canx) + 0x2D0U) /*!< CAN filter 18 data 0 register */
|
|
||||||
#define CAN_F19DATA0(canx) REG32((canx) + 0x2D8U) /*!< CAN filter 19 data 0 register */
|
|
||||||
#define CAN_F20DATA0(canx) REG32((canx) + 0x2E0U) /*!< CAN filter 20 data 0 register */
|
|
||||||
#define CAN_F21DATA0(canx) REG32((canx) + 0x2E8U) /*!< CAN filter 21 data 0 register */
|
|
||||||
#define CAN_F22DATA0(canx) REG32((canx) + 0x2F0U) /*!< CAN filter 22 data 0 register */
|
|
||||||
#define CAN_F23DATA0(canx) REG32((canx) + 0x3F8U) /*!< CAN filter 23 data 0 register */
|
|
||||||
#define CAN_F24DATA0(canx) REG32((canx) + 0x300U) /*!< CAN filter 24 data 0 register */
|
|
||||||
#define CAN_F25DATA0(canx) REG32((canx) + 0x308U) /*!< CAN filter 25 data 0 register */
|
|
||||||
#define CAN_F26DATA0(canx) REG32((canx) + 0x310U) /*!< CAN filter 26 data 0 register */
|
|
||||||
#define CAN_F27DATA0(canx) REG32((canx) + 0x318U) /*!< CAN filter 27 data 0 register */
|
|
||||||
#define CAN_F0DATA1(canx) REG32((canx) + 0x244U) /*!< CAN filter 0 data 1 register */
|
|
||||||
#define CAN_F1DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 1 data 1 register */
|
|
||||||
#define CAN_F2DATA1(canx) REG32((canx) + 0x254U) /*!< CAN filter 2 data 1 register */
|
|
||||||
#define CAN_F3DATA1(canx) REG32((canx) + 0x25CU) /*!< CAN filter 3 data 1 register */
|
|
||||||
#define CAN_F4DATA1(canx) REG32((canx) + 0x264U) /*!< CAN filter 4 data 1 register */
|
|
||||||
#define CAN_F5DATA1(canx) REG32((canx) + 0x26CU) /*!< CAN filter 5 data 1 register */
|
|
||||||
#define CAN_F6DATA1(canx) REG32((canx) + 0x274U) /*!< CAN filter 6 data 1 register */
|
|
||||||
#define CAN_F7DATA1(canx) REG32((canx) + 0x27CU) /*!< CAN filter 7 data 1 register */
|
|
||||||
#define CAN_F8DATA1(canx) REG32((canx) + 0x284U) /*!< CAN filter 8 data 1 register */
|
|
||||||
#define CAN_F9DATA1(canx) REG32((canx) + 0x28CU) /*!< CAN filter 9 data 1 register */
|
|
||||||
#define CAN_F10DATA1(canx) REG32((canx) + 0x294U) /*!< CAN filter 10 data 1 register */
|
|
||||||
#define CAN_F11DATA1(canx) REG32((canx) + 0x29CU) /*!< CAN filter 11 data 1 register */
|
|
||||||
#define CAN_F12DATA1(canx) REG32((canx) + 0x2A4U) /*!< CAN filter 12 data 1 register */
|
|
||||||
#define CAN_F13DATA1(canx) REG32((canx) + 0x2ACU) /*!< CAN filter 13 data 1 register */
|
|
||||||
#define CAN_F14DATA1(canx) REG32((canx) + 0x2B4U) /*!< CAN filter 14 data 1 register */
|
|
||||||
#define CAN_F15DATA1(canx) REG32((canx) + 0x2BCU) /*!< CAN filter 15 data 1 register */
|
|
||||||
#define CAN_F16DATA1(canx) REG32((canx) + 0x2C4U) /*!< CAN filter 16 data 1 register */
|
|
||||||
#define CAN_F17DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 17 data 1 register */
|
|
||||||
#define CAN_F18DATA1(canx) REG32((canx) + 0x2D4U) /*!< CAN filter 18 data 1 register */
|
|
||||||
#define CAN_F19DATA1(canx) REG32((canx) + 0x2DCU) /*!< CAN filter 19 data 1 register */
|
|
||||||
#define CAN_F20DATA1(canx) REG32((canx) + 0x2E4U) /*!< CAN filter 20 data 1 register */
|
|
||||||
#define CAN_F21DATA1(canx) REG32((canx) + 0x2ECU) /*!< CAN filter 21 data 1 register */
|
|
||||||
#define CAN_F22DATA1(canx) REG32((canx) + 0x2F4U) /*!< CAN filter 22 data 1 register */
|
|
||||||
#define CAN_F23DATA1(canx) REG32((canx) + 0x2FCU) /*!< CAN filter 23 data 1 register */
|
|
||||||
#define CAN_F24DATA1(canx) REG32((canx) + 0x304U) /*!< CAN filter 24 data 1 register */
|
|
||||||
#define CAN_F25DATA1(canx) REG32((canx) + 0x30CU) /*!< CAN filter 25 data 1 register */
|
|
||||||
#define CAN_F26DATA1(canx) REG32((canx) + 0x314U) /*!< CAN filter 26 data 1 register */
|
|
||||||
#define CAN_F27DATA1(canx) REG32((canx) + 0x31CU) /*!< CAN filter 27 data 1 register */
|
|
||||||
|
|
||||||
/* CAN transmit mailbox bank */
|
|
||||||
#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */
|
|
||||||
#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */
|
|
||||||
#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */
|
|
||||||
#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */
|
|
||||||
|
|
||||||
/* CAN filter bank */
|
|
||||||
#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */
|
|
||||||
#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */
|
|
||||||
|
|
||||||
/* CAN receive fifo mailbox bank */
|
|
||||||
#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */
|
|
||||||
#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */
|
|
||||||
#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */
|
|
||||||
#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */
|
|
||||||
|
|
||||||
/* bits definitions */
|
|
||||||
/* CAN_CTL */
|
|
||||||
#define CAN_CTL_IWMOD BIT(0) /*!< initial working mode */
|
|
||||||
#define CAN_CTL_SLPWMOD BIT(1) /*!< sleep working mode */
|
|
||||||
#define CAN_CTL_TFO BIT(2) /*!< transmit FIFO order */
|
|
||||||
#define CAN_CTL_RFOD BIT(3) /*!< receive FIFO overwrite disable */
|
|
||||||
#define CAN_CTL_ARD BIT(4) /*!< automatic retransmission disable */
|
|
||||||
#define CAN_CTL_AWU BIT(5) /*!< automatic wakeup */
|
|
||||||
#define CAN_CTL_ABOR BIT(6) /*!< automatic bus-off recovery */
|
|
||||||
#define CAN_CTL_TTC BIT(7) /*!< time triggered communication */
|
|
||||||
#define CAN_CTL_SWRST BIT(15) /*!< CAN software reset */
|
|
||||||
#define CAN_CTL_DFZ BIT(16) /*!< CAN debug freeze */
|
|
||||||
|
|
||||||
/* CAN_STAT */
|
|
||||||
#define CAN_STAT_IWS BIT(0) /*!< initial working state */
|
|
||||||
#define CAN_STAT_SLPWS BIT(1) /*!< sleep working state */
|
|
||||||
#define CAN_STAT_ERRIF BIT(2) /*!< error interrupt flag*/
|
|
||||||
#define CAN_STAT_WUIF BIT(3) /*!< status change interrupt flag of wakeup from sleep working mode */
|
|
||||||
#define CAN_STAT_SLPIF BIT(4) /*!< status change interrupt flag of sleep working mode entering */
|
|
||||||
#define CAN_STAT_TS BIT(8) /*!< transmitting state */
|
|
||||||
#define CAN_STAT_RS BIT(9) /*!< receiving state */
|
|
||||||
#define CAN_STAT_LASTRX BIT(10) /*!< last sample value of rx pin */
|
|
||||||
#define CAN_STAT_RXL BIT(11) /*!< CAN rx signal */
|
|
||||||
|
|
||||||
/* CAN_TSTAT */
|
|
||||||
#define CAN_TSTAT_MTF0 BIT(0) /*!< mailbox0 transmit finished */
|
|
||||||
#define CAN_TSTAT_MTFNERR0 BIT(1) /*!< mailbox0 transmit finished and no error */
|
|
||||||
#define CAN_TSTAT_MAL0 BIT(2) /*!< mailbox0 arbitration lost */
|
|
||||||
#define CAN_TSTAT_MTE0 BIT(3) /*!< mailbox0 transmit error */
|
|
||||||
#define CAN_TSTAT_MST0 BIT(7) /*!< mailbox0 stop transmitting */
|
|
||||||
#define CAN_TSTAT_MTF1 BIT(8) /*!< mailbox1 transmit finished */
|
|
||||||
#define CAN_TSTAT_MTFNERR1 BIT(9) /*!< mailbox1 transmit finished and no error */
|
|
||||||
#define CAN_TSTAT_MAL1 BIT(10) /*!< mailbox1 arbitration lost */
|
|
||||||
#define CAN_TSTAT_MTE1 BIT(11) /*!< mailbox1 transmit error */
|
|
||||||
#define CAN_TSTAT_MST1 BIT(15) /*!< mailbox1 stop transmitting */
|
|
||||||
#define CAN_TSTAT_MTF2 BIT(16) /*!< mailbox2 transmit finished */
|
|
||||||
#define CAN_TSTAT_MTFNERR2 BIT(17) /*!< mailbox2 transmit finished and no error */
|
|
||||||
#define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */
|
|
||||||
#define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */
|
|
||||||
#define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */
|
|
||||||
#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */
|
|
||||||
#define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */
|
|
||||||
#define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */
|
|
||||||
#define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */
|
|
||||||
#define CAN_TSTAT_TMLS0 BIT(29) /*!< last sending priority flag for mailbox0 */
|
|
||||||
#define CAN_TSTAT_TMLS1 BIT(30) /*!< last sending priority flag for mailbox1 */
|
|
||||||
#define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */
|
|
||||||
|
|
||||||
/* CAN_RFIFO0 */
|
|
||||||
#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */
|
|
||||||
#define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */
|
|
||||||
#define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */
|
|
||||||
#define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */
|
|
||||||
|
|
||||||
/* CAN_RFIFO1 */
|
|
||||||
#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */
|
|
||||||
#define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */
|
|
||||||
#define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */
|
|
||||||
#define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */
|
|
||||||
|
|
||||||
/* CAN_INTEN */
|
|
||||||
#define CAN_INTEN_TMEIE BIT(0) /*!< transmit mailbox empty interrupt enable */
|
|
||||||
#define CAN_INTEN_RFNEIE0 BIT(1) /*!< receive FIFO0 not empty interrupt enable */
|
|
||||||
#define CAN_INTEN_RFFIE0 BIT(2) /*!< receive FIFO0 full interrupt enable */
|
|
||||||
#define CAN_INTEN_RFOIE0 BIT(3) /*!< receive FIFO0 overfull interrupt enable */
|
|
||||||
#define CAN_INTEN_RFNEIE1 BIT(4) /*!< receive FIFO1 not empty interrupt enable */
|
|
||||||
#define CAN_INTEN_RFFIE1 BIT(5) /*!< receive FIFO1 full interrupt enable */
|
|
||||||
#define CAN_INTEN_RFOIE1 BIT(6) /*!< receive FIFO1 overfull interrupt enable */
|
|
||||||
#define CAN_INTEN_WERRIE BIT(8) /*!< warning error interrupt enable */
|
|
||||||
#define CAN_INTEN_PERRIE BIT(9) /*!< passive error interrupt enable */
|
|
||||||
#define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */
|
|
||||||
#define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */
|
|
||||||
#define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */
|
|
||||||
#define CAN_INTEN_WIE BIT(16) /*!< wakeup interrupt enable */
|
|
||||||
#define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */
|
|
||||||
|
|
||||||
/* CAN_ERR */
|
|
||||||
#define CAN_ERR_WERR BIT(0) /*!< warning error */
|
|
||||||
#define CAN_ERR_PERR BIT(1) /*!< passive error */
|
|
||||||
#define CAN_ERR_BOERR BIT(2) /*!< bus-off error */
|
|
||||||
#define CAN_ERR_ERRN BITS(4,6) /*!< error number */
|
|
||||||
#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */
|
|
||||||
#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */
|
|
||||||
|
|
||||||
/* CAN_BT */
|
|
||||||
#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */
|
|
||||||
#define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */
|
|
||||||
#define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */
|
|
||||||
#define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */
|
|
||||||
#define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */
|
|
||||||
#define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */
|
|
||||||
|
|
||||||
/* CAN_TMIx */
|
|
||||||
#define CAN_TMI_TEN BIT(0) /*!< transmit enable */
|
|
||||||
#define CAN_TMI_FT BIT(1) /*!< frame type */
|
|
||||||
#define CAN_TMI_FF BIT(2) /*!< frame format */
|
|
||||||
#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */
|
|
||||||
#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */
|
|
||||||
|
|
||||||
/* CAN_TMPx */
|
|
||||||
#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */
|
|
||||||
#define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */
|
|
||||||
#define CAN_TMP_TS BITS(16,31) /*!< time stamp */
|
|
||||||
|
|
||||||
/* CAN_TMDATA0x */
|
|
||||||
#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */
|
|
||||||
#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */
|
|
||||||
#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */
|
|
||||||
#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */
|
|
||||||
|
|
||||||
/* CAN_TMDATA1x */
|
|
||||||
#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */
|
|
||||||
#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */
|
|
||||||
#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */
|
|
||||||
#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */
|
|
||||||
|
|
||||||
/* CAN_RFIFOMIx */
|
|
||||||
#define CAN_RFIFOMI_FT BIT(1) /*!< frame type */
|
|
||||||
#define CAN_RFIFOMI_FF BIT(2) /*!< frame format */
|
|
||||||
#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */
|
|
||||||
#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */
|
|
||||||
|
|
||||||
/* CAN_RFIFOMPx */
|
|
||||||
#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */
|
|
||||||
#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */
|
|
||||||
#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */
|
|
||||||
|
|
||||||
/* CAN_RFIFOMDATA0x */
|
|
||||||
#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */
|
|
||||||
#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */
|
|
||||||
#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */
|
|
||||||
#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */
|
|
||||||
|
|
||||||
/* CAN_RFIFOMDATA1x */
|
|
||||||
#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */
|
|
||||||
#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */
|
|
||||||
#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */
|
|
||||||
#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */
|
|
||||||
|
|
||||||
/* CAN_FCTL */
|
|
||||||
#define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */
|
|
||||||
#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */
|
|
||||||
|
|
||||||
/* CAN_FMCFG */
|
|
||||||
#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/
|
|
||||||
|
|
||||||
/* CAN_FSCFG */
|
|
||||||
#define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits*/
|
|
||||||
|
|
||||||
/* CAN_FAFIFO */
|
|
||||||
#define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */
|
|
||||||
|
|
||||||
/* CAN_FW */
|
|
||||||
#define CAN_FW_FW(regval) BIT(regval) /*!< filter working */
|
|
||||||
|
|
||||||
/* CAN_FxDATAy */
|
|
||||||
#define CAN_FDATA_FD(regval) BIT(regval) /*!< filter data */
|
|
||||||
|
|
||||||
/* consts definitions */
|
|
||||||
/* define the CAN bit position and its register index offset */
|
|
||||||
#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
|
|
||||||
#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6)))
|
|
||||||
#define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
|
|
||||||
|
|
||||||
#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1))
|
|
||||||
#define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12)))
|
|
||||||
#define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU)
|
|
||||||
#define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU)
|
|
||||||
|
|
||||||
/* register offset */
|
|
||||||
#define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */
|
|
||||||
#define TSTAT_REG_OFFSET ((uint8_t)0x08U) /*!< TSTAT register offset */
|
|
||||||
#define RFIFO0_REG_OFFSET ((uint8_t)0x0CU) /*!< RFIFO0 register offset */
|
|
||||||
#define RFIFO1_REG_OFFSET ((uint8_t)0x10U) /*!< RFIFO1 register offset */
|
|
||||||
#define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */
|
|
||||||
|
|
||||||
/* CAN flags */
|
|
||||||
typedef enum {
|
|
||||||
/* flags in TSTAT register */
|
|
||||||
CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */
|
|
||||||
CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */
|
|
||||||
CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */
|
|
||||||
CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */
|
|
||||||
CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */
|
|
||||||
CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */
|
|
||||||
/* flags in RFIFO0 register */
|
|
||||||
CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */
|
|
||||||
CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */
|
|
||||||
/* flags in RFIFO1 register */
|
|
||||||
CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */
|
|
||||||
CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */
|
|
||||||
/* flags in ERR register */
|
|
||||||
CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */
|
|
||||||
CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */
|
|
||||||
CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */
|
|
||||||
} can_flag_enum;
|
|
||||||
|
|
||||||
/* CAN interrupt flags */
|
|
||||||
typedef enum {
|
|
||||||
/* interrupt flags in STAT register */
|
|
||||||
CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */
|
|
||||||
CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */
|
|
||||||
CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */
|
|
||||||
/* interrupt flags in TSTAT register */
|
|
||||||
CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */
|
|
||||||
CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */
|
|
||||||
CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */
|
|
||||||
/* interrupt flags in RFIFO0 register */
|
|
||||||
CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */
|
|
||||||
CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */
|
|
||||||
/* interrupt flags in RFIFO0 register */
|
|
||||||
CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */
|
|
||||||
CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */
|
|
||||||
} can_interrupt_flag_enum;
|
|
||||||
|
|
||||||
/* CAN initiliaze parameters struct */
|
|
||||||
typedef struct {
|
|
||||||
uint8_t working_mode; /*!< CAN working mode */
|
|
||||||
uint8_t resync_jump_width; /*!< CAN resynchronization jump width */
|
|
||||||
uint8_t time_segment_1; /*!< time segment 1 */
|
|
||||||
uint8_t time_segment_2; /*!< time segment 2 */
|
|
||||||
ControlStatus time_triggered; /*!< time triggered communication mode */
|
|
||||||
ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */
|
|
||||||
ControlStatus auto_wake_up; /*!< automatic wake-up mode */
|
|
||||||
ControlStatus no_auto_retrans; /*!< automatic retransmission mode disable */
|
|
||||||
ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */
|
|
||||||
ControlStatus trans_fifo_order; /*!< transmit FIFO order */
|
|
||||||
uint16_t prescaler; /*!< baudrate prescaler */
|
|
||||||
} can_parameter_struct;
|
|
||||||
|
|
||||||
/* CAN transmit message struct */
|
|
||||||
typedef struct {
|
|
||||||
uint32_t tx_sfid; /*!< standard format frame identifier */
|
|
||||||
uint32_t tx_efid; /*!< extended format frame identifier */
|
|
||||||
uint8_t tx_ff; /*!< format of frame, standard or extended format */
|
|
||||||
uint8_t tx_ft; /*!< type of frame, data or remote */
|
|
||||||
uint8_t tx_dlen; /*!< data length */
|
|
||||||
uint8_t tx_data[8]; /*!< transmit data */
|
|
||||||
} can_trasnmit_message_struct;
|
|
||||||
|
|
||||||
/* CAN receive message struct */
|
|
||||||
typedef struct {
|
|
||||||
uint32_t rx_sfid; /*!< standard format frame identifier */
|
|
||||||
uint32_t rx_efid; /*!< extended format frame identifier */
|
|
||||||
uint8_t rx_ff; /*!< format of frame, standard or extended format */
|
|
||||||
uint8_t rx_ft; /*!< type of frame, data or remote */
|
|
||||||
uint8_t rx_dlen; /*!< data length */
|
|
||||||
uint8_t rx_data[8]; /*!< receive data */
|
|
||||||
uint8_t rx_fi; /*!< filtering index */
|
|
||||||
} can_receive_message_struct;
|
|
||||||
|
|
||||||
/* CAN filter parameters struct */
|
|
||||||
typedef struct {
|
|
||||||
uint16_t filter_list_high; /*!< filter list number high bits*/
|
|
||||||
uint16_t filter_list_low; /*!< filter list number low bits */
|
|
||||||
uint16_t filter_mask_high; /*!< filter mask number high bits */
|
|
||||||
uint16_t filter_mask_low; /*!< filter mask number low bits */
|
|
||||||
uint16_t filter_fifo_number; /*!< receive FIFO associated with the filter */
|
|
||||||
uint16_t filter_number; /*!< filter number */
|
|
||||||
uint16_t filter_mode; /*!< filter mode, list or mask */
|
|
||||||
uint16_t filter_bits; /*!< filter scale */
|
|
||||||
ControlStatus filter_enable; /*!< filter work or not */
|
|
||||||
} can_filter_parameter_struct;
|
|
||||||
|
|
||||||
/* CAN errors */
|
|
||||||
typedef enum {
|
|
||||||
CAN_ERROR_NONE = 0, /*!< no error */
|
|
||||||
CAN_ERROR_FILL, /*!< fill error */
|
|
||||||
CAN_ERROR_FORMATE, /*!< format error */
|
|
||||||
CAN_ERROR_ACK, /*!< ACK error */
|
|
||||||
CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */
|
|
||||||
CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */
|
|
||||||
CAN_ERROR_CRC, /*!< CRC error */
|
|
||||||
CAN_ERROR_SOFTWARECFG, /*!< software configure */
|
|
||||||
} can_error_enum;
|
|
||||||
|
|
||||||
/* transmit states */
|
|
||||||
typedef enum {
|
|
||||||
CAN_TRANSMIT_FAILED = 0, /*!< CAN transmitted failure */
|
|
||||||
CAN_TRANSMIT_OK = 1, /*!< CAN transmitted success */
|
|
||||||
CAN_TRANSMIT_PENDING = 2, /*!< CAN transmitted pending */
|
|
||||||
CAN_TRANSMIT_NOMAILBOX = 4, /*!< no empty mailbox to be used for CAN */
|
|
||||||
} can_transmit_state_enum;
|
|
||||||
|
|
||||||
typedef enum {
|
|
||||||
CAN_INIT_STRUCT = 0, /* CAN initiliaze parameters struct */
|
|
||||||
CAN_FILTER_STRUCT, /* CAN filter parameters struct */
|
|
||||||
CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */
|
|
||||||
CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */
|
|
||||||
} can_struct_type_enum;
|
|
||||||
|
|
||||||
/* CAN baudrate prescaler*/
|
|
||||||
#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0))
|
|
||||||
|
|
||||||
/* CAN bit segment 1*/
|
|
||||||
#define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16))
|
|
||||||
|
|
||||||
/* CAN bit segment 2*/
|
|
||||||
#define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20))
|
|
||||||
|
|
||||||
/* CAN resynchronization jump width*/
|
|
||||||
#define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24))
|
|
||||||
|
|
||||||
/* CAN communication mode*/
|
|
||||||
#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30))
|
|
||||||
|
|
||||||
/* CAN FDATA high 16 bits */
|
|
||||||
#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16))
|
|
||||||
|
|
||||||
/* CAN FDATA low 16 bits */
|
|
||||||
#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
|
|
||||||
|
|
||||||
/* CAN1 filter start bank_number*/
|
|
||||||
#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8))
|
|
||||||
|
|
||||||
/* CAN transmit mailbox extended identifier*/
|
|
||||||
#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3))
|
|
||||||
|
|
||||||
/* CAN transmit mailbox standard identifier*/
|
|
||||||
#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21))
|
|
||||||
|
|
||||||
/* transmit data byte 0 */
|
|
||||||
#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
|
|
||||||
|
|
||||||
/* transmit data byte 1 */
|
|
||||||
#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8))
|
|
||||||
|
|
||||||
/* transmit data byte 2 */
|
|
||||||
#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16))
|
|
||||||
|
|
||||||
/* transmit data byte 3 */
|
|
||||||
#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24))
|
|
||||||
|
|
||||||
/* transmit data byte 4 */
|
|
||||||
#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
|
|
||||||
|
|
||||||
/* transmit data byte 5 */
|
|
||||||
#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8))
|
|
||||||
|
|
||||||
/* transmit data byte 6 */
|
|
||||||
#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16))
|
|
||||||
|
|
||||||
/* transmit data byte 7 */
|
|
||||||
#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24))
|
|
||||||
|
|
||||||
/* receive mailbox extended identifier*/
|
|
||||||
#define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3, 31)
|
|
||||||
|
|
||||||
/* receive mailbox standrad identifier*/
|
|
||||||
#define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21, 31)
|
|
||||||
|
|
||||||
/* receive data length */
|
|
||||||
#define GET_RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0, 3)
|
|
||||||
|
|
||||||
/* the index of the filter by which the frame is passed */
|
|
||||||
#define GET_RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8, 15)
|
|
||||||
|
|
||||||
/* receive data byte 0 */
|
|
||||||
#define GET_RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0, 7)
|
|
||||||
|
|
||||||
/* receive data byte 1 */
|
|
||||||
#define GET_RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8, 15)
|
|
||||||
|
|
||||||
/* receive data byte 2 */
|
|
||||||
#define GET_RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16, 23)
|
|
||||||
|
|
||||||
/* receive data byte 3 */
|
|
||||||
#define GET_RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24, 31)
|
|
||||||
|
|
||||||
/* receive data byte 4 */
|
|
||||||
#define GET_RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0, 7)
|
|
||||||
|
|
||||||
/* receive data byte 5 */
|
|
||||||
#define GET_RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8, 15)
|
|
||||||
|
|
||||||
/* receive data byte 6 */
|
|
||||||
#define GET_RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16, 23)
|
|
||||||
|
|
||||||
/* receive data byte 7 */
|
|
||||||
#define GET_RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24, 31)
|
|
||||||
|
|
||||||
/* error number */
|
|
||||||
#define GET_ERR_ERRN(regval) GET_BITS((uint32_t)(regval), 4, 6)
|
|
||||||
|
|
||||||
/* transmit error count */
|
|
||||||
#define GET_ERR_TECNT(regval) GET_BITS((uint32_t)(regval), 16, 23)
|
|
||||||
|
|
||||||
/* receive error count */
|
|
||||||
#define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24, 31)
|
|
||||||
|
|
||||||
/* CAN errors */
|
|
||||||
#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4))
|
|
||||||
#define CAN_ERRN_0 ERR_ERRN(0) /* no error */
|
|
||||||
#define CAN_ERRN_1 ERR_ERRN(1) /*!< fill error */
|
|
||||||
#define CAN_ERRN_2 ERR_ERRN(2) /*!< format error */
|
|
||||||
#define CAN_ERRN_3 ERR_ERRN(3) /*!< ACK error */
|
|
||||||
#define CAN_ERRN_4 ERR_ERRN(4) /*!< bit recessive error */
|
|
||||||
#define CAN_ERRN_5 ERR_ERRN(5) /*!< bit dominant error */
|
|
||||||
#define CAN_ERRN_6 ERR_ERRN(6) /*!< CRC error */
|
|
||||||
#define CAN_ERRN_7 ERR_ERRN(7) /*!< software error */
|
|
||||||
|
|
||||||
#define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */
|
|
||||||
|
|
||||||
/* CAN communication mode */
|
|
||||||
#define CAN_NORMAL_MODE ((uint8_t)0x00U) /*!< normal communication mode */
|
|
||||||
#define CAN_LOOPBACK_MODE ((uint8_t)0x01U) /*!< loopback communication mode */
|
|
||||||
#define CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */
|
|
||||||
#define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */
|
|
||||||
|
|
||||||
/* CAN resynchronisation jump width */
|
|
||||||
#define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */
|
|
||||||
#define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */
|
|
||||||
#define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */
|
|
||||||
#define CAN_BT_SJW_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */
|
|
||||||
|
|
||||||
/* CAN time segment 1 */
|
|
||||||
#define CAN_BT_BS1_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */
|
|
||||||
#define CAN_BT_BS1_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */
|
|
||||||
#define CAN_BT_BS1_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */
|
|
||||||
#define CAN_BT_BS1_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */
|
|
||||||
#define CAN_BT_BS1_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */
|
|
||||||
#define CAN_BT_BS1_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */
|
|
||||||
#define CAN_BT_BS1_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */
|
|
||||||
#define CAN_BT_BS1_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */
|
|
||||||
#define CAN_BT_BS1_9TQ ((uint8_t)0x08U) /*!< 9 time quanta */
|
|
||||||
#define CAN_BT_BS1_10TQ ((uint8_t)0x09U) /*!< 10 time quanta */
|
|
||||||
#define CAN_BT_BS1_11TQ ((uint8_t)0x0AU) /*!< 11 time quanta */
|
|
||||||
#define CAN_BT_BS1_12TQ ((uint8_t)0x0BU) /*!< 12 time quanta */
|
|
||||||
#define CAN_BT_BS1_13TQ ((uint8_t)0x0CU) /*!< 13 time quanta */
|
|
||||||
#define CAN_BT_BS1_14TQ ((uint8_t)0x0DU) /*!< 14 time quanta */
|
|
||||||
#define CAN_BT_BS1_15TQ ((uint8_t)0x0EU) /*!< 15 time quanta */
|
|
||||||
#define CAN_BT_BS1_16TQ ((uint8_t)0x0FU) /*!< 16 time quanta */
|
|
||||||
|
|
||||||
/* CAN time segment 2 */
|
|
||||||
#define CAN_BT_BS2_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */
|
|
||||||
#define CAN_BT_BS2_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */
|
|
||||||
#define CAN_BT_BS2_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */
|
|
||||||
#define CAN_BT_BS2_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */
|
|
||||||
#define CAN_BT_BS2_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */
|
|
||||||
#define CAN_BT_BS2_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */
|
|
||||||
#define CAN_BT_BS2_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */
|
|
||||||
#define CAN_BT_BS2_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */
|
|
||||||
|
|
||||||
/* CAN mailbox number */
|
|
||||||
#define CAN_MAILBOX0 ((uint8_t)0x00U) /*!< mailbox0 */
|
|
||||||
#define CAN_MAILBOX1 ((uint8_t)0x01U) /*!< mailbox1 */
|
|
||||||
#define CAN_MAILBOX2 ((uint8_t)0x02U) /*!< mailbox2 */
|
|
||||||
#define CAN_NOMAILBOX ((uint8_t)0x03U) /*!< no mailbox empty */
|
|
||||||
|
|
||||||
/* CAN frame format */
|
|
||||||
#define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */
|
|
||||||
#define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */
|
|
||||||
|
|
||||||
/* CAN receive fifo */
|
|
||||||
#define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */
|
|
||||||
#define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */
|
|
||||||
|
|
||||||
/* frame number of receive fifo */
|
|
||||||
#define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */
|
|
||||||
|
|
||||||
#define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */
|
|
||||||
#define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */
|
|
||||||
|
|
||||||
/* CAN working mode */
|
|
||||||
#define CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */
|
|
||||||
#define CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */
|
|
||||||
#define CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */
|
|
||||||
|
|
||||||
/* filter bits */
|
|
||||||
#define CAN_FILTERBITS_16BIT ((uint8_t)0x00U) /*!< CAN filter 16 bits */
|
|
||||||
#define CAN_FILTERBITS_32BIT ((uint8_t)0x01U) /*!< CAN filter 32 bits */
|
|
||||||
|
|
||||||
/* filter mode */
|
|
||||||
#define CAN_FILTERMODE_MASK ((uint8_t)0x00U) /*!< mask mode */
|
|
||||||
#define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */
|
|
||||||
|
|
||||||
/* filter 16 bits mask */
|
|
||||||
#define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) /*!< can filter 16 bits mask */
|
|
||||||
|
|
||||||
/* frame type */
|
|
||||||
#define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */
|
|
||||||
#define CAN_FT_REMOTE ((uint32_t)0x00000002U) /*!< remote frame */
|
|
||||||
|
|
||||||
/* CAN timeout */
|
|
||||||
#define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */
|
|
||||||
|
|
||||||
/* interrupt enable bits */
|
|
||||||
#define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */
|
|
||||||
#define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */
|
|
||||||
#define CAN_INT_RFF0 CAN_INTEN_RFFIE0 /*!< receive FIFO0 full interrupt enable */
|
|
||||||
#define CAN_INT_RFO0 CAN_INTEN_RFOIE0 /*!< receive FIFO0 overfull interrupt enable */
|
|
||||||
#define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1 /*!< receive FIFO1 not empty interrupt enable */
|
|
||||||
#define CAN_INT_RFF1 CAN_INTEN_RFFIE1 /*!< receive FIFO1 full interrupt enable */
|
|
||||||
#define CAN_INT_RFO1 CAN_INTEN_RFOIE1 /*!< receive FIFO1 overfull interrupt enable */
|
|
||||||
#define CAN_INT_WERR CAN_INTEN_WERRIE /*!< warning error interrupt enable */
|
|
||||||
#define CAN_INT_PERR CAN_INTEN_PERRIE /*!< passive error interrupt enable */
|
|
||||||
#define CAN_INT_BO CAN_INTEN_BOIE /*!< bus-off interrupt enable */
|
|
||||||
#define CAN_INT_ERRN CAN_INTEN_ERRNIE /*!< error number interrupt enable */
|
|
||||||
#define CAN_INT_ERR CAN_INTEN_ERRIE /*!< error interrupt enable */
|
|
||||||
#define CAN_INT_WAKEUP CAN_INTEN_WIE /*!< wakeup interrupt enable */
|
|
||||||
#define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */
|
|
||||||
|
|
||||||
/* function declarations */
|
|
||||||
/* deinitialize CAN */
|
|
||||||
void can_deinit(uint32_t can_periph);
|
|
||||||
/* initialize CAN struct */
|
|
||||||
void can_struct_para_init(can_struct_type_enum type, void* p_struct);
|
|
||||||
/* initialize CAN */
|
|
||||||
ErrStatus can_init(uint32_t can_periph,
|
|
||||||
can_parameter_struct* can_parameter_init);
|
|
||||||
/* CAN filter init */
|
|
||||||
void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init);
|
|
||||||
/* set can1 fliter start bank number */
|
|
||||||
void can1_filter_start_bank(uint8_t start_bank);
|
|
||||||
/* enable functions */
|
|
||||||
/* CAN debug freeze enable */
|
|
||||||
void can_debug_freeze_enable(uint32_t can_periph);
|
|
||||||
/* CAN debug freeze disable */
|
|
||||||
void can_debug_freeze_disable(uint32_t can_periph);
|
|
||||||
/* CAN time trigger mode enable */
|
|
||||||
void can_time_trigger_mode_enable(uint32_t can_periph);
|
|
||||||
/* CAN time trigger mode disable */
|
|
||||||
void can_time_trigger_mode_disable(uint32_t can_periph);
|
|
||||||
|
|
||||||
/* transmit functions */
|
|
||||||
/* transmit CAN message */
|
|
||||||
uint8_t can_message_transmit(uint32_t can_periph,
|
|
||||||
can_trasnmit_message_struct* transmit_message);
|
|
||||||
/* get CAN transmit state */
|
|
||||||
can_transmit_state_enum can_transmit_states(uint32_t can_periph,
|
|
||||||
uint8_t mailbox_number);
|
|
||||||
/* stop CAN transmission */
|
|
||||||
void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number);
|
|
||||||
/* CAN receive message */
|
|
||||||
void can_message_receive(uint32_t can_periph, uint8_t fifo_number,
|
|
||||||
can_receive_message_struct* receive_message);
|
|
||||||
/* CAN release fifo */
|
|
||||||
void can_fifo_release(uint32_t can_periph, uint8_t fifo_number);
|
|
||||||
/* CAN receive message length */
|
|
||||||
uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number);
|
|
||||||
/* CAN working mode */
|
|
||||||
ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode);
|
|
||||||
/* CAN wakeup from sleep mode */
|
|
||||||
ErrStatus can_wakeup(uint32_t can_periph);
|
|
||||||
|
|
||||||
/* CAN get error */
|
|
||||||
can_error_enum can_error_get(uint32_t can_periph);
|
|
||||||
/* get CAN receive error number */
|
|
||||||
uint8_t can_receive_error_number_get(uint32_t can_periph);
|
|
||||||
/* get CAN transmit error number */
|
|
||||||
uint8_t can_transmit_error_number_get(uint32_t can_periph);
|
|
||||||
|
|
||||||
/* CAN interrupt enable */
|
|
||||||
void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt);
|
|
||||||
/* CAN interrupt disable */
|
|
||||||
void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt);
|
|
||||||
/* CAN get flag state */
|
|
||||||
FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag);
|
|
||||||
/* CAN clear flag state */
|
|
||||||
void can_flag_clear(uint32_t can_periph, can_flag_enum flag);
|
|
||||||
/* CAN get interrupt flag state */
|
|
||||||
FlagStatus can_interrupt_flag_get(uint32_t can_periph,
|
|
||||||
can_interrupt_flag_enum flag);
|
|
||||||
/* CAN clear interrupt flag state */
|
|
||||||
void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag);
|
|
||||||
|
|
||||||
#endif /* GD32VF103_CAN_H */
|
|
||||||
|
|
@ -1,80 +0,0 @@
|
||||||
/*!
|
|
||||||
\file gd32vf103_crc.h
|
|
||||||
\brief definitions for the CRC
|
|
||||||
|
|
||||||
|
|
||||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef GD32VF103_CRC_H
|
|
||||||
#define GD32VF103_CRC_H
|
|
||||||
|
|
||||||
#include "gd32vf103.h"
|
|
||||||
#include "gd32vf103_rcu.h"
|
|
||||||
#include "gd32vf103_dbg.h"
|
|
||||||
|
|
||||||
/* CRC definitions */
|
|
||||||
#define CRC CRC_BASE
|
|
||||||
|
|
||||||
/* registers definitions */
|
|
||||||
#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */
|
|
||||||
#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */
|
|
||||||
#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */
|
|
||||||
|
|
||||||
/* bits definitions */
|
|
||||||
/* CRC_DATA */
|
|
||||||
#define CRC_DATA_DATA BITS(0, 31) /*!< CRC calculation result bits */
|
|
||||||
|
|
||||||
/* CRC_FDATA */
|
|
||||||
#define CRC_FDATA_FDATA BITS(0, 7) /*!< CRC free data bits */
|
|
||||||
|
|
||||||
/* CRC_CTL */
|
|
||||||
#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */
|
|
||||||
|
|
||||||
/* function declarations */
|
|
||||||
/* deinit CRC calculation unit */
|
|
||||||
void crc_deinit(void);
|
|
||||||
|
|
||||||
/* reset data register(CRC_DATA) to the value of 0xFFFFFFFF */
|
|
||||||
void crc_data_register_reset(void);
|
|
||||||
/* read the value of the data register */
|
|
||||||
uint32_t crc_data_register_read(void);
|
|
||||||
|
|
||||||
/* read the value of the free data register */
|
|
||||||
uint8_t crc_free_data_register_read(void);
|
|
||||||
/* write data to the free data register */
|
|
||||||
void crc_free_data_register_write(uint8_t free_data);
|
|
||||||
|
|
||||||
/* calculate the CRC value of a 32-bit data */
|
|
||||||
uint32_t crc_single_data_calculate(uint32_t sdata);
|
|
||||||
/* calculate the CRC value of an array of 32-bit values */
|
|
||||||
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size);
|
|
||||||
|
|
||||||
#endif /* GD32VF103_CRC_H */
|
|
||||||
|
|
@ -1,244 +0,0 @@
|
||||||
/*!
|
|
||||||
\file gd32vf103_dac.h
|
|
||||||
\brief definitions for the DAC
|
|
||||||
|
|
||||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef GD32VF103_DAC_H
|
|
||||||
#define GD32VF103_DAC_H
|
|
||||||
|
|
||||||
#include "gd32vf103.h"
|
|
||||||
#include "gd32vf103_rcu.h"
|
|
||||||
#include "gd32vf103_dbg.h"
|
|
||||||
|
|
||||||
/* DACx(x=0,1) definitions */
|
|
||||||
#define DAC DAC_BASE
|
|
||||||
#define DAC0 (0U)
|
|
||||||
#define DAC1 (1U)
|
|
||||||
|
|
||||||
/* registers definitions */
|
|
||||||
#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */
|
|
||||||
#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */
|
|
||||||
#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */
|
|
||||||
#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */
|
|
||||||
#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */
|
|
||||||
#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */
|
|
||||||
#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */
|
|
||||||
#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */
|
|
||||||
#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */
|
|
||||||
#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */
|
|
||||||
#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */
|
|
||||||
#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */
|
|
||||||
#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */
|
|
||||||
|
|
||||||
/* bits definitions */
|
|
||||||
/* DAC_CTL */
|
|
||||||
#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */
|
|
||||||
#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */
|
|
||||||
#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */
|
|
||||||
#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */
|
|
||||||
#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */
|
|
||||||
#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */
|
|
||||||
#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */
|
|
||||||
#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */
|
|
||||||
#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */
|
|
||||||
#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */
|
|
||||||
#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */
|
|
||||||
#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */
|
|
||||||
#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */
|
|
||||||
#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */
|
|
||||||
|
|
||||||
/* DAC_SWT */
|
|
||||||
#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */
|
|
||||||
#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */
|
|
||||||
|
|
||||||
/* DAC0_R12DH */
|
|
||||||
#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */
|
|
||||||
|
|
||||||
/* DAC0_L12DH */
|
|
||||||
#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */
|
|
||||||
|
|
||||||
/* DAC0_R8DH */
|
|
||||||
#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */
|
|
||||||
|
|
||||||
/* DAC1_R12DH */
|
|
||||||
#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */
|
|
||||||
|
|
||||||
/* DAC1_L12DH */
|
|
||||||
#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */
|
|
||||||
|
|
||||||
/* DAC1_R8DH */
|
|
||||||
#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */
|
|
||||||
|
|
||||||
/* DACC_R12DH */
|
|
||||||
#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */
|
|
||||||
#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */
|
|
||||||
|
|
||||||
/* DACC_L12DH */
|
|
||||||
#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */
|
|
||||||
#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */
|
|
||||||
|
|
||||||
/* DACC_R8DH */
|
|
||||||
#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */
|
|
||||||
#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */
|
|
||||||
|
|
||||||
/* DAC0_DO */
|
|
||||||
#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */
|
|
||||||
|
|
||||||
/* DAC1_DO */
|
|
||||||
#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */
|
|
||||||
|
|
||||||
/* constants definitions */
|
|
||||||
/* DAC trigger source */
|
|
||||||
#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3))
|
|
||||||
#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */
|
|
||||||
#define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */
|
|
||||||
#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */
|
|
||||||
#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */
|
|
||||||
#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */
|
|
||||||
#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */
|
|
||||||
#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */
|
|
||||||
#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */
|
|
||||||
|
|
||||||
/* DAC noise wave mode */
|
|
||||||
#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
|
|
||||||
#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */
|
|
||||||
#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */
|
|
||||||
#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */
|
|
||||||
|
|
||||||
/* DAC noise wave bit width */
|
|
||||||
#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8))
|
|
||||||
#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */
|
|
||||||
#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */
|
|
||||||
#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */
|
|
||||||
#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */
|
|
||||||
#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */
|
|
||||||
#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */
|
|
||||||
#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */
|
|
||||||
#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */
|
|
||||||
#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */
|
|
||||||
#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */
|
|
||||||
#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */
|
|
||||||
#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */
|
|
||||||
|
|
||||||
/* unmask LFSR bits in DAC LFSR noise mode */
|
|
||||||
#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */
|
|
||||||
#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */
|
|
||||||
#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */
|
|
||||||
#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */
|
|
||||||
#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */
|
|
||||||
#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */
|
|
||||||
#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */
|
|
||||||
#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */
|
|
||||||
#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */
|
|
||||||
#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */
|
|
||||||
#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */
|
|
||||||
#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */
|
|
||||||
|
|
||||||
/* DAC data alignment */
|
|
||||||
#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
|
||||||
#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12b alignment */
|
|
||||||
#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12b alignment */
|
|
||||||
#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8b alignment */
|
|
||||||
/* triangle amplitude in DAC triangle noise mode */
|
|
||||||
#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */
|
|
||||||
#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */
|
|
||||||
#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */
|
|
||||||
#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */
|
|
||||||
#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */
|
|
||||||
#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */
|
|
||||||
#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */
|
|
||||||
#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */
|
|
||||||
#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */
|
|
||||||
#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */
|
|
||||||
#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */
|
|
||||||
#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */
|
|
||||||
|
|
||||||
/* function declarations */
|
|
||||||
/* initialization functions */
|
|
||||||
/* deinitialize DAC */
|
|
||||||
void dac_deinit(void);
|
|
||||||
/* enable DAC */
|
|
||||||
void dac_enable(uint32_t dac_periph);
|
|
||||||
/* disable DAC */
|
|
||||||
void dac_disable(uint32_t dac_periph);
|
|
||||||
/* enable DAC DMA */
|
|
||||||
void dac_dma_enable(uint32_t dac_periph);
|
|
||||||
/* disable DAC DMA */
|
|
||||||
void dac_dma_disable(uint32_t dac_periph);
|
|
||||||
/* enable DAC output buffer */
|
|
||||||
void dac_output_buffer_enable(uint32_t dac_periph);
|
|
||||||
/* disable DAC output buffer */
|
|
||||||
void dac_output_buffer_disable(uint32_t dac_periph);
|
|
||||||
/* get the last data output value */
|
|
||||||
uint16_t dac_output_value_get(uint32_t dac_periph);
|
|
||||||
/* set DAC data holding register value */
|
|
||||||
void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data);
|
|
||||||
|
|
||||||
/* DAC trigger configuration */
|
|
||||||
/* enable DAC trigger */
|
|
||||||
void dac_trigger_enable(uint32_t dac_periph);
|
|
||||||
/* disable DAC trigger */
|
|
||||||
void dac_trigger_disable(uint32_t dac_periph);
|
|
||||||
/* configure DAC trigger source */
|
|
||||||
void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource);
|
|
||||||
/* enable DAC software trigger */
|
|
||||||
void dac_software_trigger_enable(uint32_t dac_periph);
|
|
||||||
/* disable DAC software trigger */
|
|
||||||
void dac_software_trigger_disable(uint32_t dac_periph);
|
|
||||||
|
|
||||||
/* DAC wave mode configuration */
|
|
||||||
/* configure DAC wave mode */
|
|
||||||
void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode);
|
|
||||||
/* configure DAC wave bit width */
|
|
||||||
void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width);
|
|
||||||
/* configure DAC LFSR noise mode */
|
|
||||||
void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits);
|
|
||||||
/* configure DAC triangle noise mode */
|
|
||||||
void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude);
|
|
||||||
|
|
||||||
/* DAC concurrent mode configuration */
|
|
||||||
/* enable DAC concurrent mode */
|
|
||||||
void dac_concurrent_enable(void);
|
|
||||||
/* disable DAC concurrent mode */
|
|
||||||
void dac_concurrent_disable(void);
|
|
||||||
/* enable DAC concurrent software trigger */
|
|
||||||
void dac_concurrent_software_trigger_enable(void);
|
|
||||||
/* disable DAC concurrent software trigger */
|
|
||||||
void dac_concurrent_software_trigger_disable(void);
|
|
||||||
/* enable DAC concurrent buffer function */
|
|
||||||
void dac_concurrent_output_buffer_enable(void);
|
|
||||||
/* disable DAC concurrent buffer function */
|
|
||||||
void dac_concurrent_output_buffer_disable(void);
|
|
||||||
/* set DAC concurrent mode data holding register value */
|
|
||||||
void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1);
|
|
||||||
|
|
||||||
#endif /* GD32VF103_DAC_H */
|
|
||||||
|
|
@ -1,111 +0,0 @@
|
||||||
/*!
|
|
||||||
\file gd32vf103_dbg.h
|
|
||||||
\brief definitions for the DBG
|
|
||||||
|
|
||||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef GD32VF103_DBG_H
|
|
||||||
#define GD32VF103_DBG_H
|
|
||||||
|
|
||||||
#include "gd32vf103.h"
|
|
||||||
#include "gd32vf103_rcu.h"
|
|
||||||
|
|
||||||
|
|
||||||
/* DBG definitions */
|
|
||||||
#define DBG DBG_BASE
|
|
||||||
|
|
||||||
/* registers definitions */
|
|
||||||
#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */
|
|
||||||
#define DBG_CTL REG32(DBG + 0x04U) /*!< DBG control register */
|
|
||||||
|
|
||||||
/* bits definitions */
|
|
||||||
/* DBG_ID */
|
|
||||||
#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */
|
|
||||||
|
|
||||||
/* DBG_CTL */
|
|
||||||
#define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */
|
|
||||||
#define DBG_CTL_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
|
|
||||||
#define DBG_CTL_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
|
|
||||||
#define DBG_CTL_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */
|
|
||||||
#define DBG_CTL_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */
|
|
||||||
#define DBG_CTL_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */
|
|
||||||
#define DBG_CTL_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */
|
|
||||||
#define DBG_CTL_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */
|
|
||||||
#define DBG_CTL_TIMER3_HOLD BIT(13) /*!< hold TIMER3 counter when core is halted */
|
|
||||||
#define DBG_CTL_CAN0_HOLD BIT(14) /*!< debug CAN0 kept when core is halted */
|
|
||||||
#define DBG_CTL_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */
|
|
||||||
#define DBG_CTL_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */
|
|
||||||
#define DBG_CTL_TIMER4_HOLD BIT(18) /*!< hold TIMER4 counter when core is halted */
|
|
||||||
#define DBG_CTL_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */
|
|
||||||
#define DBG_CTL_TIMER6_HOLD BIT(20) /*!< hold TIMER6 counter when core is halted */
|
|
||||||
#define DBG_CTL_CAN1_HOLD BIT(21) /*!< debug CAN1 kept when core is halted */
|
|
||||||
|
|
||||||
/* constants definitions */
|
|
||||||
/* debug hold when core is halted */
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */
|
|
||||||
DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */
|
|
||||||
DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */
|
|
||||||
DBG_TIMER1_HOLD = BIT(11), /*!< hold TIMER1 counter when core is halted */
|
|
||||||
DBG_TIMER2_HOLD = BIT(12), /*!< hold TIMER2 counter when core is halted */
|
|
||||||
DBG_TIMER3_HOLD = BIT(13), /*!< hold TIMER3 counter when core is halted */
|
|
||||||
DBG_CAN0_HOLD = BIT(14), /*!< debug CAN0 kept when core is halted */
|
|
||||||
DBG_I2C0_HOLD = BIT(15), /*!< hold I2C0 smbus when core is halted */
|
|
||||||
DBG_I2C1_HOLD = BIT(16), /*!< hold I2C1 smbus when core is halted */
|
|
||||||
DBG_TIMER4_HOLD = BIT(17), /*!< hold TIMER4 counter when core is halted */
|
|
||||||
DBG_TIMER5_HOLD = BIT(18), /*!< hold TIMER5 counter when core is halted */
|
|
||||||
DBG_TIMER6_HOLD = BIT(19), /*!< hold TIMER6 counter when core is halted */
|
|
||||||
DBG_CAN1_HOLD = BIT(21), /*!< debug CAN1 kept when core is halted */
|
|
||||||
}dbg_periph_enum;
|
|
||||||
|
|
||||||
/* DBG low power mode configurations */
|
|
||||||
#define DBG_LOW_POWER_SLEEP DBG_CTL_SLP_HOLD /*!< keep debugger connection during sleep mode */
|
|
||||||
#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
|
|
||||||
#define DBG_LOW_POWER_STANDBY DBG_CTL_STB_HOLD /*!< keep debugger connection during standby mode */
|
|
||||||
|
|
||||||
/* function declarations */
|
|
||||||
/* read DBG_ID code register */
|
|
||||||
uint32_t dbg_id_get(void);
|
|
||||||
|
|
||||||
/* low power behavior configuration */
|
|
||||||
/* enable low power behavior when the MCU is in debug mode */
|
|
||||||
void dbg_low_power_enable(uint32_t dbg_low_power);
|
|
||||||
/* disable low power behavior when the MCU is in debug mode */
|
|
||||||
void dbg_low_power_disable(uint32_t dbg_low_power);
|
|
||||||
|
|
||||||
/* peripheral behavior configuration */
|
|
||||||
/* enable peripheral behavior when the MCU is in debug mode */
|
|
||||||
void dbg_periph_enable(dbg_periph_enum dbg_periph);
|
|
||||||
/* disable peripheral behavior when the MCU is in debug mode */
|
|
||||||
void dbg_periph_disable(dbg_periph_enum dbg_periph);
|
|
||||||
|
|
||||||
#endif /* GD32VF103_DBG_H */
|
|
||||||
|
|
@ -1,285 +0,0 @@
|
||||||
/*!
|
|
||||||
\file gd32vf103_dma.h
|
|
||||||
\brief definitions for the DMA
|
|
||||||
|
|
||||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef GD32VF103_DMA_H
|
|
||||||
#define GD32VF103_DMA_H
|
|
||||||
|
|
||||||
#include "gd32vf103.h"
|
|
||||||
#include "gd32vf103_rcu.h"
|
|
||||||
#include "gd32vf103_dbg.h"
|
|
||||||
|
|
||||||
|
|
||||||
/* DMA definitions */
|
|
||||||
#define DMA0 (DMA_BASE) /*!< DMA0 base address */
|
|
||||||
#define DMA1 (DMA_BASE + 0x0400U) /*!< DMA1 base address */
|
|
||||||
|
|
||||||
/* registers definitions */
|
|
||||||
#define DMA_INTF(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register */
|
|
||||||
#define DMA_INTC(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag clear register */
|
|
||||||
|
|
||||||
#define DMA_CH0CTL(dmax) REG32((dmax) + 0x08U) /*!< DMA channel 0 control register */
|
|
||||||
#define DMA_CH0CNT(dmax) REG32((dmax) + 0x0CU) /*!< DMA channel 0 counter register */
|
|
||||||
#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 peripheral base address register */
|
|
||||||
#define DMA_CH0MADDR(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 memory base address register */
|
|
||||||
|
|
||||||
#define DMA_CH1CTL(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 1 control register */
|
|
||||||
#define DMA_CH1CNT(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 1 counter register */
|
|
||||||
#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 1 peripheral base address register */
|
|
||||||
#define DMA_CH1MADDR(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 memory base address register */
|
|
||||||
|
|
||||||
#define DMA_CH2CTL(dmax) REG32((dmax) + 0x30U) /*!< DMA channel 2 control register */
|
|
||||||
#define DMA_CH2CNT(dmax) REG32((dmax) + 0x34U) /*!< DMA channel 2 counter register */
|
|
||||||
#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x38U) /*!< DMA channel 2 peripheral base address register */
|
|
||||||
#define DMA_CH2MADDR(dmax) REG32((dmax) + 0x3CU) /*!< DMA channel 2 memory base address register */
|
|
||||||
|
|
||||||
#define DMA_CH3CTL(dmax) REG32((dmax) + 0x44U) /*!< DMA channel 3 control register */
|
|
||||||
#define DMA_CH3CNT(dmax) REG32((dmax) + 0x48U) /*!< DMA channel 3 counter register */
|
|
||||||
#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x4CU) /*!< DMA channel 3 peripheral base address register */
|
|
||||||
#define DMA_CH3MADDR(dmax) REG32((dmax) + 0x50U) /*!< DMA channel 3 memory base address register */
|
|
||||||
|
|
||||||
#define DMA_CH4CTL(dmax) REG32((dmax) + 0x58U) /*!< DMA channel 4 control register */
|
|
||||||
#define DMA_CH4CNT(dmax) REG32((dmax) + 0x5CU) /*!< DMA channel 4 counter register */
|
|
||||||
#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x60U) /*!< DMA channel 4 peripheral base address register */
|
|
||||||
#define DMA_CH4MADDR(dmax) REG32((dmax) + 0x64U) /*!< DMA channel 4 memory base address register */
|
|
||||||
|
|
||||||
#define DMA_CH5CTL(dmax) REG32((dmax) + 0x6CU) /*!< DMA channel 5 control register */
|
|
||||||
#define DMA_CH5CNT(dmax) REG32((dmax) + 0x70U) /*!< DMA channel 5 counter register */
|
|
||||||
#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x74U) /*!< DMA channel 5 peripheral base address register */
|
|
||||||
#define DMA_CH5MADDR(dmax) REG32((dmax) + 0x78U) /*!< DMA channel 5 memory base address register */
|
|
||||||
|
|
||||||
#define DMA_CH6CTL(dmax) REG32((dmax) + 0x80U) /*!< DMA channel 6 control register */
|
|
||||||
#define DMA_CH6CNT(dmax) REG32((dmax) + 0x84U) /*!< DMA channel 6 counter register */
|
|
||||||
#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x88U) /*!< DMA channel 6 peripheral base address register */
|
|
||||||
#define DMA_CH6MADDR(dmax) REG32((dmax) + 0x8CU) /*!< DMA channel 6 memory base address register */
|
|
||||||
|
|
||||||
/* bits definitions */
|
|
||||||
/* DMA_INTF */
|
|
||||||
#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */
|
|
||||||
#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */
|
|
||||||
#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */
|
|
||||||
#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */
|
|
||||||
|
|
||||||
/* DMA_INTC */
|
|
||||||
#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */
|
|
||||||
#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */
|
|
||||||
#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */
|
|
||||||
#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */
|
|
||||||
|
|
||||||
/* DMA_CHxCTL, x=0..6 */
|
|
||||||
#define DMA_CHXCTL_CHEN BIT(0) /*!< channel enable */
|
|
||||||
#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel full transfer finish interrupt */
|
|
||||||
#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel half transfer finish interrupt */
|
|
||||||
#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel error interrupt */
|
|
||||||
#define DMA_CHXCTL_DIR BIT(4) /*!< transfer direction */
|
|
||||||
#define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */
|
|
||||||
#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */
|
|
||||||
#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */
|
|
||||||
#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data width of peripheral */
|
|
||||||
#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data width of memory */
|
|
||||||
#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level */
|
|
||||||
#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */
|
|
||||||
|
|
||||||
/* DMA_CHxCNT, x=0..6 */
|
|
||||||
#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */
|
|
||||||
|
|
||||||
/* DMA_CHxPADDR, x=0..6 */
|
|
||||||
#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */
|
|
||||||
|
|
||||||
/* DMA_CHxMADDR, x=0..6 */
|
|
||||||
#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */
|
|
||||||
|
|
||||||
/* constants definitions */
|
|
||||||
/* DMA channel select */
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
DMA_CH0 = 0, /*!< DMA Channel0 */
|
|
||||||
DMA_CH1, /*!< DMA Channel1 */
|
|
||||||
DMA_CH2, /*!< DMA Channel2 */
|
|
||||||
DMA_CH3, /*!< DMA Channel3 */
|
|
||||||
DMA_CH4, /*!< DMA Channel4 */
|
|
||||||
DMA_CH5, /*!< DMA Channel5 */
|
|
||||||
DMA_CH6 /*!< DMA Channel6 */
|
|
||||||
} dma_channel_enum;
|
|
||||||
|
|
||||||
/* DMA initialize struct */
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t periph_addr; /*!< peripheral base address */
|
|
||||||
uint32_t periph_width; /*!< transfer data size of peripheral */
|
|
||||||
uint32_t memory_addr; /*!< memory base address */
|
|
||||||
uint32_t memory_width; /*!< transfer data size of memory */
|
|
||||||
uint32_t number; /*!< channel transfer number */
|
|
||||||
uint32_t priority; /*!< channel priority level */
|
|
||||||
uint8_t periph_inc; /*!< peripheral increasing mode */
|
|
||||||
uint8_t memory_inc; /*!< memory increasing mode */
|
|
||||||
uint8_t direction; /*!< channel data transfer direction */
|
|
||||||
|
|
||||||
} dma_parameter_struct;
|
|
||||||
|
|
||||||
#define DMA_FLAG_ADD(flag, shift) ((flag) << ((shift) * 4U)) /*!< DMA channel flag shift */
|
|
||||||
|
|
||||||
/* DMA_register address */
|
|
||||||
#define DMA_CHCTL(dma, channel) REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */
|
|
||||||
#define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */
|
|
||||||
#define DMA_CHPADDR(dma, channel) REG32(((dma) + 0x10U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */
|
|
||||||
#define DMA_CHMADDR(dma, channel) REG32(((dma) + 0x14U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */
|
|
||||||
|
|
||||||
/* DMA reset value */
|
|
||||||
#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */
|
|
||||||
#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */
|
|
||||||
#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */
|
|
||||||
#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */
|
|
||||||
#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \
|
|
||||||
DMA_INTF_HTFIF | DMA_INTF_ERRIF) /*!< clear DMA channel DMA_INTF register */
|
|
||||||
|
|
||||||
/* DMA_INTF register */
|
|
||||||
/* interrupt flag bits */
|
|
||||||
#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */
|
|
||||||
#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */
|
|
||||||
#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */
|
|
||||||
#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */
|
|
||||||
|
|
||||||
/* flag bits */
|
|
||||||
#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */
|
|
||||||
#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */
|
|
||||||
#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */
|
|
||||||
#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */
|
|
||||||
|
|
||||||
/* DMA_CHxCTL register */
|
|
||||||
/* interrupt enable bits */
|
|
||||||
#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */
|
|
||||||
#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */
|
|
||||||
#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */
|
|
||||||
|
|
||||||
/* transfer direction */
|
|
||||||
#define DMA_PERIPHERAL_TO_MEMORY ((uint8_t)0x0000U) /*!< read from peripheral and write to memory */
|
|
||||||
#define DMA_MEMORY_TO_PERIPHERAL ((uint8_t)0x0001U) /*!< read from memory and write to peripheral */
|
|
||||||
|
|
||||||
/* peripheral increasing mode */
|
|
||||||
#define DMA_PERIPH_INCREASE_DISABLE ((uint8_t)0x0000U) /*!< next address of peripheral is fixed address mode */
|
|
||||||
#define DMA_PERIPH_INCREASE_ENABLE ((uint8_t)0x0001U) /*!< next address of peripheral is increasing address mode */
|
|
||||||
|
|
||||||
/* memory increasing mode */
|
|
||||||
#define DMA_MEMORY_INCREASE_DISABLE ((uint8_t)0x0000U) /*!< next address of memory is fixed address mode */
|
|
||||||
#define DMA_MEMORY_INCREASE_ENABLE ((uint8_t)0x0001U) /*!< next address of memory is increasing address mode */
|
|
||||||
|
|
||||||
/* transfer data size of peripheral */
|
|
||||||
#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< transfer data size of peripheral */
|
|
||||||
#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0U) /*!< transfer data size of peripheral is 8-bit */
|
|
||||||
#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1U) /*!< transfer data size of peripheral is 16-bit */
|
|
||||||
#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2U) /*!< transfer data size of peripheral is 32-bit */
|
|
||||||
|
|
||||||
/* transfer data size of memory */
|
|
||||||
#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< transfer data size of memory */
|
|
||||||
#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0U) /*!< transfer data size of memory is 8-bit */
|
|
||||||
#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1U) /*!< transfer data size of memory is 16-bit */
|
|
||||||
#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2U) /*!< transfer data size of memory is 32-bit */
|
|
||||||
|
|
||||||
/* channel priority level */
|
|
||||||
#define CHCTL_PRIO(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */
|
|
||||||
#define DMA_PRIORITY_LOW CHCTL_PRIO(0U) /*!< low priority */
|
|
||||||
#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1U) /*!< medium priority */
|
|
||||||
#define DMA_PRIORITY_HIGH CHCTL_PRIO(2U) /*!< high priority */
|
|
||||||
#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3U) /*!< ultra high priority */
|
|
||||||
|
|
||||||
/* memory to memory mode */
|
|
||||||
#define DMA_MEMORY_TO_MEMORY_DISABLE ((uint32_t)0x00000000U) /*!< disable memory to memory mode */
|
|
||||||
#define DMA_MEMORY_TO_MEMORY_ENABLE ((uint32_t)0x00000001U) /*!< enable memory to memory mode */
|
|
||||||
|
|
||||||
/* DMA_CHxCNT register */
|
|
||||||
/* transfer counter */
|
|
||||||
#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT /*!< transfer counter mask */
|
|
||||||
|
|
||||||
/* function declarations */
|
|
||||||
/* DMA deinitialization and initialization functions */
|
|
||||||
/* deinitialize DMA a channel registers */
|
|
||||||
void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx);
|
|
||||||
/* initialize the parameters of DMA struct with the default values */
|
|
||||||
void dma_struct_para_init(dma_parameter_struct* init_struct);
|
|
||||||
/* initialize DMA channel */
|
|
||||||
void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct);
|
|
||||||
/* enable DMA circulation mode */
|
|
||||||
void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx);
|
|
||||||
/* disable DMA circulation mode */
|
|
||||||
void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx);
|
|
||||||
/* enable memory to memory mode */
|
|
||||||
void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx);
|
|
||||||
/* disable memory to memory mode */
|
|
||||||
void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx);
|
|
||||||
/* enable DMA channel */
|
|
||||||
void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx);
|
|
||||||
/* disable DMA channel */
|
|
||||||
void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx);
|
|
||||||
|
|
||||||
/* DMA configuration functions */
|
|
||||||
/* set DMA peripheral base address */
|
|
||||||
void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address);
|
|
||||||
/* set DMA memory base address */
|
|
||||||
void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address);
|
|
||||||
/* set the number of remaining data to be transferred by the DMA */
|
|
||||||
void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number);
|
|
||||||
/* get the number of remaining data to be transferred by the DMA */
|
|
||||||
uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx);
|
|
||||||
/* configure priority level of DMA channel */
|
|
||||||
void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority);
|
|
||||||
/* configure transfer data size of memory */
|
|
||||||
void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth);
|
|
||||||
/* configure transfer data size of peripheral */
|
|
||||||
void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth);
|
|
||||||
/* enable next address increasement algorithm of memory */
|
|
||||||
void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx);
|
|
||||||
/* disable next address increasement algorithm of memory */
|
|
||||||
void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx);
|
|
||||||
/* enable next address increasement algorithm of peripheral */
|
|
||||||
void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx);
|
|
||||||
/* disable next address increasement algorithm of peripheral */
|
|
||||||
void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx);
|
|
||||||
/* configure the direction of data transfer on the channel */
|
|
||||||
void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction);
|
|
||||||
|
|
||||||
/* flag and interrupt functions */
|
|
||||||
/* check DMA flag is set or not */
|
|
||||||
FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
|
|
||||||
/* clear the flag of a DMA channel */
|
|
||||||
void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
|
|
||||||
/* check DMA flag and interrupt enable bit is set or not */
|
|
||||||
FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
|
|
||||||
/* clear the interrupt flag of a DMA channel */
|
|
||||||
void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
|
|
||||||
/* enable DMA interrupt */
|
|
||||||
void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
|
|
||||||
/* disable DMA interrupt */
|
|
||||||
void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
|
|
||||||
|
|
||||||
#endif /* GD32VF103_DMA_H */
|
|
||||||
|
|
@ -1,129 +0,0 @@
|
||||||
/*!
|
|
||||||
\file gd32vf103_exmc.h
|
|
||||||
\brief definitions for the EXMC
|
|
||||||
|
|
||||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef GD32VF103_EXMC_H
|
|
||||||
#define GD32VF103_EXMC_H
|
|
||||||
|
|
||||||
#include "gd32vf103.h"
|
|
||||||
#include "gd32vf103_rcu.h"
|
|
||||||
#include "gd32vf103_dbg.h"
|
|
||||||
|
|
||||||
|
|
||||||
/* EXMC definitions */
|
|
||||||
#define EXMC (EXMC_BASE) /*!< EXMC register base address */
|
|
||||||
|
|
||||||
/* registers definitions */
|
|
||||||
/* NOR/PSRAM */
|
|
||||||
#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register 0 */
|
|
||||||
#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register 0 */
|
|
||||||
#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register 0 */
|
|
||||||
|
|
||||||
/* bits definitions */
|
|
||||||
/* NOR/PSRAM */
|
|
||||||
/* EXMC_SNCTLx, x=0 */
|
|
||||||
#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */
|
|
||||||
#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing */
|
|
||||||
#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */
|
|
||||||
#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */
|
|
||||||
#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */
|
|
||||||
#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */
|
|
||||||
#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */
|
|
||||||
#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */
|
|
||||||
#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */
|
|
||||||
|
|
||||||
/* EXMC_SNTCFGx, x=0 */
|
|
||||||
#define EXMC_SNTCFG_ASET BITS(0,3) /*!< address setup time */
|
|
||||||
#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< address hold time */
|
|
||||||
#define EXMC_SNTCFG_DSET BITS(8,15) /*!< data setup time */
|
|
||||||
#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */
|
|
||||||
|
|
||||||
/* constants definitions */
|
|
||||||
/* EXMC NOR/SRAM timing initialize struct */
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t bus_latency; /*!< configure the bus latency */
|
|
||||||
uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */
|
|
||||||
uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */
|
|
||||||
uint32_t asyn_address_setuptime; /*!< configure the data setup time,asynchronous access mode valid */
|
|
||||||
}exmc_norsram_timing_parameter_struct;
|
|
||||||
|
|
||||||
/* EXMC NOR/SRAM initialize struct */
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */
|
|
||||||
uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */
|
|
||||||
uint32_t nwait_signal; /*!< enable or disable the NWAIT signal */
|
|
||||||
uint32_t memory_write; /*!< enable or disable the write operation */
|
|
||||||
uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */
|
|
||||||
uint32_t databus_width; /*!< specifies the databus width of external memory */
|
|
||||||
uint32_t memory_type; /*!< specifies the type of external memory */
|
|
||||||
uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */
|
|
||||||
exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write */
|
|
||||||
}exmc_norsram_parameter_struct;
|
|
||||||
|
|
||||||
/* EXMC register address */
|
|
||||||
#define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC SRAM/NOR flash control register */
|
|
||||||
#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash timing configuration register */
|
|
||||||
|
|
||||||
/* NOR bank memory data bus width */
|
|
||||||
#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
|
|
||||||
#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */
|
|
||||||
#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */
|
|
||||||
|
|
||||||
/* NOR bank memory type */
|
|
||||||
#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
|
|
||||||
#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */
|
|
||||||
#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */
|
|
||||||
#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */
|
|
||||||
|
|
||||||
/* EXMC NOR/SRAM bank region definition */
|
|
||||||
#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */
|
|
||||||
|
|
||||||
/* EXMC NWAIT signal polarity configuration */
|
|
||||||
#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */
|
|
||||||
#define EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200U) /*!< high level is active of NWAIT */
|
|
||||||
|
|
||||||
/* function declarations */
|
|
||||||
/* deinitialize EXMC NOR/SRAM region */
|
|
||||||
void exmc_norsram_deinit(uint32_t norsram_region);
|
|
||||||
/* exmc_norsram_parameter_struct parameter initialize */
|
|
||||||
void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
|
|
||||||
/* initialize EXMC NOR/SRAM region */
|
|
||||||
void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
|
|
||||||
/* EXMC NOR/SRAM bank enable */
|
|
||||||
void exmc_norsram_enable(uint32_t norsram_region);
|
|
||||||
/* EXMC NOR/SRAM bank disable */
|
|
||||||
void exmc_norsram_disable(uint32_t norsram_region);
|
|
||||||
|
|
||||||
#endif /* GD32VF103_EXMC_H */
|
|
||||||
|
|
@ -1,248 +0,0 @@
|
||||||
/*!
|
|
||||||
\file gd32vf103_exti.h
|
|
||||||
\brief definitions for the EXTI
|
|
||||||
|
|
||||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef GD32VF103_EXTI_H
|
|
||||||
#define GD32VF103_EXTI_H
|
|
||||||
|
|
||||||
#include "gd32vf103.h"
|
|
||||||
#include "gd32vf103_rcu.h"
|
|
||||||
#include "gd32vf103_dbg.h"
|
|
||||||
|
|
||||||
|
|
||||||
/* EXTI definitions */
|
|
||||||
#define EXTI EXTI_BASE
|
|
||||||
|
|
||||||
/* registers definitions */
|
|
||||||
#define EXTI_INTEN REG32(EXTI + 0x00U) /*!< interrupt enable register */
|
|
||||||
#define EXTI_EVEN REG32(EXTI + 0x04U) /*!< event enable register */
|
|
||||||
#define EXTI_RTEN REG32(EXTI + 0x08U) /*!< rising edge trigger enable register */
|
|
||||||
#define EXTI_FTEN REG32(EXTI + 0x0CU) /*!< falling trigger enable register */
|
|
||||||
#define EXTI_SWIEV REG32(EXTI + 0x10U) /*!< software interrupt event register */
|
|
||||||
#define EXTI_PD REG32(EXTI + 0x14U) /*!< pending register */
|
|
||||||
|
|
||||||
/* bits definitions */
|
|
||||||
/* EXTI_INTEN */
|
|
||||||
#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */
|
|
||||||
#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */
|
|
||||||
#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */
|
|
||||||
#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */
|
|
||||||
#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */
|
|
||||||
#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */
|
|
||||||
#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */
|
|
||||||
#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */
|
|
||||||
#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */
|
|
||||||
#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */
|
|
||||||
#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */
|
|
||||||
#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */
|
|
||||||
#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */
|
|
||||||
#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */
|
|
||||||
#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */
|
|
||||||
#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */
|
|
||||||
#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */
|
|
||||||
#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */
|
|
||||||
#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */
|
|
||||||
|
|
||||||
/* EXTI_EVEN */
|
|
||||||
#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */
|
|
||||||
#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */
|
|
||||||
#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */
|
|
||||||
#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */
|
|
||||||
#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */
|
|
||||||
#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */
|
|
||||||
#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */
|
|
||||||
#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */
|
|
||||||
#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */
|
|
||||||
#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */
|
|
||||||
#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */
|
|
||||||
#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */
|
|
||||||
#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */
|
|
||||||
#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */
|
|
||||||
#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */
|
|
||||||
#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */
|
|
||||||
#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */
|
|
||||||
#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */
|
|
||||||
#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */
|
|
||||||
|
|
||||||
/* EXTI_RTEN */
|
|
||||||
#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */
|
|
||||||
#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */
|
|
||||||
#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */
|
|
||||||
#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */
|
|
||||||
#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */
|
|
||||||
#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */
|
|
||||||
#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */
|
|
||||||
#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */
|
|
||||||
#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */
|
|
||||||
#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */
|
|
||||||
#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */
|
|
||||||
#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */
|
|
||||||
#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */
|
|
||||||
#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */
|
|
||||||
#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */
|
|
||||||
#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */
|
|
||||||
#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */
|
|
||||||
#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */
|
|
||||||
#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */
|
|
||||||
|
|
||||||
/* EXTI_FTEN */
|
|
||||||
#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */
|
|
||||||
#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */
|
|
||||||
#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */
|
|
||||||
#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */
|
|
||||||
#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */
|
|
||||||
#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */
|
|
||||||
#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */
|
|
||||||
#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */
|
|
||||||
#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */
|
|
||||||
#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */
|
|
||||||
#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */
|
|
||||||
#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */
|
|
||||||
#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */
|
|
||||||
#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */
|
|
||||||
#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */
|
|
||||||
#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */
|
|
||||||
#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */
|
|
||||||
#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */
|
|
||||||
#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */
|
|
||||||
|
|
||||||
/* EXTI_SWIEV */
|
|
||||||
#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */
|
|
||||||
#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */
|
|
||||||
#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */
|
|
||||||
#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */
|
|
||||||
#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */
|
|
||||||
#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */
|
|
||||||
#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */
|
|
||||||
#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */
|
|
||||||
#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */
|
|
||||||
#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */
|
|
||||||
#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */
|
|
||||||
#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */
|
|
||||||
#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */
|
|
||||||
#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */
|
|
||||||
#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */
|
|
||||||
#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */
|
|
||||||
#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */
|
|
||||||
#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */
|
|
||||||
#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */
|
|
||||||
|
|
||||||
/* EXTI_PD */
|
|
||||||
#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */
|
|
||||||
#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */
|
|
||||||
#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */
|
|
||||||
#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */
|
|
||||||
#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */
|
|
||||||
#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */
|
|
||||||
#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */
|
|
||||||
#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */
|
|
||||||
#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */
|
|
||||||
#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */
|
|
||||||
#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */
|
|
||||||
#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */
|
|
||||||
#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */
|
|
||||||
#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */
|
|
||||||
#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */
|
|
||||||
#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */
|
|
||||||
#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */
|
|
||||||
#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */
|
|
||||||
#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */
|
|
||||||
|
|
||||||
/* constants definitions */
|
|
||||||
/* EXTI line number */
|
|
||||||
typedef enum {
|
|
||||||
EXTI_0 = BIT(0), /*!< EXTI line 0 */
|
|
||||||
EXTI_1 = BIT(1), /*!< EXTI line 1 */
|
|
||||||
EXTI_2 = BIT(2), /*!< EXTI line 2 */
|
|
||||||
EXTI_3 = BIT(3), /*!< EXTI line 3 */
|
|
||||||
EXTI_4 = BIT(4), /*!< EXTI line 4 */
|
|
||||||
EXTI_5 = BIT(5), /*!< EXTI line 5 */
|
|
||||||
EXTI_6 = BIT(6), /*!< EXTI line 6 */
|
|
||||||
EXTI_7 = BIT(7), /*!< EXTI line 7 */
|
|
||||||
EXTI_8 = BIT(8), /*!< EXTI line 8 */
|
|
||||||
EXTI_9 = BIT(9), /*!< EXTI line 9 */
|
|
||||||
EXTI_10 = BIT(10), /*!< EXTI line 10 */
|
|
||||||
EXTI_11 = BIT(11), /*!< EXTI line 11 */
|
|
||||||
EXTI_12 = BIT(12), /*!< EXTI line 12 */
|
|
||||||
EXTI_13 = BIT(13), /*!< EXTI line 13 */
|
|
||||||
EXTI_14 = BIT(14), /*!< EXTI line 14 */
|
|
||||||
EXTI_15 = BIT(15), /*!< EXTI line 15 */
|
|
||||||
EXTI_16 = BIT(16), /*!< EXTI line 16 */
|
|
||||||
EXTI_17 = BIT(17), /*!< EXTI line 17 */
|
|
||||||
EXTI_18 = BIT(18), /*!< EXTI line 18 */
|
|
||||||
} exti_line_enum;
|
|
||||||
|
|
||||||
/* external interrupt and event */
|
|
||||||
typedef enum {
|
|
||||||
EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */
|
|
||||||
EXTI_EVENT /*!< EXTI event mode */
|
|
||||||
} exti_mode_enum;
|
|
||||||
|
|
||||||
/* interrupt trigger mode */
|
|
||||||
typedef enum {
|
|
||||||
EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */
|
|
||||||
EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */
|
|
||||||
EXTI_TRIG_BOTH, /*!< EXTI rising edge and falling edge trigger */
|
|
||||||
EXTI_TRIG_NONE /*!< without rising edge or falling edge trigger */
|
|
||||||
} exti_trig_type_enum;
|
|
||||||
|
|
||||||
/* function declarations */
|
|
||||||
/* initialization, EXTI lines configuration functions */
|
|
||||||
/* deinitialize the EXTI */
|
|
||||||
void exti_deinit(void);
|
|
||||||
/* enable the configuration of EXTI initialize */
|
|
||||||
void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type);
|
|
||||||
/* enable the interrupts from EXTI line x */
|
|
||||||
void exti_interrupt_enable(exti_line_enum linex);
|
|
||||||
/* enable the events from EXTI line x */
|
|
||||||
void exti_event_enable(exti_line_enum linex);
|
|
||||||
/* disable the interrupts from EXTI line x */
|
|
||||||
void exti_interrupt_disable(exti_line_enum linex);
|
|
||||||
/* disable the events from EXTI line x */
|
|
||||||
void exti_event_disable(exti_line_enum linex);
|
|
||||||
|
|
||||||
/* interrupt & flag functions */
|
|
||||||
/* get EXTI lines pending flag */
|
|
||||||
FlagStatus exti_flag_get(exti_line_enum linex);
|
|
||||||
/* clear EXTI lines pending flag */
|
|
||||||
void exti_flag_clear(exti_line_enum linex);
|
|
||||||
/* get EXTI lines flag when the interrupt flag is set */
|
|
||||||
FlagStatus exti_interrupt_flag_get(exti_line_enum linex);
|
|
||||||
/* clear EXTI lines pending flag */
|
|
||||||
void exti_interrupt_flag_clear(exti_line_enum linex);
|
|
||||||
/* enable the EXTI software interrupt event */
|
|
||||||
void exti_software_interrupt_enable(exti_line_enum linex);
|
|
||||||
/* disable the EXTI software interrupt event */
|
|
||||||
void exti_software_interrupt_disable(exti_line_enum linex);
|
|
||||||
|
|
||||||
#endif /* GD32VF103_EXTI_H */
|
|
||||||
|
|
@ -1,314 +0,0 @@
|
||||||
/*!
|
|
||||||
\file gd32vf103_fmc.h
|
|
||||||
\brief definitions for the FMC
|
|
||||||
|
|
||||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef GD32VF103_FMC_H
|
|
||||||
#define GD32VF103_FMC_H
|
|
||||||
|
|
||||||
#include "gd32vf103.h"
|
|
||||||
#include "gd32vf103_rcu.h"
|
|
||||||
#include "gd32vf103_dbg.h"
|
|
||||||
|
|
||||||
|
|
||||||
/* FMC and option byte definition */
|
|
||||||
#define FMC FMC_BASE /*!< FMC register base address */
|
|
||||||
#define OB OB_BASE /*!< option bytes base address */
|
|
||||||
|
|
||||||
/* registers definitions */
|
|
||||||
#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */
|
|
||||||
#define FMC_KEY0 REG32((FMC) + 0x04U) /*!< FMC unlock key register 0 */
|
|
||||||
#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */
|
|
||||||
#define FMC_STAT0 REG32((FMC) + 0x0CU) /*!< FMC status register 0 */
|
|
||||||
#define FMC_CTL0 REG32((FMC) + 0x10U) /*!< FMC control register 0 */
|
|
||||||
#define FMC_ADDR0 REG32((FMC) + 0x14U) /*!< FMC address register 0 */
|
|
||||||
#define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */
|
|
||||||
#define FMC_WP REG32((FMC) + 0x20U) /*!< FMC erase/program protection register */
|
|
||||||
#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */
|
|
||||||
|
|
||||||
#define OB_SPC REG16((OB) + 0x00U) /*!< option byte security protection value */
|
|
||||||
#define OB_USER REG16((OB) + 0x02U) /*!< option byte user value*/
|
|
||||||
#define OB_WP0 REG16((OB) + 0x08U) /*!< option byte write protection 0 */
|
|
||||||
#define OB_WP1 REG16((OB) + 0x0AU) /*!< option byte write protection 1 */
|
|
||||||
#define OB_WP2 REG16((OB) + 0x0CU) /*!< option byte write protection 2 */
|
|
||||||
#define OB_WP3 REG16((OB) + 0x0EU) /*!< option byte write protection 3 */
|
|
||||||
|
|
||||||
/* bits definitions */
|
|
||||||
/* FMC_WS */
|
|
||||||
#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */
|
|
||||||
|
|
||||||
/* FMC_KEY0 */
|
|
||||||
#define FMC_KEY0_KEY BITS(0,31) /*!< FMC_CTL0 unlock key bits */
|
|
||||||
|
|
||||||
/* FMC_OBKEY */
|
|
||||||
#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */
|
|
||||||
|
|
||||||
/* FMC_STAT0 */
|
|
||||||
#define FMC_STAT0_BUSY BIT(0) /*!< flash busy flag bit */
|
|
||||||
#define FMC_STAT0_PGERR BIT(2) /*!< flash program error flag bit */
|
|
||||||
#define FMC_STAT0_WPERR BIT(4) /*!< erase/program protection error flag bit */
|
|
||||||
#define FMC_STAT0_ENDF BIT(5) /*!< end of operation flag bit */
|
|
||||||
|
|
||||||
/* FMC_CTL0 */
|
|
||||||
#define FMC_CTL0_PG BIT(0) /*!< main flash program for bank0 command bit */
|
|
||||||
#define FMC_CTL0_PER BIT(1) /*!< main flash page erase for bank0 command bit */
|
|
||||||
#define FMC_CTL0_MER BIT(2) /*!< main flash mass erase for bank0 command bit */
|
|
||||||
#define FMC_CTL0_OBPG BIT(4) /*!< option bytes program command bit */
|
|
||||||
#define FMC_CTL0_OBER BIT(5) /*!< option bytes erase command bit */
|
|
||||||
#define FMC_CTL0_START BIT(6) /*!< send erase command to FMC bit */
|
|
||||||
#define FMC_CTL0_LK BIT(7) /*!< FMC_CTL0 lock bit */
|
|
||||||
#define FMC_CTL0_OBWEN BIT(9) /*!< option bytes erase/program enable bit */
|
|
||||||
#define FMC_CTL0_ERRIE BIT(10) /*!< error interrupt enable bit */
|
|
||||||
#define FMC_CTL0_ENDIE BIT(12) /*!< end of operation interrupt enable bit */
|
|
||||||
|
|
||||||
/* FMC_ADDR0 */
|
|
||||||
#define FMC_ADDR0_ADDR BITS(0,31) /*!< Flash erase/program command address bits */
|
|
||||||
|
|
||||||
/* FMC_OBSTAT */
|
|
||||||
#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */
|
|
||||||
#define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */
|
|
||||||
#define FMC_OBSTAT_USER BITS(2,9) /*!< store USER of option bytes block after system reset */
|
|
||||||
#define FMC_OBSTAT_DATA BITS(10,25) /*!< store DATA of option bytes block after system reset. */
|
|
||||||
|
|
||||||
/* FMC_WP */
|
|
||||||
#define FMC_WP_WP BITS(0,31) /*!< store WP of option bytes block after system reset */
|
|
||||||
|
|
||||||
/* FMC_WSEN */
|
|
||||||
#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */
|
|
||||||
|
|
||||||
/* FMC_PID */
|
|
||||||
#define FMC_PID_PID BITS(0,31) /*!< product ID bits */
|
|
||||||
|
|
||||||
/* constants definitions */
|
|
||||||
/* define the FMC bit position and its register index offset */
|
|
||||||
#define FMC_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
|
|
||||||
#define FMC_REG_VAL(offset) (REG32(FMC + ((uint32_t)(offset) >> 6)))
|
|
||||||
#define FMC_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
|
|
||||||
#define FMC_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1))
|
|
||||||
#define FMC_REG_VALS(offset) (REG32(FMC + ((uint32_t)(offset) >> 12)))
|
|
||||||
#define FMC_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU)
|
|
||||||
#define FMC_BIT_POS1(val) ((uint32_t)(val) & 0x1FU)
|
|
||||||
#define FMC_REG_OFFSET_GET(flag) ((uint32_t)(flag) >> 12)
|
|
||||||
|
|
||||||
/* configuration register */
|
|
||||||
#define FMC_STAT0_REG_OFFSET 0x0CU /*!< status register 0 offset */
|
|
||||||
#define FMC_CTL0_REG_OFFSET 0x10U /*!< control register 0 offset */
|
|
||||||
#define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option byte status register offset */
|
|
||||||
|
|
||||||
/* fmc state */
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
FMC_READY, /*!< the operation has been completed */
|
|
||||||
FMC_BUSY, /*!< the operation is in progress */
|
|
||||||
FMC_PGERR, /*!< program error */
|
|
||||||
FMC_WPERR, /*!< erase/program protection error */
|
|
||||||
FMC_TOERR, /*!< timeout error */
|
|
||||||
}fmc_state_enum;
|
|
||||||
|
|
||||||
/* FMC interrupt enable */
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
FMC_INT_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U), /*!< enable FMC end of program interrupt */
|
|
||||||
FMC_INT_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U), /*!< enable FMC error interrupt */
|
|
||||||
}fmc_int_enum;
|
|
||||||
|
|
||||||
/* FMC flags */
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
FMC_FLAG_BUSY = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U), /*!< FMC busy flag */
|
|
||||||
FMC_FLAG_PGERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U), /*!< FMC operation error flag bit */
|
|
||||||
FMC_FLAG_WPERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U), /*!< FMC erase/program protection error flag bit */
|
|
||||||
FMC_FLAG_END = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 5U), /*!< FMC end of operation flag bit */
|
|
||||||
FMC_FLAG_OBERR = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U), /*!< FMC option bytes read error flag */
|
|
||||||
}fmc_flag_enum;
|
|
||||||
|
|
||||||
/* FMC interrupt flags */
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
FMC_INT_FLAG_PGERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U), /*!< FMC operation error interrupt flag bit */
|
|
||||||
FMC_INT_FLAG_WPERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U), /*!< FMC erase/program protection error interrupt flag bit */
|
|
||||||
FMC_INT_FLAG_END = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U), /*!< FMC end of operation interrupt flag bit */
|
|
||||||
}fmc_interrupt_flag_enum;
|
|
||||||
|
|
||||||
/* unlock key */
|
|
||||||
#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */
|
|
||||||
#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */
|
|
||||||
|
|
||||||
/* FMC wait state counter */
|
|
||||||
#define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval)))
|
|
||||||
#define WS_WSCNT_0 WS_WSCNT(0) /*!< FMC 0 wait */
|
|
||||||
#define WS_WSCNT_1 WS_WSCNT(1) /*!< FMC 1 wait */
|
|
||||||
#define WS_WSCNT_2 WS_WSCNT(2) /*!< FMC 2 wait */
|
|
||||||
|
|
||||||
/* option bytes software/hardware free watch dog timer */
|
|
||||||
#define OB_FWDGT_SW ((uint8_t)0x01U) /*!< software free watchdog */
|
|
||||||
#define OB_FWDGT_HW ((uint8_t)0x00U) /*!< hardware free watchdog */
|
|
||||||
|
|
||||||
/* option bytes reset or not entering deep sleep mode */
|
|
||||||
#define OB_DEEPSLEEP_NRST ((uint8_t)0x02U) /*!< no reset when entering deepsleep mode */
|
|
||||||
#define OB_DEEPSLEEP_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering deepsleep mode */
|
|
||||||
|
|
||||||
/* option bytes reset or not entering standby mode */
|
|
||||||
#define OB_STDBY_NRST ((uint8_t)0x04U) /*!< no reset when entering deepsleep mode */
|
|
||||||
#define OB_STDBY_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering standby mode */
|
|
||||||
|
|
||||||
/* option bytes boot bank value */
|
|
||||||
#define OB_BOOT_B0 ((uint8_t)0x08U) /*!< boot from bank0 */
|
|
||||||
|
|
||||||
#define OB_USER_MASK ((uint8_t)0xF0U) /*!< MASK value */
|
|
||||||
|
|
||||||
/* read protect configure */
|
|
||||||
#define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */
|
|
||||||
#define FMC_USPC ((uint8_t)0xBBU) /*!< under security protection */
|
|
||||||
|
|
||||||
/* OB_SPC */
|
|
||||||
#define OB_SPC_SPC ((uint32_t)0x000000FFU) /*!< option byte security protection value */
|
|
||||||
#define OB_SPC_SPC_N ((uint32_t)0x0000FF00U) /*!< option byte security protection complement value */
|
|
||||||
|
|
||||||
/* OB_USER */
|
|
||||||
#define OB_USER_USER ((uint32_t)0x00FF0000U) /*!< user option value */
|
|
||||||
#define OB_USER_USER_N ((uint32_t)0xFF000000U) /*!< user option complement value */
|
|
||||||
|
|
||||||
/* OB_WP0 */
|
|
||||||
#define OB_WP0_WP0 ((uint32_t)0x000000FFU) /*!< FMC write protection option value */
|
|
||||||
|
|
||||||
/* OB_WP1 */
|
|
||||||
#define OB_WP1_WP1 ((uint32_t)0x0000FF00U) /*!< FMC write protection option complement value */
|
|
||||||
|
|
||||||
/* OB_WP2 */
|
|
||||||
#define OB_WP2_WP2 ((uint32_t)0x00FF0000U) /*!< FMC write protection option value */
|
|
||||||
|
|
||||||
/* OB_WP3 */
|
|
||||||
#define OB_WP3_WP3 ((uint32_t)0xFF000000U) /*!< FMC write protection option complement value */
|
|
||||||
|
|
||||||
/* option bytes write protection */
|
|
||||||
#define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */
|
|
||||||
#define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */
|
|
||||||
#define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */
|
|
||||||
#define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */
|
|
||||||
#define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */
|
|
||||||
#define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */
|
|
||||||
#define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */
|
|
||||||
#define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */
|
|
||||||
#define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */
|
|
||||||
#define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */
|
|
||||||
#define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */
|
|
||||||
#define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */
|
|
||||||
#define OB_WP_12 ((uint32_t)0x00001000U) /*!< erase/program protection of sector 12 */
|
|
||||||
#define OB_WP_13 ((uint32_t)0x00002000U) /*!< erase/program protection of sector 13 */
|
|
||||||
#define OB_WP_14 ((uint32_t)0x00004000U) /*!< erase/program protection of sector 14 */
|
|
||||||
#define OB_WP_15 ((uint32_t)0x00008000U) /*!< erase/program protection of sector 15 */
|
|
||||||
#define OB_WP_16 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 16 */
|
|
||||||
#define OB_WP_17 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 17 */
|
|
||||||
#define OB_WP_18 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 18 */
|
|
||||||
#define OB_WP_19 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 19 */
|
|
||||||
#define OB_WP_20 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 20 */
|
|
||||||
#define OB_WP_21 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 21 */
|
|
||||||
#define OB_WP_22 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 22 */
|
|
||||||
#define OB_WP_23 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 23 */
|
|
||||||
#define OB_WP_24 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 24 */
|
|
||||||
#define OB_WP_25 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 25 */
|
|
||||||
#define OB_WP_26 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 26 */
|
|
||||||
#define OB_WP_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 27 */
|
|
||||||
#define OB_WP_28 ((uint32_t)0x10000000U) /*!< erase/program protection of sector 28 */
|
|
||||||
#define OB_WP_29 ((uint32_t)0x20000000U) /*!< erase/program protection of sector 29 */
|
|
||||||
#define OB_WP_30 ((uint32_t)0x40000000U) /*!< erase/program protection of sector 30 */
|
|
||||||
#define OB_WP_31 ((uint32_t)0x80000000U) /*!< erase/program protection of sector 31 */
|
|
||||||
#define OB_WP_ALL ((uint32_t)0xFFFFFFFFU) /*!< erase/program protection of all sectors */
|
|
||||||
|
|
||||||
/* FMC timeout */
|
|
||||||
#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< FMC timeout count value */
|
|
||||||
|
|
||||||
/* FMC BANK address */
|
|
||||||
#define FMC_SIZE (*(uint16_t *)0x1FFFF7E0U) /*!< FMC size */
|
|
||||||
#define SRAM_SIZE (*(uint16_t *)0x1FFFF7E2U) /*!< SRAM size*/
|
|
||||||
|
|
||||||
/* function declarations */
|
|
||||||
/* FMC main memory programming functions */
|
|
||||||
/* set the FMC wait state counter */
|
|
||||||
void fmc_wscnt_set(uint32_t wscnt);
|
|
||||||
/* unlock the main FMC operation */
|
|
||||||
void fmc_unlock(void);
|
|
||||||
/* lock the main FMC operation */
|
|
||||||
void fmc_lock(void);
|
|
||||||
/* FMC erase page */
|
|
||||||
fmc_state_enum fmc_page_erase(uint32_t page_address);
|
|
||||||
/* FMC erase whole chip */
|
|
||||||
fmc_state_enum fmc_mass_erase(void);
|
|
||||||
/* FMC program a word at the corresponding address */
|
|
||||||
fmc_state_enum fmc_word_program(uint32_t address, uint32_t data);
|
|
||||||
/* FMC program a half word at the corresponding address */
|
|
||||||
fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data);
|
|
||||||
|
|
||||||
/* FMC option bytes programming functions */
|
|
||||||
/* unlock the option byte operation */
|
|
||||||
void ob_unlock(void);
|
|
||||||
/* lock the option byte operation */
|
|
||||||
void ob_lock(void);
|
|
||||||
/* erase the FMC option byte */
|
|
||||||
fmc_state_enum ob_erase(void);
|
|
||||||
/* enable write protect */
|
|
||||||
fmc_state_enum ob_write_protection_enable(uint32_t ob_wp);
|
|
||||||
/* configure the option byte security protection */
|
|
||||||
fmc_state_enum ob_security_protection_config(uint8_t ob_spc);
|
|
||||||
/* write the FMC option byte */
|
|
||||||
fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot);
|
|
||||||
/* program option bytes data */
|
|
||||||
fmc_state_enum ob_data_program(uint32_t address, uint8_t data);
|
|
||||||
/* get the FMC option byte user */
|
|
||||||
uint8_t ob_user_get(void);
|
|
||||||
/* get OB_DATA in register FMC_OBSTAT */
|
|
||||||
uint16_t ob_data_get(void);
|
|
||||||
/* get the FMC option byte write protection */
|
|
||||||
uint32_t ob_write_protection_get(void);
|
|
||||||
/* get FMC option byte security protection code value */
|
|
||||||
FlagStatus ob_spc_get(void);
|
|
||||||
|
|
||||||
/* FMC interrupts and flags management functions */
|
|
||||||
/* enable FMC interrupt */
|
|
||||||
void fmc_interrupt_enable(uint32_t interrupt);
|
|
||||||
/* disable FMC interrupt */
|
|
||||||
void fmc_interrupt_disable(uint32_t interrupt);
|
|
||||||
/* check flag is set or not */
|
|
||||||
FlagStatus fmc_flag_get(uint32_t flag);
|
|
||||||
/* clear the FMC flag */
|
|
||||||
void fmc_flag_clear(uint32_t flag);
|
|
||||||
/* get FMC interrupt flag state */
|
|
||||||
FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag);
|
|
||||||
/* clear FMC interrupt flag state */
|
|
||||||
void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag);
|
|
||||||
/* return the FMC state */
|
|
||||||
fmc_state_enum fmc_state_get(void);
|
|
||||||
/* check FMC ready or not */
|
|
||||||
fmc_state_enum fmc_ready_wait(uint32_t timeout);
|
|
||||||
|
|
||||||
#endif /* GD32VF103_FMC_H */
|
|
||||||
|
|
@ -1,107 +0,0 @@
|
||||||
/*!
|
|
||||||
\file gd32vf103_fwdgt.h
|
|
||||||
\brief definitions for the FWDGT
|
|
||||||
|
|
||||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef GD32VF103_FWDGT_H
|
|
||||||
#define GD32VF103_FWDGT_H
|
|
||||||
|
|
||||||
#include "gd32vf103.h"
|
|
||||||
#include "gd32vf103_rcu.h"
|
|
||||||
#include "gd32vf103_dbg.h"
|
|
||||||
|
|
||||||
|
|
||||||
/* FWDGT definitions */
|
|
||||||
#define FWDGT FWDGT_BASE /*!< FWDGT base address */
|
|
||||||
|
|
||||||
/* registers definitions */
|
|
||||||
#define FWDGT_CTL REG32((FWDGT) + 0x00000000U) /*!< FWDGT control register */
|
|
||||||
#define FWDGT_PSC REG32((FWDGT) + 0x00000004U) /*!< FWDGT prescaler register */
|
|
||||||
#define FWDGT_RLD REG32((FWDGT) + 0x00000008U) /*!< FWDGT reload register */
|
|
||||||
#define FWDGT_STAT REG32((FWDGT) + 0x0000000CU) /*!< FWDGT status register */
|
|
||||||
|
|
||||||
/* bits definitions */
|
|
||||||
/* FWDGT_CTL */
|
|
||||||
#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */
|
|
||||||
|
|
||||||
/* FWDGT_PSC */
|
|
||||||
#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */
|
|
||||||
|
|
||||||
/* FWDGT_RLD */
|
|
||||||
#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */
|
|
||||||
|
|
||||||
/* FWDGT_STAT */
|
|
||||||
#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */
|
|
||||||
#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */
|
|
||||||
|
|
||||||
/* constants definitions */
|
|
||||||
/* psc register value */
|
|
||||||
#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
|
|
||||||
#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */
|
|
||||||
#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */
|
|
||||||
#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */
|
|
||||||
#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */
|
|
||||||
#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */
|
|
||||||
#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */
|
|
||||||
#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */
|
|
||||||
|
|
||||||
/* control value */
|
|
||||||
#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */
|
|
||||||
#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */
|
|
||||||
#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */
|
|
||||||
#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */
|
|
||||||
|
|
||||||
/* FWDGT timeout value */
|
|
||||||
#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */
|
|
||||||
#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */
|
|
||||||
|
|
||||||
/* FWDGT flag definitions */
|
|
||||||
#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */
|
|
||||||
#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */
|
|
||||||
|
|
||||||
/* function declarations */
|
|
||||||
/* enable write access to FWDGT_PSC and FWDGT_RLD */
|
|
||||||
void fwdgt_write_enable(void);
|
|
||||||
/* disable write access to FWDGT_PSC and FWDGT_RLD */
|
|
||||||
void fwdgt_write_disable(void);
|
|
||||||
/* start the free watchdog timer counter */
|
|
||||||
void fwdgt_enable(void);
|
|
||||||
|
|
||||||
/* reload the counter of FWDGT */
|
|
||||||
void fwdgt_counter_reload(void);
|
|
||||||
/* configure counter reload value, and prescaler divider value */
|
|
||||||
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
|
|
||||||
|
|
||||||
/* get flag state of FWDGT */
|
|
||||||
FlagStatus fwdgt_flag_get(uint16_t flag);
|
|
||||||
|
|
||||||
#endif /* GD32VF103_FWDGT_H */
|
|
||||||
|
|
@ -1,423 +0,0 @@
|
||||||
/*!
|
|
||||||
\file gd32vf103_gpio.h
|
|
||||||
\brief definitions for the GPIO
|
|
||||||
|
|
||||||
\version 2019-06-5, V1.0.0, firmware for GD32VF103
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef GD32VF103_GPIO_H
|
|
||||||
#define GD32VF103_GPIO_H
|
|
||||||
|
|
||||||
#include "gd32vf103.h"
|
|
||||||
#include "gd32vf103_rcu.h"
|
|
||||||
#include "gd32vf103_dbg.h"
|
|
||||||
|
|
||||||
/* GPIOx(x=A,B,C,D,E) definitions */
|
|
||||||
#define GPIOA (GPIO_BASE + 0x00000000U)
|
|
||||||
#define GPIOB (GPIO_BASE + 0x00000400U)
|
|
||||||
#define GPIOC (GPIO_BASE + 0x00000800U)
|
|
||||||
#define GPIOD (GPIO_BASE + 0x00000C00U)
|
|
||||||
#define GPIOE (GPIO_BASE + 0x00001000U)
|
|
||||||
|
|
||||||
/* AFIO definitions */
|
|
||||||
#define AFIO AFIO_BASE
|
|
||||||
|
|
||||||
/* registers definitions */
|
|
||||||
|
|
||||||
/* GPIO registers definitions */
|
|
||||||
#define GPIO_CTL0(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register 0 */
|
|
||||||
#define GPIO_CTL1(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port control register 1 */
|
|
||||||
#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port input status register */
|
|
||||||
#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port output control register */
|
|
||||||
#define GPIO_BOP(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port bit operation register */
|
|
||||||
#define GPIO_BC(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO bit clear register */
|
|
||||||
#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port configuration lock register */
|
|
||||||
|
|
||||||
/* AFIO registers definitions */
|
|
||||||
#define AFIO_EC REG32(AFIO + 0x00U) /*!< AFIO event control register */
|
|
||||||
#define AFIO_PCF0 REG32(AFIO + 0x04U) /*!< AFIO port configuration register 0 */
|
|
||||||
#define AFIO_EXTISS0 REG32(AFIO + 0x08U) /*!< AFIO port EXTI sources selection register 0 */
|
|
||||||
#define AFIO_EXTISS1 REG32(AFIO + 0x0CU) /*!< AFIO port EXTI sources selection register 1 */
|
|
||||||
#define AFIO_EXTISS2 REG32(AFIO + 0x10U) /*!< AFIO port EXTI sources selection register 2 */
|
|
||||||
#define AFIO_EXTISS3 REG32(AFIO + 0x14U) /*!< AFIO port EXTI sources selection register 3 */
|
|
||||||
#define AFIO_PCF1 REG32(AFIO + 0x1CU) /*!< AFIO port configuration register 1 */
|
|
||||||
|
|
||||||
/* bits definitions */
|
|
||||||
/* GPIO_CTL0 */
|
|
||||||
#define GPIO_CTL0_MD0 BITS(0, 1) /*!< port 0 mode bits */
|
|
||||||
#define GPIO_CTL0_CTL0 BITS(2, 3) /*!< pin 0 configuration bits */
|
|
||||||
#define GPIO_CTL0_MD1 BITS(4, 5) /*!< port 1 mode bits */
|
|
||||||
#define GPIO_CTL0_CTL1 BITS(6, 7) /*!< pin 1 configuration bits */
|
|
||||||
#define GPIO_CTL0_MD2 BITS(8, 9) /*!< port 2 mode bits */
|
|
||||||
#define GPIO_CTL0_CTL2 BITS(10, 11) /*!< pin 2 configuration bits */
|
|
||||||
#define GPIO_CTL0_MD3 BITS(12, 13) /*!< port 3 mode bits */
|
|
||||||
#define GPIO_CTL0_CTL3 BITS(14, 15) /*!< pin 3 configuration bits */
|
|
||||||
#define GPIO_CTL0_MD4 BITS(16, 17) /*!< port 4 mode bits */
|
|
||||||
#define GPIO_CTL0_CTL4 BITS(18, 19) /*!< pin 4 configuration bits */
|
|
||||||
#define GPIO_CTL0_MD5 BITS(20, 21) /*!< port 5 mode bits */
|
|
||||||
#define GPIO_CTL0_CTL5 BITS(22, 23) /*!< pin 5 configuration bits */
|
|
||||||
#define GPIO_CTL0_MD6 BITS(24, 25) /*!< port 6 mode bits */
|
|
||||||
#define GPIO_CTL0_CTL6 BITS(26, 27) /*!< pin 6 configuration bits */
|
|
||||||
#define GPIO_CTL0_MD7 BITS(28, 29) /*!< port 7 mode bits */
|
|
||||||
#define GPIO_CTL0_CTL7 BITS(30, 31) /*!< pin 7 configuration bits */
|
|
||||||
|
|
||||||
/* GPIO_CTL1 */
|
|
||||||
#define GPIO_CTL1_MD8 BITS(0, 1) /*!< port 8 mode bits */
|
|
||||||
#define GPIO_CTL1_CTL8 BITS(2, 3) /*!< pin 8 configuration bits */
|
|
||||||
#define GPIO_CTL1_MD9 BITS(4, 5) /*!< port 9 mode bits */
|
|
||||||
#define GPIO_CTL1_CTL9 BITS(6, 7) /*!< pin 9 configuration bits */
|
|
||||||
#define GPIO_CTL1_MD10 BITS(8, 9) /*!< port 10 mode bits */
|
|
||||||
#define GPIO_CTL1_CTL10 BITS(10, 11) /*!< pin 10 configuration bits */
|
|
||||||
#define GPIO_CTL1_MD11 BITS(12, 13) /*!< port 11 mode bits */
|
|
||||||
#define GPIO_CTL1_CTL11 BITS(14, 15) /*!< pin 11 configuration bits */
|
|
||||||
#define GPIO_CTL1_MD12 BITS(16, 17) /*!< port 12 mode bits */
|
|
||||||
#define GPIO_CTL1_CTL12 BITS(18, 19) /*!< pin 12 configuration bits */
|
|
||||||
#define GPIO_CTL1_MD13 BITS(20, 21) /*!< port 13 mode bits */
|
|
||||||
#define GPIO_CTL1_CTL13 BITS(22, 23) /*!< pin 13 configuration bits */
|
|
||||||
#define GPIO_CTL1_MD14 BITS(24, 25) /*!< port 14 mode bits */
|
|
||||||
#define GPIO_CTL1_CTL14 BITS(26, 27) /*!< pin 14 configuration bits */
|
|
||||||
#define GPIO_CTL1_MD15 BITS(28, 29) /*!< port 15 mode bits */
|
|
||||||
#define GPIO_CTL1_CTL15 BITS(30, 31) /*!< pin 15 configuration bits */
|
|
||||||
|
|
||||||
/* GPIO_ISTAT */
|
|
||||||
#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */
|
|
||||||
#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */
|
|
||||||
#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */
|
|
||||||
#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */
|
|
||||||
#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */
|
|
||||||
#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */
|
|
||||||
#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */
|
|
||||||
#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */
|
|
||||||
#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */
|
|
||||||
#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */
|
|
||||||
#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */
|
|
||||||
#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */
|
|
||||||
#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */
|
|
||||||
#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */
|
|
||||||
#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */
|
|
||||||
#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */
|
|
||||||
|
|
||||||
/* GPIO_OCTL */
|
|
||||||
#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */
|
|
||||||
#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */
|
|
||||||
#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */
|
|
||||||
#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */
|
|
||||||
#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */
|
|
||||||
#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */
|
|
||||||
#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */
|
|
||||||
#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */
|
|
||||||
#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */
|
|
||||||
#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */
|
|
||||||
#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */
|
|
||||||
#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */
|
|
||||||
#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */
|
|
||||||
#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */
|
|
||||||
#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */
|
|
||||||
#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */
|
|
||||||
|
|
||||||
/* GPIO_BOP */
|
|
||||||
#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */
|
|
||||||
#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */
|
|
||||||
#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */
|
|
||||||
#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */
|
|
||||||
#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */
|
|
||||||
#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */
|
|
||||||
#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */
|
|
||||||
#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */
|
|
||||||
#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */
|
|
||||||
#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */
|
|
||||||
#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */
|
|
||||||
#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */
|
|
||||||
#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */
|
|
||||||
#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */
|
|
||||||
#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */
|
|
||||||
#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */
|
|
||||||
#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */
|
|
||||||
#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */
|
|
||||||
#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */
|
|
||||||
#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */
|
|
||||||
#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */
|
|
||||||
#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */
|
|
||||||
#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */
|
|
||||||
#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */
|
|
||||||
#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */
|
|
||||||
#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */
|
|
||||||
#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */
|
|
||||||
#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */
|
|
||||||
#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */
|
|
||||||
#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */
|
|
||||||
#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */
|
|
||||||
#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */
|
|
||||||
|
|
||||||
/* GPIO_BC */
|
|
||||||
#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */
|
|
||||||
#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */
|
|
||||||
#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */
|
|
||||||
#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */
|
|
||||||
#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */
|
|
||||||
#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */
|
|
||||||
#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */
|
|
||||||
#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */
|
|
||||||
#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */
|
|
||||||
#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */
|
|
||||||
#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */
|
|
||||||
#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */
|
|
||||||
#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */
|
|
||||||
#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */
|
|
||||||
#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */
|
|
||||||
#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */
|
|
||||||
|
|
||||||
/* GPIO_LOCK */
|
|
||||||
#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */
|
|
||||||
#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */
|
|
||||||
#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */
|
|
||||||
#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */
|
|
||||||
#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */
|
|
||||||
#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */
|
|
||||||
#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */
|
|
||||||
#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */
|
|
||||||
#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */
|
|
||||||
#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */
|
|
||||||
#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */
|
|
||||||
#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */
|
|
||||||
#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */
|
|
||||||
#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */
|
|
||||||
#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */
|
|
||||||
#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */
|
|
||||||
#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */
|
|
||||||
|
|
||||||
/* AFIO_EC */
|
|
||||||
#define AFIO_EC_PIN BITS(0, 3) /*!< event output pin selection */
|
|
||||||
#define AFIO_EC_PORT BITS(4, 6) /*!< event output port selection */
|
|
||||||
#define AFIO_EC_EOE BIT(7) /*!< event output enable */
|
|
||||||
|
|
||||||
/* AFIO_PCF0 */
|
|
||||||
#define AFIO_PCF0_SPI0_REMAP BIT(0) /*!< SPI0 remapping */
|
|
||||||
#define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */
|
|
||||||
#define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */
|
|
||||||
#define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */
|
|
||||||
#define AFIO_PCF0_USART2_REMAP BITS(4, 5) /*!< USART2 remapping */
|
|
||||||
#define AFIO_PCF0_TIMER0_REMAP BITS(6, 7) /*!< TIMER0 remapping */
|
|
||||||
#define AFIO_PCF0_TIMER1_REMAP BITS(8, 9) /*!< TIMER1 remapping */
|
|
||||||
#define AFIO_PCF0_TIMER2_REMAP BITS(10, 11) /*!< TIMER2 remapping */
|
|
||||||
#define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */
|
|
||||||
#define AFIO_PCF0_CAN_REMAP BITS(13, 14) /*!< CAN remapping */
|
|
||||||
#define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */
|
|
||||||
#define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER3 channel3 internal remapping */
|
|
||||||
#define AFIO_PCF0_SWJ_CFG BITS(24, 26) /*!< serial wire JTAG configuration */
|
|
||||||
#define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */
|
|
||||||
#define AFIO_PCF0_TIMER1_ITI1_REMAP BIT(29) /*!< TIMER1 internal trigger 1 remapping */
|
|
||||||
|
|
||||||
/* AFIO_EXTISS0 */
|
|
||||||
#define AFIO_EXTI0_SS BITS(0, 3) /*!< EXTI 0 sources selection */
|
|
||||||
#define AFIO_EXTI1_SS BITS(4, 7) /*!< EXTI 1 sources selection */
|
|
||||||
#define AFIO_EXTI2_SS BITS(8, 11) /*!< EXTI 2 sources selection */
|
|
||||||
#define AFIO_EXTI3_SS BITS(12, 15) /*!< EXTI 3 sources selection */
|
|
||||||
|
|
||||||
/* AFIO_EXTISS1 */
|
|
||||||
#define AFIO_EXTI4_SS BITS(0, 3) /*!< EXTI 4 sources selection */
|
|
||||||
#define AFIO_EXTI5_SS BITS(4, 7) /*!< EXTI 5 sources selection */
|
|
||||||
#define AFIO_EXTI6_SS BITS(8, 11) /*!< EXTI 6 sources selection */
|
|
||||||
#define AFIO_EXTI7_SS BITS(12, 15) /*!< EXTI 7 sources selection */
|
|
||||||
|
|
||||||
/* AFIO_EXTISS2 */
|
|
||||||
#define AFIO_EXTI8_SS BITS(0, 3) /*!< EXTI 8 sources selection */
|
|
||||||
#define AFIO_EXTI9_SS BITS(4, 7) /*!< EXTI 9 sources selection */
|
|
||||||
#define AFIO_EXTI10_SS BITS(8, 11) /*!< EXTI 10 sources selection */
|
|
||||||
#define AFIO_EXTI11_SS BITS(12, 15) /*!< EXTI 11 sources selection */
|
|
||||||
|
|
||||||
/* AFIO_EXTISS3 */
|
|
||||||
#define AFIO_EXTI12_SS BITS(0, 3) /*!< EXTI 12 sources selection */
|
|
||||||
#define AFIO_EXTI13_SS BITS(4, 7) /*!< EXTI 13 sources selection */
|
|
||||||
#define AFIO_EXTI14_SS BITS(8, 11) /*!< EXTI 14 sources selection */
|
|
||||||
#define AFIO_EXTI15_SS BITS(12, 15) /*!< EXTI 15 sources selection */
|
|
||||||
|
|
||||||
/* AFIO_PCF1 */
|
|
||||||
#define AFIO_PCF1_EXMC_NADV BIT(10) /*!< EXMC_NADV connect/disconnect */
|
|
||||||
|
|
||||||
/* constants definitions */
|
|
||||||
typedef FlagStatus bit_status;
|
|
||||||
|
|
||||||
/* GPIO mode values set */
|
|
||||||
#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (4U * (n))))
|
|
||||||
#define GPIO_MODE_MASK(n) (0xFU << (4U * (n)))
|
|
||||||
|
|
||||||
/* GPIO mode definitions */
|
|
||||||
#define GPIO_MODE_AIN ((uint8_t)0x00U) /*!< analog input mode */
|
|
||||||
#define GPIO_MODE_IN_FLOATING ((uint8_t)0x04U) /*!< floating input mode */
|
|
||||||
#define GPIO_MODE_IPD ((uint8_t)0x28U) /*!< pull-down input mode */
|
|
||||||
#define GPIO_MODE_IPU ((uint8_t)0x48U) /*!< pull-up input mode */
|
|
||||||
#define GPIO_MODE_OUT_OD ((uint8_t)0x14U) /*!< GPIO output with open-drain */
|
|
||||||
#define GPIO_MODE_OUT_PP ((uint8_t)0x10U) /*!< GPIO output with push-pull */
|
|
||||||
#define GPIO_MODE_AF_OD ((uint8_t)0x1CU) /*!< AFIO output with open-drain */
|
|
||||||
#define GPIO_MODE_AF_PP ((uint8_t)0x18U) /*!< AFIO output with push-pull */
|
|
||||||
|
|
||||||
/* GPIO output max speed value */
|
|
||||||
#define GPIO_OSPEED_10MHZ ((uint8_t)0x01U) /*!< output max speed 10MHz */
|
|
||||||
#define GPIO_OSPEED_2MHZ ((uint8_t)0x02U) /*!< output max speed 2MHz */
|
|
||||||
#define GPIO_OSPEED_50MHZ ((uint8_t)0x03U) /*!< output max speed 50MHz */
|
|
||||||
|
|
||||||
/* GPIO event output port definitions */
|
|
||||||
#define GPIO_EVENT_PORT_GPIOA ((uint8_t)0x00U) /*!< event output port A */
|
|
||||||
#define GPIO_EVENT_PORT_GPIOB ((uint8_t)0x01U) /*!< event output port B */
|
|
||||||
#define GPIO_EVENT_PORT_GPIOC ((uint8_t)0x02U) /*!< event output port C */
|
|
||||||
#define GPIO_EVENT_PORT_GPIOD ((uint8_t)0x03U) /*!< event output port D */
|
|
||||||
#define GPIO_EVENT_PORT_GPIOE ((uint8_t)0x04U) /*!< event output port E */
|
|
||||||
|
|
||||||
/* GPIO output port source definitions */
|
|
||||||
#define GPIO_PORT_SOURCE_GPIOA ((uint8_t)0x00U) /*!< output port source A */
|
|
||||||
#define GPIO_PORT_SOURCE_GPIOB ((uint8_t)0x01U) /*!< output port source B */
|
|
||||||
#define GPIO_PORT_SOURCE_GPIOC ((uint8_t)0x02U) /*!< output port source C */
|
|
||||||
#define GPIO_PORT_SOURCE_GPIOD ((uint8_t)0x03U) /*!< output port source D */
|
|
||||||
#define GPIO_PORT_SOURCE_GPIOE ((uint8_t)0x04U) /*!< output port source E */
|
|
||||||
|
|
||||||
/* GPIO event output pin definitions */
|
|
||||||
#define GPIO_EVENT_PIN_0 ((uint8_t)0x00U) /*!< GPIO event pin 0 */
|
|
||||||
#define GPIO_EVENT_PIN_1 ((uint8_t)0x01U) /*!< GPIO event pin 1 */
|
|
||||||
#define GPIO_EVENT_PIN_2 ((uint8_t)0x02U) /*!< GPIO event pin 2 */
|
|
||||||
#define GPIO_EVENT_PIN_3 ((uint8_t)0x03U) /*!< GPIO event pin 3 */
|
|
||||||
#define GPIO_EVENT_PIN_4 ((uint8_t)0x04U) /*!< GPIO event pin 4 */
|
|
||||||
#define GPIO_EVENT_PIN_5 ((uint8_t)0x05U) /*!< GPIO event pin 5 */
|
|
||||||
#define GPIO_EVENT_PIN_6 ((uint8_t)0x06U) /*!< GPIO event pin 6 */
|
|
||||||
#define GPIO_EVENT_PIN_7 ((uint8_t)0x07U) /*!< GPIO event pin 7 */
|
|
||||||
#define GPIO_EVENT_PIN_8 ((uint8_t)0x08U) /*!< GPIO event pin 8 */
|
|
||||||
#define GPIO_EVENT_PIN_9 ((uint8_t)0x09U) /*!< GPIO event pin 9 */
|
|
||||||
#define GPIO_EVENT_PIN_10 ((uint8_t)0x0AU) /*!< GPIO event pin 10 */
|
|
||||||
#define GPIO_EVENT_PIN_11 ((uint8_t)0x0BU) /*!< GPIO event pin 11 */
|
|
||||||
#define GPIO_EVENT_PIN_12 ((uint8_t)0x0CU) /*!< GPIO event pin 12 */
|
|
||||||
#define GPIO_EVENT_PIN_13 ((uint8_t)0x0DU) /*!< GPIO event pin 13 */
|
|
||||||
#define GPIO_EVENT_PIN_14 ((uint8_t)0x0EU) /*!< GPIO event pin 14 */
|
|
||||||
#define GPIO_EVENT_PIN_15 ((uint8_t)0x0FU) /*!< GPIO event pin 15 */
|
|
||||||
|
|
||||||
/* GPIO output pin source definitions */
|
|
||||||
#define GPIO_PIN_SOURCE_0 ((uint8_t)0x00U) /*!< GPIO pin source 0 */
|
|
||||||
#define GPIO_PIN_SOURCE_1 ((uint8_t)0x01U) /*!< GPIO pin source 1 */
|
|
||||||
#define GPIO_PIN_SOURCE_2 ((uint8_t)0x02U) /*!< GPIO pin source 2 */
|
|
||||||
#define GPIO_PIN_SOURCE_3 ((uint8_t)0x03U) /*!< GPIO pin source 3 */
|
|
||||||
#define GPIO_PIN_SOURCE_4 ((uint8_t)0x04U) /*!< GPIO pin source 4 */
|
|
||||||
#define GPIO_PIN_SOURCE_5 ((uint8_t)0x05U) /*!< GPIO pin source 5 */
|
|
||||||
#define GPIO_PIN_SOURCE_6 ((uint8_t)0x06U) /*!< GPIO pin source 6 */
|
|
||||||
#define GPIO_PIN_SOURCE_7 ((uint8_t)0x07U) /*!< GPIO pin source 7 */
|
|
||||||
#define GPIO_PIN_SOURCE_8 ((uint8_t)0x08U) /*!< GPIO pin source 8 */
|
|
||||||
#define GPIO_PIN_SOURCE_9 ((uint8_t)0x09U) /*!< GPIO pin source 9 */
|
|
||||||
#define GPIO_PIN_SOURCE_10 ((uint8_t)0x0AU) /*!< GPIO pin source 10 */
|
|
||||||
#define GPIO_PIN_SOURCE_11 ((uint8_t)0x0BU) /*!< GPIO pin source 11 */
|
|
||||||
#define GPIO_PIN_SOURCE_12 ((uint8_t)0x0CU) /*!< GPIO pin source 12 */
|
|
||||||
#define GPIO_PIN_SOURCE_13 ((uint8_t)0x0DU) /*!< GPIO pin source 13 */
|
|
||||||
#define GPIO_PIN_SOURCE_14 ((uint8_t)0x0EU) /*!< GPIO pin source 14 */
|
|
||||||
#define GPIO_PIN_SOURCE_15 ((uint8_t)0x0FU) /*!< GPIO pin source 15 */
|
|
||||||
|
|
||||||
/* GPIO pin definitions */
|
|
||||||
#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */
|
|
||||||
#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */
|
|
||||||
#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */
|
|
||||||
#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */
|
|
||||||
#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */
|
|
||||||
#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */
|
|
||||||
#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */
|
|
||||||
#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */
|
|
||||||
#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */
|
|
||||||
#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */
|
|
||||||
#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */
|
|
||||||
#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */
|
|
||||||
#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */
|
|
||||||
#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */
|
|
||||||
#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */
|
|
||||||
#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */
|
|
||||||
#define GPIO_PIN_ALL BITS(0, 15) /*!< GPIO pin all */
|
|
||||||
|
|
||||||
/* GPIO remap definitions */
|
|
||||||
#define GPIO_SPI0_REMAP ((uint32_t)0x00000001U) /*!< SPI0 remapping */
|
|
||||||
#define GPIO_I2C0_REMAP ((uint32_t)0x00000002U) /*!< I2C0 remapping */
|
|
||||||
#define GPIO_USART0_REMAP ((uint32_t)0x00000004U) /*!< USART0 remapping */
|
|
||||||
#define GPIO_USART1_REMAP ((uint32_t)0x00000008U) /*!< USART1 remapping */
|
|
||||||
#define GPIO_USART2_PARTIAL_REMAP ((uint32_t)0x00140010U) /*!< USART2 partial remapping */
|
|
||||||
#define GPIO_USART2_FULL_REMAP ((uint32_t)0x00140030U) /*!< USART2 full remapping */
|
|
||||||
#define GPIO_TIMER0_PARTIAL_REMAP ((uint32_t)0x00160040U) /*!< TIMER0 partial remapping */
|
|
||||||
#define GPIO_TIMER0_FULL_REMAP ((uint32_t)0x001600C0U) /*!< TIMER0 full remapping */
|
|
||||||
#define GPIO_TIMER1_PARTIAL_REMAP0 ((uint32_t)0x00180100U) /*!< TIMER1 partial remapping */
|
|
||||||
#define GPIO_TIMER1_PARTIAL_REMAP1 ((uint32_t)0x00180200U) /*!< TIMER1 partial remapping */
|
|
||||||
#define GPIO_TIMER1_FULL_REMAP ((uint32_t)0x00180300U) /*!< TIMER1 full remapping */
|
|
||||||
#define GPIO_TIMER2_PARTIAL_REMAP ((uint32_t)0x001A0800U) /*!< TIMER2 partial remapping */
|
|
||||||
#define GPIO_TIMER2_FULL_REMAP ((uint32_t)0x001A0C00U) /*!< TIMER2 full remapping */
|
|
||||||
#define GPIO_TIMER3_REMAP ((uint32_t)0x00001000U) /*!< TIMER3 remapping */
|
|
||||||
#define GPIO_CAN0_PARTIAL_REMAP ((uint32_t)0x001D4000U) /*!< CAN0 partial remapping */
|
|
||||||
#define GPIO_CAN0_FULL_REMAP ((uint32_t)0x001D6000U) /*!< CAN0 full remapping */
|
|
||||||
#define GPIO_PD01_REMAP ((uint32_t)0x00008000U) /*!< PD01 remapping */
|
|
||||||
#define GPIO_TIMER4CH3_IREMAP ((uint32_t)0x00200001U) /*!< TIMER4 channel3 internal remapping */
|
|
||||||
#define GPIO_CAN1_REMAP ((uint32_t)0x00200040U) /*!< CAN1 remapping */
|
|
||||||
#define GPIO_SWJ_NONJTRST_REMAP ((uint32_t)0x00300100U) /*!< JTAG-DP,but without NJTRST */
|
|
||||||
#define GPIO_SWJ_DISABLE_REMAP ((uint32_t)0x00300200U) /*!< JTAG-DP disabled */
|
|
||||||
#define GPIO_SPI2_REMAP ((uint32_t)0x00201100U) /*!< SPI2 remapping */
|
|
||||||
#define GPIO_TIMER1ITI1_REMAP ((uint32_t)0x00202000U) /*!< TIMER1 internal trigger 1 remapping */
|
|
||||||
#define GPIO_EXMC_NADV_REMAP ((uint32_t)0x80000400U) /*!< EXMC_NADV connect/disconnect */
|
|
||||||
|
|
||||||
/* function declarations */
|
|
||||||
/* reset GPIO port */
|
|
||||||
void gpio_deinit(uint32_t gpio_periph);
|
|
||||||
/* reset alternate function I/O(AFIO) */
|
|
||||||
void gpio_afio_deinit(void);
|
|
||||||
/* GPIO parameter initialization */
|
|
||||||
void gpio_init(uint32_t gpio_periph,uint32_t mode,uint32_t speed,uint32_t pin);
|
|
||||||
|
|
||||||
/* set GPIO pin bit */
|
|
||||||
void gpio_bit_set(uint32_t gpio_periph, uint32_t pin);
|
|
||||||
/* reset GPIO pin bit */
|
|
||||||
void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin);
|
|
||||||
/* write data to the specified GPIO pin */
|
|
||||||
void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value);
|
|
||||||
/* write data to the specified GPIO port */
|
|
||||||
void gpio_port_write(uint32_t gpio_periph, uint16_t data);
|
|
||||||
|
|
||||||
/* get GPIO pin input status */
|
|
||||||
FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin);
|
|
||||||
/* get GPIO port input status */
|
|
||||||
uint16_t gpio_input_port_get(uint32_t gpio_periph);
|
|
||||||
/* get GPIO pin output status */
|
|
||||||
FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin);
|
|
||||||
/* get GPIO port output status */
|
|
||||||
uint16_t gpio_output_port_get(uint32_t gpio_periph);
|
|
||||||
|
|
||||||
/* configure GPIO pin remap */
|
|
||||||
void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue);
|
|
||||||
|
|
||||||
/* select GPIO pin exti sources */
|
|
||||||
void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin);
|
|
||||||
/* configure GPIO pin event output */
|
|
||||||
void gpio_event_output_config(uint8_t output_port, uint8_t output_pin);
|
|
||||||
/* enable GPIO pin event output */
|
|
||||||
void gpio_event_output_enable(void);
|
|
||||||
/* disable GPIO pin event output */
|
|
||||||
void gpio_event_output_disable(void);
|
|
||||||
|
|
||||||
/* lock GPIO pin bit */
|
|
||||||
void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin);
|
|
||||||
|
|
||||||
#endif /* GD32VF103_GPIO_H */
|
|
||||||
|
|
@ -1,344 +0,0 @@
|
||||||
/*!
|
|
||||||
\file gd32vf103_i2c.h
|
|
||||||
\brief definitions for the I2C
|
|
||||||
|
|
||||||
\version 2019-6-5, V1.0.0, firmware for GD32VF103
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice, this
|
|
||||||
list of conditions and the following disclaimer.
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer in the documentation
|
|
||||||
and/or other materials provided with the distribution.
|
|
||||||
3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
may be used to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
|
||||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
||||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
|
||||||
OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef GD32VF103_I2C_H
|
|
||||||
#define GD32VF103_I2C_H
|
|
||||||
|
|
||||||
#include "gd32vf103.h"
|
|
||||||
#include "gd32vf103_rcu.h"
|
|
||||||
#include "gd32vf103_dbg.h"
|
|
||||||
|
|
||||||
/* I2Cx(x=0,1) definitions */
|
|
||||||
#define I2C0 I2C_BASE /*!< I2C0 base address */
|
|
||||||
#define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */
|
|
||||||
|
|
||||||
/* registers definitions */
|
|
||||||
#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */
|
|
||||||
#define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */
|
|
||||||
#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0*/
|
|
||||||
#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register */
|
|
||||||
#define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register */
|
|
||||||
#define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register 0 */
|
|
||||||
#define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register */
|
|
||||||
#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU) /*!< I2C clock configure register */
|
|
||||||
#define I2C_RT(i2cx) REG32((i2cx) + 0x20U) /*!< I2C rise time register */
|
|
||||||
|
|
||||||
/* bits definitions */
|
|
||||||
/* I2Cx_CTL0 */
|
|
||||||
#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */
|
|
||||||
#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */
|
|
||||||
#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */
|
|
||||||
#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */
|
|
||||||
#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */
|
|
||||||
#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */
|
|
||||||
#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */
|
|
||||||
#define I2C_CTL0_START BIT(8) /*!< start generation */
|
|
||||||
#define I2C_CTL0_STOP BIT(9) /*!< stop generation */
|
|
||||||
#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */
|
|
||||||
#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */
|
|
||||||
#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */
|
|
||||||
#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */
|
|
||||||
#define I2C_CTL0_SRESET BIT(15) /*!< software reset */
|
|
||||||
|
|
||||||
/* I2Cx_CTL1 */
|
|
||||||
#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */
|
|
||||||
#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */
|
|
||||||
#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */
|
|
||||||
#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */
|
|
||||||
#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */
|
|
||||||
#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */
|
|
||||||
|
|
||||||
/* I2Cx_SADDR0 */
|
|
||||||
#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */
|
|
||||||
#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */
|
|
||||||
#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */
|
|
||||||
#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */
|
|
||||||
|
|
||||||
/* I2Cx_SADDR1 */
|
|
||||||
#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */
|
|
||||||
#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */
|
|
||||||
|
|
||||||
/* I2Cx_DATA */
|
|
||||||
#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */
|
|
||||||
|
|
||||||
/* I2Cx_STAT0 */
|
|
||||||
#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */
|
|
||||||
#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */
|
|
||||||
#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */
|
|
||||||
#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */
|
|
||||||
#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */
|
|
||||||
#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */
|
|
||||||
#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */
|
|
||||||
#define I2C_STAT0_BERR BIT(8) /*!< bus error */
|
|
||||||
#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */
|
|
||||||
#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */
|
|
||||||
#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */
|
|
||||||
#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */
|
|
||||||
#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */
|
|
||||||
#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */
|
|
||||||
|
|
||||||
/* I2Cx_STAT1 */
|
|
||||||
#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */
|
|
||||||
#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */
|
|
||||||
#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */
|
|
||||||
#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */
|
|
||||||
#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */
|
|
||||||
#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */
|
|
||||||
#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */
|
|
||||||
#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */
|
|
||||||
|
|
||||||
/* I2Cx_CKCFG */
|
|
||||||
#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */
|
|
||||||
#define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */
|
|
||||||
#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */
|
|
||||||
|
|
||||||
/* I2Cx_RT */
|
|
||||||
#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */
|
|
||||||
|
|
||||||
/* constants definitions */
|
|
||||||
/* define the I2C bit position and its register index offset */
|
|
||||||
#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
|
|
||||||
#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6)))
|
|
||||||
#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
|
|
||||||
#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
|
|
||||||
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
|
|
||||||
#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22)))
|
|
||||||
#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16)
|
|
||||||
|
|
||||||
/* register offset */
|
|
||||||
#define I2C_CTL1_REG_OFFSET 0x04U /*!< CTL1 register offset */
|
|
||||||
#define I2C_STAT0_REG_OFFSET 0x14U /*!< STAT0 register offset */
|
|
||||||
#define I2C_STAT1_REG_OFFSET 0x18U /*!< STAT1 register offset */
|
|
||||||
|
|
||||||
/* I2C flags */
|
|
||||||
typedef enum {
|
|
||||||
/* flags in STAT0 register */
|
|
||||||
I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */
|
|
||||||
I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */
|
|
||||||
I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */
|
|
||||||
I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */
|
|
||||||
I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */
|
|
||||||
I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving */
|
|
||||||
I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */
|
|
||||||
I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */
|
|
||||||
I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */
|
|
||||||
I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */
|
|
||||||
I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */
|
|
||||||
I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */
|
|
||||||
I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */
|
|
||||||
I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */
|
|
||||||
/* flags in STAT1 register */
|
|
||||||
I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */
|
|
||||||
I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */
|
|
||||||
I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */
|
|
||||||
I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */
|
|
||||||
I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */
|
|
||||||
I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */
|
|
||||||
I2C_FLAG_DUMODF = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */
|
|
||||||
} i2c_flag_enum;
|
|
||||||
|
|
||||||
/* I2C interrupt flags */
|
|
||||||
typedef enum {
|
|
||||||
/* interrupt flags in CTL1 register */
|
|
||||||
I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */
|
|
||||||
I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */
|
|
||||||
I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */
|
|
||||||
I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */
|
|
||||||
I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */
|
|
||||||
I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */
|
|
||||||
I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */
|
|
||||||
I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */
|
|
||||||
I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */
|
|
||||||
I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */
|
|
||||||
I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */
|
|
||||||
I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */
|
|
||||||
I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */
|
|
||||||
I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */
|
|
||||||
} i2c_interrupt_flag_enum;
|
|
||||||
|
|
||||||
/* I2C interrupt enable or disable */
|
|
||||||
typedef enum {
|
|
||||||
/* interrupt in CTL1 register */
|
|
||||||
I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */
|
|
||||||
I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */
|
|
||||||
I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */
|
|
||||||
} i2c_interrupt_enum;
|
|
||||||
|
|
||||||
/* SMBus/I2C mode switch and SMBus type selection */
|
|
||||||
#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */
|
|
||||||
#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */
|
|
||||||
|
|
||||||
/* SMBus/I2C mode switch and SMBus type selection */
|
|
||||||
#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */
|
|
||||||
#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */
|
|
||||||
|
|
||||||
/* I2C transfer direction */
|
|
||||||
#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */
|
|
||||||
#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */
|
|
||||||
|
|
||||||
/* whether or not to send an ACK */
|
|
||||||
#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */
|
|
||||||
#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */
|
|
||||||
|
|
||||||
/* I2C POAP position*/
|
|
||||||
#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */
|
|
||||||
#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */
|
|
||||||
|
|
||||||
/* I2C dual-address mode switch */
|
|
||||||
#define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U) /*!< dual-address mode disabled */
|
|
||||||
#define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U) /*!< dual-address mode enabled */
|
|
||||||
|
|
||||||
/* whether or not to stretch SCL low */
|
|
||||||
#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is enabled */
|
|
||||||
#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< SCL stretching is disabled */
|
|
||||||
|
|
||||||
/* whether or not to response to a general call */
|
|
||||||
#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */
|
|
||||||
#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */
|
|
||||||
|
|
||||||
/* software reset I2C */
|
|
||||||
#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */
|
|
||||||
#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */
|
|
||||||
|
|
||||||
/* I2C DMA mode configure */
|
|
||||||
/* DMA mode switch */
|
|
||||||
#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */
|
|
||||||
#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */
|
|
||||||
|
|
||||||
/* flag indicating DMA last transfer */
|
|
||||||
#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */
|
|
||||||
#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */
|
|
||||||
|
|
||||||
/* I2C PEC configure */
|
|
||||||
/* PEC enable */
|
|
||||||
#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */
|
|
||||||
#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */
|
|
||||||
|
|
||||||
/* PEC transfer */
|
|
||||||
#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */
|
|
||||||
#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */
|
|
||||||
|
|
||||||
/* I2C SMBus configure */
|
|
||||||
/* issue or not alert through SMBA pin */
|
|
||||||
#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */
|
|
||||||
#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */
|
|
||||||
|
|
||||||
/* ARP protocol in SMBus switch */
|
|
||||||
#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP enable */
|
|
||||||
#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP disable */
|
|
||||||
|
|
||||||
/* transmit I2C data */
|
|
||||||
#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
|
|
||||||
|
|
||||||
/* receive I2C data */
|
|
||||||
#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7)
|
|
||||||
|
|
||||||
/* I2C duty cycle in fast mode */
|
|
||||||
#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< I2C fast mode Tlow/Thigh = 2 */
|
|
||||||
#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< I2C fast mode Tlow/Thigh = 16/9 */
|
|
||||||
|
|
||||||
/* address mode for the I2C slave */
|
|
||||||
#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */
|
|
||||||
#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */
|
|
||||||
|
|
||||||
/* function declarations */
|
|
||||||
/* reset I2C */
|
|
||||||
void i2c_deinit(uint32_t i2c_periph);
|
|
||||||
/* configure I2C clock */
|
|
||||||
void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc);
|
|
||||||
/* configure I2C address */
|
|
||||||
void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode,uint32_t addformat, uint32_t addr);
|
|
||||||
/* SMBus type selection */
|
|
||||||
void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type);
|
|
||||||
/* whether or not to send an ACK */
|
|
||||||
void i2c_ack_config(uint32_t i2c_periph, uint32_t ack);
|
|
||||||
/* configure I2C POAP position */
|
|
||||||
void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos);
|
|
||||||
/* master sends slave address */
|
|
||||||
void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr,uint32_t trandirection);
|
|
||||||
/* configure I2C saddress1 */
|
|
||||||
void i2c_saddr1_config(uint32_t i2c_periph,uint32_t addr);
|
|
||||||
/* enable dual-address mode */
|
|
||||||
void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr);
|
|
||||||
/* disable dual-address mode */
|
|
||||||
void i2c_dualaddr_disable(uint32_t i2c_periph);
|
|
||||||
/* enable I2C */
|
|
||||||
void i2c_enable(uint32_t i2c_periph);
|
|
||||||
/* disable I2C */
|
|
||||||
void i2c_disable(uint32_t i2c_periph);
|
|
||||||
|
|
||||||
/* generate a START condition on I2C bus */
|
|
||||||
void i2c_start_on_bus(uint32_t i2c_periph);
|
|
||||||
/* generate a STOP condition on I2C bus */
|
|
||||||
void i2c_stop_on_bus(uint32_t i2c_periph);
|
|
||||||
/* I2C transmit data function */
|
|
||||||
void i2c_data_transmit(uint32_t i2c_periph, uint8_t data);
|
|
||||||
/* I2C receive data function */
|
|
||||||
uint8_t i2c_data_receive(uint32_t i2c_periph);
|
|
||||||
/* enable I2C DMA mode */
|
|
||||||
void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate);
|
|
||||||
/* configure whether next DMA EOT is DMA last transfer or not */
|
|
||||||
void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast);
|
|
||||||
/* whether to stretch SCL low when data is not ready in slave mode */
|
|
||||||
void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara);
|
|
||||||
/* whether or not to response to a general call */
|
|
||||||
void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara);
|
|
||||||
/* software reset I2C */
|
|
||||||
void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset);
|
|
||||||
|
|
||||||
/* I2C PEC calculation on or off */
|
|
||||||
void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate);
|
|
||||||
/* I2C whether to transfer PEC value */
|
|
||||||
void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara);
|
|
||||||
/* packet error checking value */
|
|
||||||
uint8_t i2c_pec_value_get(uint32_t i2c_periph);
|
|
||||||
/* I2C issue alert through SMBA pin */
|
|
||||||
void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara);
|
|
||||||
/* I2C ARP protocol in SMBus switch */
|
|
||||||
void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate);
|
|
||||||
|
|
||||||
/* check I2C flag is set or not */
|
|
||||||
FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag);
|
|
||||||
/* clear I2C flag */
|
|
||||||
void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag);
|
|
||||||
/* enable I2C interrupt */
|
|
||||||
void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
|
|
||||||
/* disable I2C interrupt */
|
|
||||||
void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
|
|
||||||
/* check I2C interrupt flag */
|
|
||||||
FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph,i2c_interrupt_flag_enum int_flag);
|
|
||||||
/* clear I2C interrupt flag */
|
|
||||||
void i2c_interrupt_flag_clear(uint32_t i2c_periph,i2c_interrupt_flag_enum int_flag);
|
|
||||||
|
|
||||||
#endif /* GD32VF103_I2C_H */
|
|
||||||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue