From db7d641c223db8ab25501d79c2a6331f743d830b Mon Sep 17 00:00:00 2001 From: Haryslee Date: Thu, 10 Feb 2022 21:43:31 +0800 Subject: [PATCH] =?UTF-8?q?feat:=20cortex-m55=E6=94=AF=E6=8C=81psplimit?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit cortex-m55增加栈溢出检测特性 close #I4T7R3 Signed-off-by: Haryslee Change-Id: Ie24adbb672c47404b56aa5bfc9f22e0f7f947540 --- .../arm/cortex-m55/gcc/NTZ/los_arch_context.h | 3 +- .../cortex-m55/gcc/NTZ/los_arch_interrupt.h | 61 ++++++++++++------- arch/arm/cortex-m55/gcc/NTZ/los_context.c | 5 +- arch/arm/cortex-m55/gcc/NTZ/los_dispatch.S | 12 ++-- arch/arm/cortex-m55/gcc/NTZ/los_exc.S | 10 +-- arch/arm/cortex-m55/gcc/NTZ/los_interrupt.c | 12 ++-- 6 files changed, 64 insertions(+), 39 deletions(-) diff --git a/arch/arm/cortex-m55/gcc/NTZ/los_arch_context.h b/arch/arm/cortex-m55/gcc/NTZ/los_arch_context.h index 4caf6de5..47e3f132 100755 --- a/arch/arm/cortex-m55/gcc/NTZ/los_arch_context.h +++ b/arch/arm/cortex-m55/gcc/NTZ/los_arch_context.h @@ -41,7 +41,8 @@ extern "C" { #endif /* __cplusplus */ typedef struct TagTskContext { - UINT32 uwEXCLR; + UINT32 uwPspLim; + UINT32 uwExcLR; UINT32 uwR4; UINT32 uwR5; UINT32 uwR6; diff --git a/arch/arm/cortex-m55/gcc/NTZ/los_arch_interrupt.h b/arch/arm/cortex-m55/gcc/NTZ/los_arch_interrupt.h index 568e4525..4838306b 100755 --- a/arch/arm/cortex-m55/gcc/NTZ/los_arch_interrupt.h +++ b/arch/arm/cortex-m55/gcc/NTZ/los_arch_interrupt.h @@ -505,133 +505,150 @@ VOID HalExcUsageFault(VOID); VOID HalSVCHandler(VOID); VOID HalHwiInit(VOID); +/** + * @ingroup los_exc + * Cortex-M exception types: Record whether a precise BusFault occurred during floating-point lazy state preservation. + */ +#define OS_EXC_BF_LSPERR 1 + /** * @ingroup los_exc * Cortex-M exception types: An error occurred while the bus status register was being pushed. */ -#define OS_EXC_BF_STKERR 1 +#define OS_EXC_BF_STKERR 2 /** * @ingroup los_exc * Cortex-M exception types: An error occurred while the bus status register was out of the stack. */ -#define OS_EXC_BF_UNSTKERR 2 +#define OS_EXC_BF_UNSTKERR 3 /** * @ingroup los_exc * Cortex-M exception types: Bus status register imprecise data access violation. */ -#define OS_EXC_BF_IMPRECISERR 3 +#define OS_EXC_BF_IMPRECISERR 4 /** * @ingroup los_exc * Cortex-M exception types: Bus status register exact data access violation. */ -#define OS_EXC_BF_PRECISERR 4 +#define OS_EXC_BF_PRECISERR 5 /** * @ingroup los_exc * Cortex-M exception types: Bus status register access violation while pointing. */ -#define OS_EXC_BF_IBUSERR 5 +#define OS_EXC_BF_IBUSERR 6 + +/** + * @ingroup los_exc + * Cortex-M exception types: Record whether a MemManage fault occurred during floating-point lazy state preservation. + */ +#define OS_EXC_MF_MLSPERR 7 /** * @ingroup los_exc * Cortex-M exception types: An error occurred while the memory management status register was being pushed. */ -#define OS_EXC_MF_MSTKERR 6 +#define OS_EXC_MF_MSTKERR 8 /** * @ingroup los_exc * Cortex-M exception types: An error occurred while the memory management status register was out of the stack. */ -#define OS_EXC_MF_MUNSTKERR 7 +#define OS_EXC_MF_MUNSTKERR 9 /** * @ingroup los_exc * Cortex-M exception types: Memory management status register data access violation. */ -#define OS_EXC_MF_DACCVIOL 8 +#define OS_EXC_MF_DACCVIOL 10 /** * @ingroup los_exc * Cortex-M exception types: Memory management status register access violation. */ -#define OS_EXC_MF_IACCVIOL 9 - +#define OS_EXC_MF_IACCVIOL 11 /** * @ingroup los_exc * Cortex-M exception types: Incorrect usage indicating that the divisor is zero during the division operation. */ -#define OS_EXC_UF_DIVBYZERO 10 +#define OS_EXC_UF_DIVBYZERO 12 /** * @ingroup los_exc * Cortex-M exception types: Usage error, error caused by unaligned access. */ -#define OS_EXC_UF_UNALIGNED 11 +#define OS_EXC_UF_UNALIGNED 13 + +/** + * @ingroup los_exc + * Cortex-M exception types: Sticky flag indicating whether a stack overflow error has occurred. + */ +#define OS_EXC_UF_STKOF 14 /** * @ingroup los_exc * Cortex-M exception types: Incorrect usage attempting to execute coprocessor related instruction. */ -#define OS_EXC_UF_NOCP 12 +#define OS_EXC_UF_NOCP 15 /** * @ingroup los_exc * Cortex-M exception types: Usage error attempting to load EXC_RETURN to PC illegally on exception return. */ -#define OS_EXC_UF_INVPC 13 +#define OS_EXC_UF_INVPC 16 /** * @ingroup los_exc * Cortex-M exception types: Incorrect usage, attempting to cut to ARM state. */ -#define OS_EXC_UF_INVSTATE 14 +#define OS_EXC_UF_INVSTATE 17 /** * @ingroup los_exc * Cortex-M exception types: Incorrect usage. Executed instruction whose code is undefined. */ -#define OS_EXC_UF_UNDEFINSTR 15 +#define OS_EXC_UF_UNDEFINSTR 18 /** * @ingroup los_exc * Cortex-M exception types: NMI */ -#define OS_EXC_CAUSE_NMI 16 +#define OS_EXC_CAUSE_NMI 19 /** * @ingroup los_exc * Cortex-M exception types: hard fault */ -#define OS_EXC_CAUSE_HARDFAULT 17 +#define OS_EXC_CAUSE_HARDFAULT 20 /** * @ingroup los_exc * Cortex-M exception types: The task handler exits. */ -#define OS_EXC_CAUSE_TASK_EXIT 18 +#define OS_EXC_CAUSE_TASK_EXIT 21 /** * @ingroup los_exc * Cortex-M exception types: A fatal error. */ -#define OS_EXC_CAUSE_FATAL_ERR 19 +#define OS_EXC_CAUSE_FATAL_ERR 22 /** * @ingroup los_exc * Cortex-M exception types: Hard Fault caused by a debug event. */ -#define OS_EXC_CAUSE_DEBUGEVT 20 +#define OS_EXC_CAUSE_DEBUGEVT 23 /** * @ingroup los_exc * Cortex-M exception types: A hard fault that occurs when a quantity is oriented. */ -#define OS_EXC_CAUSE_VECTBL 21 +#define OS_EXC_CAUSE_VECTBL 24 /** * @ingroup los_exc diff --git a/arch/arm/cortex-m55/gcc/NTZ/los_context.c b/arch/arm/cortex-m55/gcc/NTZ/los_context.c index a920c676..3ee56f82 100755 --- a/arch/arm/cortex-m55/gcc/NTZ/los_context.c +++ b/arch/arm/cortex-m55/gcc/NTZ/los_context.c @@ -112,10 +112,11 @@ LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VO context->S15 = 0xAA00000F; context->FPSCR = 0x00000000; context->NO_NAME = 0xAA000011; - context->uwEXCLR = 0xFFFFFFEDL; + context->uwExcLR = 0xFFFFFFEDL; #else - context->uwEXCLR = 0xFFFFFFFDL; + context->uwExcLR = 0xFFFFFFFDL; #endif + context->uwPspLim = (UINT32)topStack; context->uwR4 = 0x04040404L; context->uwR5 = 0x05050505L; context->uwR6 = 0x06060606L; diff --git a/arch/arm/cortex-m55/gcc/NTZ/los_dispatch.S b/arch/arm/cortex-m55/gcc/NTZ/los_dispatch.S index b8afd980..a1545c96 100755 --- a/arch/arm/cortex-m55/gcc/NTZ/los_dispatch.S +++ b/arch/arm/cortex-m55/gcc/NTZ/los_dispatch.S @@ -67,12 +67,12 @@ HalStartToRun: ldr r0, [r1, #4] ldr r12, [r0] - ldr r2, [r12] + ldr r2, [r12, #4] tst r2, #0x10 it ne bne __DisabledFPU - add r12, r12, #104 + add r12, r12, #108 ldmfd r12!, {r0-r7} add r12, r12, #72 msr psp, r12 @@ -84,7 +84,7 @@ HalStartToRun: bx r6 __DisabledFPU: - add r12, r12, #40 + add r12, r12, #44 ldmfd r12!, {r0-r7} msr psp, r12 @@ -166,8 +166,9 @@ TaskContextSwitch: tst lr, #0x10 it eq vstmdbeq r0!, {d8-d15} + mrs r2, psplim mov r3, lr - stmfd r0!, {r3-r12} + stmfd r0!, {r2-r12} ldr r5, =g_losTask ldr r6, [r5] @@ -178,7 +179,8 @@ TaskContextSwitch: ldr r1, [r0] SignalContextRestore: - ldmfd r1!, {r3-r12} + ldmfd r1!, {r2-r12} + msr psplim, r2 tst r3, #0x10 it eq vldmiaeq r1!, {d8-d15} diff --git a/arch/arm/cortex-m55/gcc/NTZ/los_exc.S b/arch/arm/cortex-m55/gcc/NTZ/los_exc.S index 2668ddac..c23af56f 100755 --- a/arch/arm/cortex-m55/gcc/NTZ/los_exc.S +++ b/arch/arm/cortex-m55/gcc/NTZ/los_exc.S @@ -46,11 +46,11 @@ .extern g_taskScheduled .equ OS_FLG_BGD_ACTIVE, 0x0002 -.equ OS_EXC_CAUSE_NMI, 16 -.equ OS_EXC_CAUSE_HARDFAULT, 17 +.equ OS_EXC_CAUSE_NMI, 19 +.equ OS_EXC_CAUSE_HARDFAULT, 20 -.equ HF_DEBUGEVT, 20 -.equ HF_VECTBL, 21 +.equ HF_DEBUGEVT, 23 +.equ HF_VECTBL, 24 .equ FLAG_ADDR_VALID, 0x10000 .equ FLAG_HWI_ACTIVE, 0x20000 @@ -222,7 +222,7 @@ HalExcUsageFault: LDR R0, =OS_NVIC_FSR LDR R0, [R0] - MOVW R1, #0x030F + MOVW R1, #0x031F LSL R1, R1, #16 AND R0, R0, R1 MOV R12, #0 diff --git a/arch/arm/cortex-m55/gcc/NTZ/los_interrupt.c b/arch/arm/cortex-m55/gcc/NTZ/los_interrupt.c index 86bef8ac..7a882269 100755 --- a/arch/arm/cortex-m55/gcc/NTZ/los_interrupt.c +++ b/arch/arm/cortex-m55/gcc/NTZ/los_interrupt.c @@ -342,10 +342,14 @@ LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum) ExcInfo g_excInfo = {0}; UINT8 g_uwExcTbl[FAULT_STATUS_REG_BIT] = { - 0, 0, 0, 0, 0, 0, OS_EXC_UF_DIVBYZERO, OS_EXC_UF_UNALIGNED, - 0, 0, 0, 0, OS_EXC_UF_NOCP, OS_EXC_UF_INVPC, OS_EXC_UF_INVSTATE, OS_EXC_UF_UNDEFINSTR, - 0, 0, 0, OS_EXC_BF_STKERR, OS_EXC_BF_UNSTKERR, OS_EXC_BF_IMPRECISERR, OS_EXC_BF_PRECISERR, OS_EXC_BF_IBUSERR, - 0, 0, 0, OS_EXC_MF_MSTKERR, OS_EXC_MF_MUNSTKERR, 0, OS_EXC_MF_DACCVIOL, OS_EXC_MF_IACCVIOL + 0, 0, 0, 0, + 0, 0, OS_EXC_UF_DIVBYZERO, OS_EXC_UF_UNALIGNED, + 0, 0, 0, OS_EXC_UF_STKOF, + OS_EXC_UF_NOCP, OS_EXC_UF_INVPC, OS_EXC_UF_INVSTATE, OS_EXC_UF_UNDEFINSTR, + 0, 0, OS_EXC_BF_LSPERR, OS_EXC_BF_STKERR, + OS_EXC_BF_UNSTKERR, OS_EXC_BF_IMPRECISERR, OS_EXC_BF_PRECISERR, OS_EXC_BF_IBUSERR, + 0, 0, OS_EXC_MF_MLSPERR, OS_EXC_MF_MSTKERR, + OS_EXC_MF_MUNSTKERR, 0, OS_EXC_MF_DACCVIOL, OS_EXC_MF_IACCVIOL }; #if (LOSCFG_KERNEL_PRINTF != 0)