diff --git a/arch/risc-v/riscv32/gcc/asm/soc_common.h b/arch/risc-v/riscv32/gcc/asm/soc_common.h
index 7032ada1..10bea9fc 100644
--- a/arch/risc-v/riscv32/gcc/asm/soc_common.h
+++ b/arch/risc-v/riscv32/gcc/asm/soc_common.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2013-2020, Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -63,6 +63,9 @@
 #define RISCV_MIE_MEIE                      0x000000800
 
 /************************** mcause ***********************/
+#ifndef MCAUSE_INT_ID_MASK
+#define MCAUSE_INT_ID_MASK                  0x7FFFFFF
+#endif
 #define RISCV_MCAUSE_ECALL_U                8
 
 #define RISCV_USER_SOFT_IRQ                 0
@@ -72,7 +75,6 @@
 #define RISCV_USER_EXT_IRQ                  8
 #define RISCV_MACH_EXT_IRQ                  11
 
-
 #define READ_CSR(reg) ({                                          \
     UINT32 _tmp;                                                  \
     __asm__ volatile("csrr %0, " #reg : "=r"(_tmp) : : "memory"); \
diff --git a/arch/risc-v/riscv32/gcc/los_context.c b/arch/risc-v/riscv32/gcc/los_context.c
index 7f266fbf..31a7ce6b 100644
--- a/arch/risc-v/riscv32/gcc/los_context.c
+++ b/arch/risc-v/riscv32/gcc/los_context.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2013-2020, Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -35,7 +35,7 @@
 #include "los_task.h"
 #include "los_sched.h"
 #include "los_memory.h"
-#include "soc.h"
+#include "soc_common.h"
 
 STATIC UINT32 g_sysNeedSched = FALSE;
 
diff --git a/arch/risc-v/riscv32/gcc/los_dispatch.S b/arch/risc-v/riscv32/gcc/los_dispatch.S
index da2dfe27..9e670ba8 100644
--- a/arch/risc-v/riscv32/gcc/los_dispatch.S
+++ b/arch/risc-v/riscv32/gcc/los_dispatch.S
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2013-2020, Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -29,7 +29,7 @@
  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "soc.h"
+#include "soc_common.h"
 
 .global  HalEnableIRQ
 .global  HalDisableIRQ
diff --git a/arch/risc-v/riscv32/gcc/los_exc.S b/arch/risc-v/riscv32/gcc/los_exc.S
index c4cf2eac..8e5a4fd2 100644
--- a/arch/risc-v/riscv32/gcc/los_exc.S
+++ b/arch/risc-v/riscv32/gcc/los_exc.S
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2013-2020, Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -31,7 +31,7 @@
 
 #ifndef _LOS_EXC_S
 #define _LOS_EXC_S
-#include "soc.h"
+#include "soc_common.h"
 
 .macro PUSH_CALLER_REG
     addi sp, sp, -(32 * REGBYTES)