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fix: 修复los_interrupt.c文件中HalHwiInit函数里未使能未对齐异常问题 

修复los_interrupt.c文件中HalHwiInit函数里未使能未对齐异常问题

close #I4EJGR

Signed-off-by: kenneth <zhushangyuan@huawei.com>
This commit is contained in:
kenneth 2021-10-19 19:45:24 +08:00
parent d8a6a4bdb9
commit d32e25f3ae
8 changed files with 24 additions and 12 deletions
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4
kernel/arch/arm/cortex-m3/keil/los_interrupt.c
View File

@ -273,6 +273,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
#define BUSFAULT (1 << 17) #define BUSFAULT (1 << 17)
#define MEMFAULT (1 << 16) #define MEMFAULT (1 << 16)
#define DIV0FAULT (1 << 4) #define DIV0FAULT (1 << 4)
#define UNALIGNFAULT (1 << 3)
#define HARDFAULT_IRQN (-13) #define HARDFAULT_IRQN (-13)
ExcInfo g_excInfo = {0}; ExcInfo g_excInfo = {0};
@ -520,8 +521,9 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
/* Enable USGFAULT, BUSFAULT, MEMFAULT */ /* Enable USGFAULT, BUSFAULT, MEMFAULT */
*(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT); *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
/* Enable DIV 0 and unaligned exception */ /* Enable DIV 0 and unaligned exception */
*(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT; *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT);
return; return;
} }

4
kernel/arch/arm/cortex-m33/gcc/NTZ/los_interrupt.c
View File

@ -263,6 +263,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
#define BUSFAULT (1 << 17) #define BUSFAULT (1 << 17)
#define MEMFAULT (1 << 16) #define MEMFAULT (1 << 16)
#define DIV0FAULT (1 << 4) #define DIV0FAULT (1 << 4)
#define UNALIGNFAULT (1 << 3)
#define HARDFAULT_IRQN (-13) #define HARDFAULT_IRQN (-13)
ExcInfo g_excInfo = {0}; ExcInfo g_excInfo = {0};
@ -510,8 +511,9 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
/* Enable USGFAULT, BUSFAULT, MEMFAULT */ /* Enable USGFAULT, BUSFAULT, MEMFAULT */
*(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT); *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
/* Enable DIV 0 and unaligned exception */ /* Enable DIV 0 and unaligned exception */
*(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT; *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT);
return; return;
} }

4
kernel/arch/arm/cortex-m33/gcc/TZ/non_secure/los_interrupt.c
View File

@ -263,6 +263,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
#define BUSFAULT (1 << 17) #define BUSFAULT (1 << 17)
#define MEMFAULT (1 << 16) #define MEMFAULT (1 << 16)
#define DIV0FAULT (1 << 4) #define DIV0FAULT (1 << 4)
#define UNALIGNFAULT (1 << 3)
#define HARDFAULT_IRQN (-13) #define HARDFAULT_IRQN (-13)
ExcInfo g_excInfo = {0}; ExcInfo g_excInfo = {0};
@ -510,8 +511,9 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
/* Enable USGFAULT, BUSFAULT, MEMFAULT */ /* Enable USGFAULT, BUSFAULT, MEMFAULT */
*(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT); *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
/* Enable DIV 0 and unaligned exception */ /* Enable DIV 0 and unaligned exception */
*(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT; *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT);
return; return;
} }

4
kernel/arch/arm/cortex-m33/gcc/los_interrupt.c
View File

@ -263,6 +263,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
#define BUSFAULT (1 << 17) #define BUSFAULT (1 << 17)
#define MEMFAULT (1 << 16) #define MEMFAULT (1 << 16)
#define DIV0FAULT (1 << 4) #define DIV0FAULT (1 << 4)
#define UNALIGNFAULT (1 << 3)
#define HARDFAULT_IRQN (-13) #define HARDFAULT_IRQN (-13)
ExcInfo g_excInfo = {0}; ExcInfo g_excInfo = {0};
@ -510,8 +511,9 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
/* Enable USGFAULT, BUSFAULT, MEMFAULT */ /* Enable USGFAULT, BUSFAULT, MEMFAULT */
*(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT); *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
/* Enable DIV 0 and unaligned exception */ /* Enable DIV 0 and unaligned exception */
*(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT; *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT);
return; return;
} }

4
kernel/arch/arm/cortex-m4/gcc/los_interrupt.c
View File

@ -273,6 +273,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
#define BUSFAULT (1 << 17) #define BUSFAULT (1 << 17)
#define MEMFAULT (1 << 16) #define MEMFAULT (1 << 16)
#define DIV0FAULT (1 << 4) #define DIV0FAULT (1 << 4)
#define UNALIGNFAULT (1 << 3)
#define HARDFAULT_IRQN (-13) #define HARDFAULT_IRQN (-13)
ExcInfo g_excInfo = {0}; ExcInfo g_excInfo = {0};
@ -530,8 +531,9 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
/* Enable USGFAULT, BUSFAULT, MEMFAULT */ /* Enable USGFAULT, BUSFAULT, MEMFAULT */
*(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT); *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
/* Enable DIV 0 and unaligned exception */ /* Enable DIV 0 and unaligned exception */
*(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT; *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT);
return; return;
} }

6
kernel/arch/arm/cortex-m4/iar/los_interrupt.c
View File

@ -166,9 +166,7 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
#endif #endif
intSave = LOS_IntLock(); intSave = LOS_IntLock();
g_intCount++; g_intCount++;
LOS_IntRestore(intSave); LOS_IntRestore(intSave);
hwiIndex = HalIntNumGet(); hwiIndex = HalIntNumGet();
@ -276,6 +274,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
#define BUSFAULT (1 << 17) #define BUSFAULT (1 << 17)
#define MEMFAULT (1 << 16) #define MEMFAULT (1 << 16)
#define DIV0FAULT (1 << 4) #define DIV0FAULT (1 << 4)
#define UNALIGNFAULT (1 << 3)
#define HARDFAULT_IRQN (-13) #define HARDFAULT_IRQN (-13)
ExcInfo g_excInfo = {0}; ExcInfo g_excInfo = {0};
@ -523,8 +522,9 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
/* Enable USGFAULT, BUSFAULT, MEMFAULT */ /* Enable USGFAULT, BUSFAULT, MEMFAULT */
*(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT); *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
/* Enable DIV 0 and unaligned exception */ /* Enable DIV 0 and unaligned exception */
*(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT; *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT);
return; return;
} }

4
kernel/arch/arm/cortex-m7/gcc/los_interrupt.c
View File

@ -263,6 +263,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
#define BUSFAULT (1 << 17) #define BUSFAULT (1 << 17)
#define MEMFAULT (1 << 16) #define MEMFAULT (1 << 16)
#define DIV0FAULT (1 << 4) #define DIV0FAULT (1 << 4)
#define UNALIGNFAULT (1 << 3)
#define HARDFAULT_IRQN (-13) #define HARDFAULT_IRQN (-13)
ExcInfo g_excInfo = {0}; ExcInfo g_excInfo = {0};
@ -510,8 +511,9 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
/* Enable USGFAULT, BUSFAULT, MEMFAULT */ /* Enable USGFAULT, BUSFAULT, MEMFAULT */
*(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT); *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
/* Enable DIV 0 and unaligned exception */ /* Enable DIV 0 and unaligned exception */
*(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT; *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT);
return; return;
} }

6
kernel/arch/arm/cortex-m7/iar/los_interrupt.c
View File

@ -162,9 +162,7 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
#endif #endif
intSave = LOS_IntLock(); intSave = LOS_IntLock();
g_intCount++; g_intCount++;
LOS_IntRestore(intSave); LOS_IntRestore(intSave);
hwiIndex = HalIntNumGet(); hwiIndex = HalIntNumGet();
@ -272,6 +270,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
#define BUSFAULT (1 << 17) #define BUSFAULT (1 << 17)
#define MEMFAULT (1 << 16) #define MEMFAULT (1 << 16)
#define DIV0FAULT (1 << 4) #define DIV0FAULT (1 << 4)
#define UNALIGNFAULT (1 << 3)
#define HARDFAULT_IRQN (-13) #define HARDFAULT_IRQN (-13)
ExcInfo g_excInfo = {0}; ExcInfo g_excInfo = {0};
@ -519,8 +518,9 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
/* Enable USGFAULT, BUSFAULT, MEMFAULT */ /* Enable USGFAULT, BUSFAULT, MEMFAULT */
*(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT); *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
/* Enable DIV 0 and unaligned exception */ /* Enable DIV 0 and unaligned exception */
*(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT; *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT);
return; return;
} }