From caa28225a80a4aa58e7446aa431948e193e9ac47 Mon Sep 17 00:00:00 2001 From: kenneth Date: Tue, 19 Oct 2021 19:45:24 +0800 Subject: [PATCH] =?UTF-8?q?fixed=20d32e25f=20from=20https://gitee.com/rtos?= =?UTF-8?q?=5Fyuan/kernel=5Fliteos=5Fm/pulls/362=20fix:=20=E4=BF=AE?= =?UTF-8?q?=E5=A4=8Dlos=5Finterrupt.c=E6=96=87=E4=BB=B6=E4=B8=ADHalHwiInit?= =?UTF-8?q?=E5=87=BD=E6=95=B0=E9=87=8C=E6=9C=AA=E4=BD=BF=E8=83=BD=E6=9C=AA?= =?UTF-8?q?=E5=AF=B9=E9=BD=90=E5=BC=82=E5=B8=B8=E9=97=AE=E9=A2=98?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 修复los_interrupt.c文件中HalHwiInit函数里未使能未对齐异常问题 close #I4EJGR Signed-off-by: kenneth --- kernel/arch/arm/cortex-m3/keil/los_interrupt.c | 8 +++++++- kernel/arch/arm/cortex-m33/gcc/NTZ/los_interrupt.c | 8 +++++++- .../arch/arm/cortex-m33/gcc/TZ/non_secure/los_interrupt.c | 8 +++++++- kernel/arch/arm/cortex-m33/gcc/los_interrupt.c | 8 +++++++- kernel/arch/arm/cortex-m4/gcc/los_interrupt.c | 8 +++++++- kernel/arch/arm/cortex-m4/iar/los_interrupt.c | 8 +++++++- kernel/arch/arm/cortex-m7/gcc/los_interrupt.c | 8 +++++++- kernel/arch/arm/cortex-m7/iar/los_interrupt.c | 8 +++++++- 8 files changed, 56 insertions(+), 8 deletions(-) diff --git a/kernel/arch/arm/cortex-m3/keil/los_interrupt.c b/kernel/arch/arm/cortex-m3/keil/los_interrupt.c index 0dee58cf..e3df1be1 100644 --- a/kernel/arch/arm/cortex-m3/keil/los_interrupt.c +++ b/kernel/arch/arm/cortex-m3/keil/los_interrupt.c @@ -273,6 +273,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum) #define BUSFAULT (1 << 17) #define MEMFAULT (1 << 16) #define DIV0FAULT (1 << 4) +#define UNALIGNFAULT (1 << 3) #define HARDFAULT_IRQN (-13) ExcInfo g_excInfo = {0}; @@ -520,8 +521,13 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit() /* Enable USGFAULT, BUSFAULT, MEMFAULT */ *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT); + /* Enable DIV 0 and unaligned exception */ - *(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT; +#ifdef LOSCFG_ARCH_UNALIGNED_EXC + *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT); +#else + *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT); +#endif return; } diff --git a/kernel/arch/arm/cortex-m33/gcc/NTZ/los_interrupt.c b/kernel/arch/arm/cortex-m33/gcc/NTZ/los_interrupt.c index d1f55b80..9e8ab1fb 100755 --- a/kernel/arch/arm/cortex-m33/gcc/NTZ/los_interrupt.c +++ b/kernel/arch/arm/cortex-m33/gcc/NTZ/los_interrupt.c @@ -263,6 +263,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum) #define BUSFAULT (1 << 17) #define MEMFAULT (1 << 16) #define DIV0FAULT (1 << 4) +#define UNALIGNFAULT (1 << 3) #define HARDFAULT_IRQN (-13) ExcInfo g_excInfo = {0}; @@ -510,8 +511,13 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit() /* Enable USGFAULT, BUSFAULT, MEMFAULT */ *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT); + /* Enable DIV 0 and unaligned exception */ - *(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT; +#ifdef LOSCFG_ARCH_UNALIGNED_EXC + *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT); +#else + *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT); +#endif return; } diff --git a/kernel/arch/arm/cortex-m33/gcc/TZ/non_secure/los_interrupt.c b/kernel/arch/arm/cortex-m33/gcc/TZ/non_secure/los_interrupt.c index d1f55b80..9e8ab1fb 100755 --- a/kernel/arch/arm/cortex-m33/gcc/TZ/non_secure/los_interrupt.c +++ b/kernel/arch/arm/cortex-m33/gcc/TZ/non_secure/los_interrupt.c @@ -263,6 +263,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum) #define BUSFAULT (1 << 17) #define MEMFAULT (1 << 16) #define DIV0FAULT (1 << 4) +#define UNALIGNFAULT (1 << 3) #define HARDFAULT_IRQN (-13) ExcInfo g_excInfo = {0}; @@ -510,8 +511,13 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit() /* Enable USGFAULT, BUSFAULT, MEMFAULT */ *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT); + /* Enable DIV 0 and unaligned exception */ - *(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT; +#ifdef LOSCFG_ARCH_UNALIGNED_EXC + *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT); +#else + *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT); +#endif return; } diff --git a/kernel/arch/arm/cortex-m33/gcc/los_interrupt.c b/kernel/arch/arm/cortex-m33/gcc/los_interrupt.c index c5952da6..51c5d1bd 100644 --- a/kernel/arch/arm/cortex-m33/gcc/los_interrupt.c +++ b/kernel/arch/arm/cortex-m33/gcc/los_interrupt.c @@ -263,6 +263,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum) #define BUSFAULT (1 << 17) #define MEMFAULT (1 << 16) #define DIV0FAULT (1 << 4) +#define UNALIGNFAULT (1 << 3) #define HARDFAULT_IRQN (-13) ExcInfo g_excInfo = {0}; @@ -510,8 +511,13 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit() /* Enable USGFAULT, BUSFAULT, MEMFAULT */ *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT); + /* Enable DIV 0 and unaligned exception */ - *(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT; +#ifdef LOSCFG_ARCH_UNALIGNED_EXC + *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT); +#else + *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT); +#endif return; } diff --git a/kernel/arch/arm/cortex-m4/gcc/los_interrupt.c b/kernel/arch/arm/cortex-m4/gcc/los_interrupt.c index 6ab35187..2f2b3042 100644 --- a/kernel/arch/arm/cortex-m4/gcc/los_interrupt.c +++ b/kernel/arch/arm/cortex-m4/gcc/los_interrupt.c @@ -273,6 +273,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum) #define BUSFAULT (1 << 17) #define MEMFAULT (1 << 16) #define DIV0FAULT (1 << 4) +#define UNALIGNFAULT (1 << 3) #define HARDFAULT_IRQN (-13) ExcInfo g_excInfo = {0}; @@ -530,8 +531,13 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit() /* Enable USGFAULT, BUSFAULT, MEMFAULT */ *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT); + /* Enable DIV 0 and unaligned exception */ - *(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT; +#ifdef LOSCFG_ARCH_UNALIGNED_EXC + *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT); +#else + *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT); +#endif return; } diff --git a/kernel/arch/arm/cortex-m4/iar/los_interrupt.c b/kernel/arch/arm/cortex-m4/iar/los_interrupt.c index cd7ff15c..4447c68d 100644 --- a/kernel/arch/arm/cortex-m4/iar/los_interrupt.c +++ b/kernel/arch/arm/cortex-m4/iar/los_interrupt.c @@ -276,6 +276,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum) #define BUSFAULT (1 << 17) #define MEMFAULT (1 << 16) #define DIV0FAULT (1 << 4) +#define UNALIGNFAULT (1 << 3) #define HARDFAULT_IRQN (-13) ExcInfo g_excInfo = {0}; @@ -523,8 +524,13 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit() /* Enable USGFAULT, BUSFAULT, MEMFAULT */ *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT); + /* Enable DIV 0 and unaligned exception */ - *(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT; +#ifdef LOSCFG_ARCH_UNALIGNED_EXC + *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT); +#else + *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT); +#endif return; } diff --git a/kernel/arch/arm/cortex-m7/gcc/los_interrupt.c b/kernel/arch/arm/cortex-m7/gcc/los_interrupt.c index e1eb52e3..77b01445 100644 --- a/kernel/arch/arm/cortex-m7/gcc/los_interrupt.c +++ b/kernel/arch/arm/cortex-m7/gcc/los_interrupt.c @@ -263,6 +263,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum) #define BUSFAULT (1 << 17) #define MEMFAULT (1 << 16) #define DIV0FAULT (1 << 4) +#define UNALIGNFAULT (1 << 3) #define HARDFAULT_IRQN (-13) ExcInfo g_excInfo = {0}; @@ -510,8 +511,13 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit() /* Enable USGFAULT, BUSFAULT, MEMFAULT */ *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT); + /* Enable DIV 0 and unaligned exception */ - *(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT; +#ifdef LOSCFG_ARCH_UNALIGNED_EXC + *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT); +#else + *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT); +#endif return; } diff --git a/kernel/arch/arm/cortex-m7/iar/los_interrupt.c b/kernel/arch/arm/cortex-m7/iar/los_interrupt.c index 6c5adc22..cfbde251 100644 --- a/kernel/arch/arm/cortex-m7/iar/los_interrupt.c +++ b/kernel/arch/arm/cortex-m7/iar/los_interrupt.c @@ -272,6 +272,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum) #define BUSFAULT (1 << 17) #define MEMFAULT (1 << 16) #define DIV0FAULT (1 << 4) +#define UNALIGNFAULT (1 << 3) #define HARDFAULT_IRQN (-13) ExcInfo g_excInfo = {0}; @@ -519,8 +520,13 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit() /* Enable USGFAULT, BUSFAULT, MEMFAULT */ *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT); + /* Enable DIV 0 and unaligned exception */ - *(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT; +#ifdef LOSCFG_ARCH_UNALIGNED_EXC + *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT); +#else + *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT); +#endif return; }