diff --git a/kernel/arch/arm/arm9/gcc/los_dispatch.S b/kernel/arch/arm/arm9/gcc/los_dispatch.S
index 01c9afb8..3d9c17b0 100644
--- a/kernel/arch/arm/arm9/gcc/los_dispatch.S
+++ b/kernel/arch/arm/arm9/gcc/los_dispatch.S
@@ -29,18 +29,18 @@
  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-    .equ    OS_PSR_THUMB,       0x20U
-    .equ    OS_PSR_INT_DIS,     0xC0U
-    .equ    OS_PSR_FIQ_DIS,     0x40U
-    .equ    OS_PSR_IRQ_DIS,     0x80U
-    .equ    OS_PSR_MODE_MASK,   0x1FU
-    .equ    OS_PSR_MODE_USR,    0x10U
-    .equ    OS_PSR_MODE_FIQ,    0x11U
-    .equ    OS_PSR_MODE_IRQ,    0x12U
-    .equ    OS_PSR_MODE_SVC,    0x13U
-    .equ    OS_PSR_MODE_ABT,    0x17U
-    .equ    OS_PSR_MODE_UND,    0x1BU
-    .equ    OS_PSR_MODE_SYS,    0x1FU
+    .equ    OS_PSR_THUMB,       0x20
+    .equ    OS_PSR_INT_DIS,     0xC0
+    .equ    OS_PSR_FIQ_DIS,     0x40
+    .equ    OS_PSR_IRQ_DIS,     0x80
+    .equ    OS_PSR_MODE_MASK,   0x1F
+    .equ    OS_PSR_MODE_USR,    0x10
+    .equ    OS_PSR_MODE_FIQ,    0x11
+    .equ    OS_PSR_MODE_IRQ,    0x12
+    .equ    OS_PSR_MODE_SVC,    0x13
+    .equ    OS_PSR_MODE_ABT,    0x17
+    .equ    OS_PSR_MODE_UND,    0x1B
+    .equ    OS_PSR_MODE_SYS,    0x1F
 
     .global HalStartToRun
     .global OsTaskEntryArm
diff --git a/kernel/arch/arm/arm9/gcc/los_exc.S b/kernel/arch/arm/arm9/gcc/los_exc.S
index 9c082e52..d74d8b86 100644
--- a/kernel/arch/arm/arm9/gcc/los_exc.S
+++ b/kernel/arch/arm/arm9/gcc/los_exc.S
@@ -29,17 +29,17 @@
  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-    .equ OS_PSR_INT_DIS,    0xC0U
-    .equ OS_PSR_FIQ_DIS,    0x40U
-    .equ OS_PSR_IRQ_DIS,    0x80U
-    .equ OS_PSR_MODE_MASK,  0x1FU
-    .equ OS_PSR_MODE_USR,   0x10U
-    .equ OS_PSR_MODE_FIQ,   0x11U
-    .equ OS_PSR_MODE_IRQ,   0x12U
-    .equ OS_PSR_MODE_SVC,   0x13U
-    .equ OS_PSR_MODE_ABT,   0x17U
-    .equ OS_PSR_MODE_UND,   0x1BU
-    .equ OS_PSR_MODE_SYS,   0x1FU
+    .equ OS_PSR_INT_DIS,    0xC0
+    .equ OS_PSR_FIQ_DIS,    0x40
+    .equ OS_PSR_IRQ_DIS,    0x80
+    .equ OS_PSR_MODE_MASK,  0x1F
+    .equ OS_PSR_MODE_USR,   0x10
+    .equ OS_PSR_MODE_FIQ,   0x11
+    .equ OS_PSR_MODE_IRQ,   0x12
+    .equ OS_PSR_MODE_SVC,   0x13
+    .equ OS_PSR_MODE_ABT,   0x17
+    .equ OS_PSR_MODE_UND,   0x1B
+    .equ OS_PSR_MODE_SYS,   0x1F
 
     .equ OS_EXCEPT_RESET,           0x00
     .equ OS_EXCEPT_UNDEF_INSTR,     0x01
diff --git a/kernel/arch/arm/arm9/gcc/los_timer.c b/kernel/arch/arm/arm9/gcc/los_timer.c
index 972dfe6b..590f736b 100644
--- a/kernel/arch/arm/arm9/gcc/los_timer.c
+++ b/kernel/arch/arm/arm9/gcc/los_timer.c
@@ -140,15 +140,11 @@ WEAK VOID HalTickUnlock(VOID)
     WRITE_UINT32(value, OS_TIMER_CTL_REG_ADDR);
 }
 
-VOID HalEnterSleep(LOS_SysSleepEnum sleep)
+UINT32 HalEnterSleep(VOID)
 {
-#if (LOSCFG_BASE_CORE_SCHED_SLEEP == 1)
-    if (sleep == OS_SYS_DEEP_SLEEP) {
-        OsSchedToSleep();
-    }
-#endif
-
     dsb();
     wfi();
     isb();
+
+    return LOS_OK;
 }
diff --git a/kernel/arch/arm/arm9/gcc/reset_vector.S b/kernel/arch/arm/arm9/gcc/reset_vector.S
index ca015a17..b106ea17 100644
--- a/kernel/arch/arm/arm9/gcc/reset_vector.S
+++ b/kernel/arch/arm/arm9/gcc/reset_vector.S
@@ -29,15 +29,15 @@
  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-    .equ CPSR_IRQ_DISABLE,  0x80U
-    .equ CPSR_FIQ_DISABLE,  0x40U
-    .equ CPSR_THUMB_ENABLE, 0x20U
-    .equ CPSR_USER_MODE,    0x10U
-    .equ CPSR_FIQ_MODE,     0x11U
-    .equ CPSR_IRQ_MODE,     0x12U
-    .equ CPSR_SVC_MODE,     0x13U
-    .equ CPSR_ABT_MODE,     0x17U
-    .equ CPSR_UNDEF_MODE,   0x1BU
+    .equ CPSR_IRQ_DISABLE,  0x80
+    .equ CPSR_FIQ_DISABLE,  0x40
+    .equ CPSR_THUMB_ENABLE, 0x20
+    .equ CPSR_USER_MODE,    0x10
+    .equ CPSR_FIQ_MODE,     0x11
+    .equ CPSR_IRQ_MODE,     0x12
+    .equ CPSR_SVC_MODE,     0x13
+    .equ CPSR_ABT_MODE,     0x17
+    .equ CPSR_UNDEF_MODE,   0x1B
 
     .global __exc_stack_top
     .global __irq_stack_top