From bc31d46e423b7f9b262f39416b20a60d46347137 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E9=87=91=E6=B0=B8=E7=94=9F?= Date: Wed, 24 Mar 2021 15:47:54 +0800 Subject: [PATCH] fix:pendsv trigger for cortex-m SOC:some cpu will not enter pendsv when set the flag,and we need dsb and isb to fix this --- kernel/arch/arm/cortex-m3/keil/los_dispatch.S | 2 ++ kernel/arch/arm/cortex-m33/gcc/los_dispatch.S | 2 ++ kernel/arch/arm/cortex-m4/gcc/los_dispatch.S | 2 ++ kernel/arch/arm/cortex-m4/iar/los_dispatch.S | 2 ++ kernel/arch/arm/cortex-m7/gcc/los_dispatch.S | 2 ++ kernel/arch/arm/cortex-m7/iar/los_dispatch.S | 2 ++ 6 files changed, 12 insertions(+) diff --git a/kernel/arch/arm/cortex-m3/keil/los_dispatch.S b/kernel/arch/arm/cortex-m3/keil/los_dispatch.S index ba53feb6..f6bb1088 100644 --- a/kernel/arch/arm/cortex-m3/keil/los_dispatch.S +++ b/kernel/arch/arm/cortex-m3/keil/los_dispatch.S @@ -111,6 +111,8 @@ HalTaskSchedule LDR R0, =OS_NVIC_INT_CTRL LDR R1, =OS_NVIC_PENDSVSET STR R1, [R0] + DSB + ISB BX LR HalPendSV diff --git a/kernel/arch/arm/cortex-m33/gcc/los_dispatch.S b/kernel/arch/arm/cortex-m33/gcc/los_dispatch.S index 298e7409..309fdde4 100644 --- a/kernel/arch/arm/cortex-m33/gcc/los_dispatch.S +++ b/kernel/arch/arm/cortex-m33/gcc/los_dispatch.S @@ -142,6 +142,8 @@ HalTaskSchedule: ldr r0, =OS_NVIC_INT_CTRL ldr r1, =OS_NVIC_PENDSVSET str r1, [r0] + dsb + isb bx lr .fnend diff --git a/kernel/arch/arm/cortex-m4/gcc/los_dispatch.S b/kernel/arch/arm/cortex-m4/gcc/los_dispatch.S index 648cb7c9..5116cd9c 100644 --- a/kernel/arch/arm/cortex-m4/gcc/los_dispatch.S +++ b/kernel/arch/arm/cortex-m4/gcc/los_dispatch.S @@ -145,6 +145,8 @@ HalTaskSchedule: ldr r1, =OS_NVIC_PENDSVSET str r1, [r0] bx lr + dsb + isb .fnend diff --git a/kernel/arch/arm/cortex-m4/iar/los_dispatch.S b/kernel/arch/arm/cortex-m4/iar/los_dispatch.S index e4c88527..dac97f6e 100755 --- a/kernel/arch/arm/cortex-m4/iar/los_dispatch.S +++ b/kernel/arch/arm/cortex-m4/iar/los_dispatch.S @@ -124,6 +124,8 @@ HalTaskSchedule LDR R0, =OS_NVIC_INT_CTRL LDR R1, =OS_NVIC_PENDSVSET STR R1, [R0] + DSB + ISB BX LR HalPendSV diff --git a/kernel/arch/arm/cortex-m7/gcc/los_dispatch.S b/kernel/arch/arm/cortex-m7/gcc/los_dispatch.S index 298e7409..309fdde4 100644 --- a/kernel/arch/arm/cortex-m7/gcc/los_dispatch.S +++ b/kernel/arch/arm/cortex-m7/gcc/los_dispatch.S @@ -142,6 +142,8 @@ HalTaskSchedule: ldr r0, =OS_NVIC_INT_CTRL ldr r1, =OS_NVIC_PENDSVSET str r1, [r0] + dsb + isb bx lr .fnend diff --git a/kernel/arch/arm/cortex-m7/iar/los_dispatch.S b/kernel/arch/arm/cortex-m7/iar/los_dispatch.S index e4c88527..dac97f6e 100755 --- a/kernel/arch/arm/cortex-m7/iar/los_dispatch.S +++ b/kernel/arch/arm/cortex-m7/iar/los_dispatch.S @@ -124,6 +124,8 @@ HalTaskSchedule LDR R0, =OS_NVIC_INT_CTRL LDR R1, =OS_NVIC_PENDSVSET STR R1, [R0] + DSB + ISB BX LR HalPendSV