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Update nuclei demo soc to latest version 

Based on Nuclei SDK v0.3.1

Signed-off-by: linzewen <linzewen@nucleisys.com>
This commit is contained in:
linzewen 2021-04-18 18:26:31 -07:00
parent 4170e57f18
commit b4f5bc433c
48 changed files with 231 additions and 245 deletions
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18
targets/riscv_nuclei_demo_soc_gcc/GCC/Makefile
View File

@ -37,13 +37,13 @@ LITEOSTOPDIR := ../../../
# C sources
C_SOURCES = \
$(wildcard ../Src/*.c) \
$(wildcard ../SoC/hbird/Common/Source/*.c) \
$(wildcard ../SoC/hbird/Common/Source/Drivers/*.c) \
$(wildcard ../SoC/hbird/Common/Source/Stubs/*.c)
$(wildcard ../SoC/demosoc/Common/Source/*.c) \
$(wildcard ../SoC/demosoc/Common/Source/Drivers/*.c) \
$(wildcard ../SoC/demosoc/Common/Source/Stubs/*.c)
# ASM sources
ASMS_SOURCES = \
$(wildcard ../SoC/hbird/Common/Source/GCC/*.S)
$(wildcard ../SoC/demosoc/Common/Source/GCC/*.S)
#######################################
@ -84,7 +84,7 @@ BIN = $(CP) -O binary -S
ECHO := echo
OPENOCD_CFG := openocd_hbird.cfg
OPENOCD_CFG := openocd_demosoc.cfg
#######################################
# CFLAGS
@ -110,9 +110,9 @@ AS_INCLUDES =
C_INCLUDES = \
-I../OS_CONFIG \
-I../Src \
-I../SoC/hbird/Board/hbird_eval/Include \
-I../SoC/hbird/Common/Include \
-I../SoC/hbird/Common/Source/Stubs
-I../SoC/demosoc/Board/nuclei_fpga_eval/Include \
-I../SoC/demosoc/Common/Include \
-I../SoC/demosoc/Common/Source/Stubs
# compile gcc flags
ASFLAGS = $(AS_DEFS) $(OPT) $(CORE_ARCH_ABI) $(OTHER_FLAGS) $(AS_INCLUDES) -Wall -fdata-sections -ffunction-sections
@ -150,7 +150,7 @@ GDB_CMDS += -ex "target extended-remote localhost:$(GDB_PORT)"
# LDFLAGS
#######################################
# link script
LDSCRIPT = gcc_hbird_ilm.ld
LDSCRIPT = gcc_demosoc_ilm.ld
# libraries
LIBS = -lm

2
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Board/hbird_eval/Source/GCC/gcc_hbird_ilm.ld → targets/riscv_nuclei_demo_soc_gcc/GCC/gcc_demosoc_ilm.ld
View File

@ -16,7 +16,7 @@
* limitations under the License.
*/
/******************************************************************************
* @file gcc_hbird_ilm.ld
* @file gcc_demosoc_ilm.ld
* @brief GNU Linker Script for Nuclei N/NX based device in ilm Download Mode
* @version V1.0.0
* @date 17. Dec 2019

6
targets/riscv_nuclei_demo_soc_gcc/GCC/openocd_hbird.cfg → targets/riscv_nuclei_demo_soc_gcc/GCC/openocd_demosoc.cfg
View File

@ -2,7 +2,7 @@ adapter_khz 1000
interface ftdi
ftdi_vid_pid 0x0403 0x6010
ftdi_oscan1_mode on
ftdi_oscan1_mode off
## bindto 0.0.0.0 can be used to cover all available interfaces.
## Uncomment bindto line to enable remote machine debug
@ -10,8 +10,8 @@ ftdi_oscan1_mode on
## If ftdi_device_desc not specified, the device description is ignored during device selection.
## So if you want to specify a dedicated FTDI device, you can select following device description:
## "Dual RS232-HS" is for HummingBird Debugger V1
## "USB <-> JTAG-DEBUGGER" is for HummingBird Debugger V2
## "Dual RS232-HS" is for Nuclei HummingBird Debugger V1
## "USB <-> JTAG-DEBUGGER" is for Nuclei HummingBird Debugger V2
## Uncomment one which match your device description
# ftdi_device_desc "Dual RS232-HS"
# ftdi_device_desc "USB <-> JTAG-DEBUGGER"

6
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Board/hbird_eval/Include/board_hbird_eval.h → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Board/nuclei_fpga_eval/Include/board_nuclei_fpga_eval.h
View File

@ -1,9 +1,9 @@
// See LICENSE for license details.
#ifndef _BOARD_HBIRD_EVAL_H_
#define _BOARD_HBIRD_EVAL_H_
#ifndef _BOARD_NUCLEI_FPGA_EVAL_H_
#define _BOARD_NUCLEI_FPGA_EVAL_H_
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "nuclei_sdk_soc.h"

4
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Board/hbird_eval/Include/nuclei_sdk_hal.h → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Board/nuclei_fpga_eval/Include/nuclei_sdk_hal.h
View File

@ -3,10 +3,10 @@
#define _NUCLEI_SDK_HAL_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "board_hbird_eval.h"
#include "board_nuclei_fpga_eval.h"
#define SOC_DEBUG_UART UART0

2
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Board/hbird_eval/Source/GCC/gcc_hbird_ddr.ld → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Board/nuclei_fpga_eval/Source/GCC/gcc_demosoc_ddr.ld
View File

@ -16,7 +16,7 @@
* limitations under the License.
*/
/******************************************************************************
* @file gcc_hbird_ddr.ld
* @file gcc_demosoc_ddr.ld
* @brief GNU Linker Script for Nuclei N/NX based device in ddr Download Mode
* @version V1.0.0
* @date 20. Jul 2020

4
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Board/hbird_eval/Source/GCC/gcc_hbird_flash.ld → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Board/nuclei_fpga_eval/Source/GCC/gcc_demosoc_flash.ld
View File

@ -16,8 +16,8 @@
* limitations under the License.
*/
/******************************************************************************
* @file gcc_hbird_flash.ld
* @brief GNU Linker Script for Nuclei N/NX based device in Flash Download Mode
* @file gcc_demosoc_flash.ld
* @brief GNU Linker Script for Nuclei N/NX based device in flash Download Mode
* @version V1.0.0
* @date 17. Dec 2019
******************************************************************************/

4
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Board/hbird_eval/Source/GCC/gcc_hbird_flashxip.ld → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Board/nuclei_fpga_eval/Source/GCC/gcc_demosoc_flashxip.ld
View File

@ -16,8 +16,8 @@
* limitations under the License.
*/
/******************************************************************************
* @file gcc_hbird_flashxip.ld
* @brief GNU Linker Script for Nuclei N/NX based device in FlashXIP Download Mode
* @file gcc_demosoc_flashxip.ld
* @brief GNU Linker Script for Nuclei N/NX based device in flashxip Download Mode
* @version V1.0.0
* @date 17. Dec 2019
******************************************************************************/

22
targets/riscv_nuclei_demo_soc_gcc/GCC/gcc_hbird_ilm.ld → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Board/nuclei_fpga_eval/Source/GCC/gcc_demosoc_ilm.ld
View File

@ -16,7 +16,7 @@
* limitations under the License.
*/
/******************************************************************************
* @file gcc_hbird_ilm.ld
* @file gcc_demosoc_ilm.ld
* @brief GNU Linker Script for Nuclei N/NX based device in ilm Download Mode
* @version V1.0.0
* @date 17. Dec 2019
@ -35,8 +35,7 @@ MEMORY
SECTIONS
{
__stack_size = DEFINED(__stack_size) ? __stack_size : 10K;
__heap_size = DEFINED(__heap_size) ? __heap_size : 10K;
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
.init :
{
@ -180,10 +179,6 @@ SECTIONS
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
. = ALIGN(4);
__osdriv_start = .;
KEEP (*(osdriv))
__osdriv_end = .;
} >ram AT>ilm
. = ALIGN(4);
@ -203,20 +198,13 @@ SECTIONS
} >ram AT>ram
. = ALIGN(8);
PROVIDE( _end = . );
PROVIDE( end = . );
.stack : ALIGN(0x10)
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
{
PROVIDE( _heap_end = . );
. = __stack_size;
PROVIDE( _sp = . );
} >ram AT>ram
PROVIDE( _end = . );
.heap : ALIGN(0x10)
{
. = __heap_size;
PROVIDE( _heap_end = . );
PROVIDE( __los_heap_addr_start__ = . );
. = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram);
PROVIDE( __los_heap_addr_end__ = . );
} >ram AT>ram
}

19
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Board/hbird_eval/openocd_hbird.cfg → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Board/nuclei_fpga_eval/openocd_demosoc.cfg
View File

@ -1,15 +1,20 @@
adapter_khz 1000
interface ftdi
ftdi_vid_pid 0x0403 0x6010
ftdi_oscan1_mode off
## bindto 0.0.0.0 can be used to cover all available interfaces.
## Uncomment bindto line to enable remote machine debug
# bindto 0.0.0.0
## If ftdi_device_desc not specified, the device description is ignored during device selection.
## So if you want to specify a dedicated FTDI device, you can select following device description:
## "Dual RS232-HS" is for HummingBird Debugger V1
## "USB <-> JTAG-DEBUGGER" is for HummingBird Debugger V2
## "Dual RS232-HS" is for Nuclei HummingBird Debugger V1
## "USB <-> JTAG-DEBUGGER" is for Nuclei HummingBird Debugger V2
## Uncomment one which match your device description
# ftdi_device_desc "Dual RS232-HS"
# ftdi_device_desc "USB <-> JTAG-DEBUGGER"
ftdi_vid_pid 0x0403 0x6010
ftdi_oscan1_mode off
transport select jtag
@ -33,13 +38,13 @@ flash bank $_FLASHNAME fespi 0x20000000 0 0 0 $_TARGETNAME
# Set the ILM space also as flash, to make sure it can be add breakpoint with hardware trigger
#flash bank onboard_ilm fespi 0x80000000 0 0 0 $_TARGETNAME
# Expose Nuclei self-defined CSRS range 770-800,835-850,1984-2032,2064-2070
# Expose Nuclei self-defined CSRS
# See https://github.com/riscv/riscv-gnu-toolchain/issues/319#issuecomment-358397306
# Then user can view the csr register value in gdb using: info reg csr775 for CSR MTVT(0x307)
riscv expose_csrs 770-800,835-850,1984-2032,2064-2070
riscv expose_csrs 416-496,770-800,835-850,1227-1231,1483-1486,1984-2032,2064-2070,2370-2380,2490-2500,4032-4040
init
#reset
if {[ info exists pulse_srst]} {
ftdi_set_signal nSRST 0
ftdi_set_signal nSRST z

73
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Include/hbird.h → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Include/demosoc.h
View File

@ -1,7 +1,7 @@
/******************************************************************************
* @file hbird.h
* @file demosoc.h
* @brief NMSIS Core Peripheral Access Layer Header File for
* Nuclei HummingBird evaluation SoC which support Nuclei N/NX class cores
* Nuclei Demo SoC which support Nuclei N/NX class cores
* @version V1.00
* @date 22. Nov 2019
******************************************************************************/
@ -23,8 +23,8 @@
* limitations under the License.
*/
#ifndef __HBIRD_H__
#define __HBIRD_H__
#ifndef __DEMOSOC_H__
#define __DEMOSOC_H__
#include <stddef.h>
@ -37,7 +37,7 @@ extern "C" {
*/
/** @addtogroup hbird
/** @addtogroup demosoc
* @{
*/
@ -52,9 +52,8 @@ extern "C" {
/* ================ Interrupt Number Definition ================ */
/* =========================================================================================================================== */
typedef enum IRQn
{
/* ======================================= Nuclei Core Specific Interrupt Numbers ======================================== */
typedef enum IRQn {
/* ======================================= Nuclei Core Specific Interrupt Numbers ======================================== */
Reserved0_IRQn = 0, /*!< Internal reserved */
Reserved1_IRQn = 1, /*!< Internal reserved */
@ -76,10 +75,10 @@ typedef enum IRQn
Reserved15_IRQn = 17, /*!< Internal reserved */
Reserved16_IRQn = 18, /*!< Internal reserved */
/* =========================================== hbird Specific Interrupt Numbers ========================================= */
/* ToDo: add here your device specific external interrupt numbers. 19~1023 is reserved number for user. Maxmum interrupt supported
could get from clicinfo.NUM_INTERRUPT. According the interrupt handlers defined in startup_Device.s
eg.: Interrupt for Timer#1 eclic_tim1_handler -> TIM1_IRQn */
/* =========================================== demosoc Specific Interrupt Numbers ========================================= */
/* ToDo: add here your device specific external interrupt numbers. 19~1023 is reserved number for user. Maxmum interrupt supported
could get from clicinfo.NUM_INTERRUPT. According the interrupt handlers defined in startup_Device.s
eg.: Interrupt for Timer#1 eclic_tim1_handler -> TIM1_IRQn */
SOC_INT19_IRQn = 19, /*!< Device Interrupt */
SOC_INT20_IRQn = 20, /*!< Device Interrupt */
SOC_INT21_IRQn = 21, /*!< Device Interrupt */
@ -120,7 +119,7 @@ typedef enum IRQn
/* =========================================================================================================================== */
typedef enum EXCn {
/* ======================================= Nuclei N/NX Specific Exception Code ======================================== */
/* ======================================= Nuclei N/NX Specific Exception Code ======================================== */
InsUnalign_EXCn = 0, /*!< Instruction address misaligned */
InsAccFault_EXCn = 1, /*!< Instruction access fault */
IlleIns_EXCn = 2, /*!< Illegal instruction */
@ -158,7 +157,7 @@ typedef enum EXCn {
#endif /* __riscv_xlen == 64 */
/* ToDo: define the correct core features for the hbird */
/* ToDo: define the correct core features for the demosoc */
#define __ECLIC_PRESENT 1 /*!< Set to 1 if ECLIC is present */
#define __ECLIC_BASEADDR 0x0C000000UL /*!< Set to ECLIC baseaddr of your device */
@ -188,16 +187,16 @@ typedef enum EXCn {
#include <nmsis_core.h> /*!< Nuclei N/NX class processor and core peripherals */
/* ToDo: include your system_hbird.h file
/* ToDo: include your system_demosoc.h file
replace 'Device' with your device name */
#include "system_hbird.h" /*!< hbird System */
#include "system_demosoc.h" /*!< demosoc System */
/* ======================================== Start of section using anonymous unions ======================================== */
#if defined (__GNUC__)
/* anonymous unions are enabled by default */
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#warning Not supported compiler type
#endif
#define RTC_FREQ 32768
@ -309,11 +308,11 @@ typedef struct {
*/
typedef struct {
__IOM uint32_t CFG;
uint32_t RESERVED0;
uint32_t RESERVED0;
__IOM uint32_t COUNT;
uint32_t RESERVED1;
uint32_t RESERVED1;
__IOM uint32_t S;
uint32_t RESERVED2[3];
uint32_t RESERVED2[3];
__IOM uint32_t CMP0;
__IOM uint32_t CMP1;
__IOM uint32_t CMP2;
@ -359,14 +358,14 @@ typedef struct {
__IOM uint8_t CSR; /* CR and SR in same address */
} I2C_TypeDef;
/*@}*/ /* end of group hbird_Peripherals */
/*@}*/ /* end of group demosoc_Peripherals */
/* ========================================= End of section using anonymous unions ========================================= */
#if defined (__GNUC__)
/* anonymous unions are enabled by default */
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#warning Not supported compiler type
#endif
@ -385,21 +384,21 @@ typedef struct {
#define ONCHIP_ROM_BASE (0x00001000UL) /*!< (ROM ) Base Address */
#define ONCHIP_ILM_BASE (0x80000000UL) /*!< (ILM ) Base Address */
#define ONCHIP_DLM_BASE (0x90000000UL) /*!< (DLM ) Base Address */
#define HBIRD_PERIPH_BASE (0x10000000UL) /*!< (Peripheral) Base Address */
#define DEMOSOC_PERIPH_BASE (0x10000000UL) /*!< (Peripheral) Base Address */
/* Peripheral memory map */
/* Fast-IO Interfaced IP */
#define GPIO_BASE (HBIRD_PERIPH_BASE + 0x12000) /*!< (GPIO) Base Address */
#define GPIO_BASE (DEMOSOC_PERIPH_BASE + 0x12000) /*!< (GPIO) Base Address */
/* PPI Interfaced IP */
#define UART0_BASE (HBIRD_PERIPH_BASE + 0x13000) /*!< (UART0) Base Address */
#define QSPI0_BASE (HBIRD_PERIPH_BASE + 0x14000) /*!< (QSPI0) Base Address */
#define PWM0_BASE (HBIRD_PERIPH_BASE + 0x15000) /*!< (PWM0) Base Address */
#define UART1_BASE (HBIRD_PERIPH_BASE + 0x23000) /*!< (UART1) Base Address */
#define QSPI1_BASE (HBIRD_PERIPH_BASE + 0x24000) /*!< (QSPI1) Base Address */
#define PWM1_BASE (HBIRD_PERIPH_BASE + 0x25000) /*!< (PWM1) Base Address */
#define QSPI2_BASE (HBIRD_PERIPH_BASE + 0x34000) /*!< (QSPI2) Base Address */
#define PWM2_BASE (HBIRD_PERIPH_BASE + 0x35000) /*!< (PWM2) Base Address */
#define I2C_BASE (HBIRD_PERIPH_BASE + 0x42000) /*!< (I2C Master) Base Address */
#define UART0_BASE (DEMOSOC_PERIPH_BASE + 0x13000) /*!< (UART0) Base Address */
#define QSPI0_BASE (DEMOSOC_PERIPH_BASE + 0x14000) /*!< (QSPI0) Base Address */
#define PWM0_BASE (DEMOSOC_PERIPH_BASE + 0x15000) /*!< (PWM0) Base Address */
#define UART1_BASE (DEMOSOC_PERIPH_BASE + 0x23000) /*!< (UART1) Base Address */
#define QSPI1_BASE (DEMOSOC_PERIPH_BASE + 0x24000) /*!< (QSPI1) Base Address */
#define PWM1_BASE (DEMOSOC_PERIPH_BASE + 0x25000) /*!< (PWM1) Base Address */
#define QSPI2_BASE (DEMOSOC_PERIPH_BASE + 0x34000) /*!< (QSPI2) Base Address */
#define PWM2_BASE (DEMOSOC_PERIPH_BASE + 0x35000) /*!< (PWM2) Base Address */
#define I2C_BASE (DEMOSOC_PERIPH_BASE + 0x42000) /*!< (I2C Master) Base Address */
/** @} */ /* End of group Device_Peripheral_peripheralAddr */
@ -448,7 +447,7 @@ typedef struct {
uint32_t get_cpu_freq();
void delay_1ms(uint32_t count);
/** @} */ /* End of group hbird */
/** @} */ /* End of group demosoc */
/** @} */ /* End of group Nuclei */
@ -456,4 +455,4 @@ void delay_1ms(uint32_t count);
}
#endif
#endif /* __HBIRD_H__ */
#endif /* __DEMOSOC_H__ */

32
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Include/hbird_gpio.h → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Include/demosoc_gpio.h
View File

@ -1,9 +1,9 @@
// See LICENSE for license details.
#ifndef _HBIRD_GPIO_H
#define _HBIRD_GPIO_H
#ifndef _DEMOSOC_GPIO_H
#define _DEMOSOC_GPIO_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#define GPIO_INPUT_VAL (0x00)
@ -37,20 +37,20 @@ typedef enum gpio_int_type {
GPIO_INT_LOW = 3
} GPIO_INT_TYPE;
int32_t gpio_iof_config(GPIO_TypeDef *gpio, uint32_t mask, IOF_FUNC func);
int32_t gpio_enable_output(GPIO_TypeDef *gpio, uint32_t mask);
int32_t gpio_enable_input(GPIO_TypeDef *gpio, uint32_t mask);
int32_t gpio_write(GPIO_TypeDef *gpio, uint32_t mask, uint32_t value);
int32_t gpio_toggle(GPIO_TypeDef *gpio, uint32_t mask);
int32_t gpio_read(GPIO_TypeDef *gpio, uint32_t mask);
int32_t gpio_set_pue(GPIO_TypeDef *gpio, uint32_t mask, uint32_t value);
int32_t gpio_set_ds(GPIO_TypeDef *gpio, uint32_t mask, uint32_t value);
int32_t gpio_set_outxor(GPIO_TypeDef *gpio, uint32_t mask, uint32_t value);
int32_t gpio_enable_interrupt(GPIO_TypeDef *gpio, uint32_t mask, GPIO_INT_TYPE type);
int32_t gpio_disable_interrupt(GPIO_TypeDef *gpio, uint32_t mask, GPIO_INT_TYPE type);
int32_t gpio_clear_interrupt(GPIO_TypeDef *gpio, uint32_t mask, GPIO_INT_TYPE type);
int32_t gpio_iof_config(GPIO_TypeDef* gpio, uint32_t mask, IOF_FUNC func);
int32_t gpio_enable_output(GPIO_TypeDef* gpio, uint32_t mask);
int32_t gpio_enable_input(GPIO_TypeDef* gpio, uint32_t mask);
int32_t gpio_write(GPIO_TypeDef* gpio, uint32_t mask, uint32_t value);
int32_t gpio_toggle(GPIO_TypeDef* gpio, uint32_t mask);
int32_t gpio_read(GPIO_TypeDef* gpio, uint32_t mask);
int32_t gpio_set_pue(GPIO_TypeDef* gpio, uint32_t mask, uint32_t value);
int32_t gpio_set_ds(GPIO_TypeDef* gpio, uint32_t mask, uint32_t value);
int32_t gpio_set_outxor(GPIO_TypeDef* gpio, uint32_t mask, uint32_t value);
int32_t gpio_enable_interrupt(GPIO_TypeDef* gpio, uint32_t mask, GPIO_INT_TYPE type);
int32_t gpio_disable_interrupt(GPIO_TypeDef* gpio, uint32_t mask, GPIO_INT_TYPE type);
int32_t gpio_clear_interrupt(GPIO_TypeDef* gpio, uint32_t mask, GPIO_INT_TYPE type);
#ifdef __cplusplus
}
#endif
#endif /* _HBIRD_GPIO_H */
#endif /* _DEMOSOC_GPIO_H */

8
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Include/hbird_i2c.h → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Include/demosoc_i2c.h
View File

@ -1,10 +1,10 @@
//See LICENSE for license details
#ifndef _HBIRD_I2C_H
#define _HBIRD_I2C_H
#ifndef _DEMOSOC_I2C_H
#define _DEMOSOC_I2C_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* register offsets */
@ -53,4 +53,4 @@
#ifdef __cplusplus
}
#endif
#endif /* _HBIRD_I2C_H */
#endif /* _DEMOSOC_I2C_H */

8
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Include/hbird_pwm.h → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Include/demosoc_pwm.h
View File

@ -1,10 +1,10 @@
// See LICENSE for license details.
#ifndef _HBIRD_PWM_H
#define _HBIRD_PWM_H
#ifndef _DEMOSOC_PWM_H
#define _DEMOSOC_PWM_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Register offsets */
@ -41,4 +41,4 @@
#ifdef __cplusplus
}
#endif
#endif /* _HBIRD_PWM_H */
#endif /* _DEMOSOC_PWM_H */

8
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Include/hbird_spi.h → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Include/demosoc_spi.h
View File

@ -1,10 +1,10 @@
// See LICENSE for license details.
#ifndef _HBIRD_SPI_H
#define _HBIRD_SPI_H
#ifndef _DEMOSOC_SPI_H
#define _DEMOSOC_SPI_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Register offsets */
@ -83,4 +83,4 @@
#ifdef __cplusplus
}
#endif
#endif /* _HBIRD_SPI_H */
#endif /* _DEMOSOC_SPI_H */

28
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Include/hbird_uart.h → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Include/demosoc_uart.h
View File

@ -1,10 +1,10 @@
// See LICENSE for license details.
#ifndef _HBIRD_UART_H
#define _HBIRD_UART_H
#ifndef _DEMOSOC_UART_H
#define _DEMOSOC_UART_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Register offsets */
@ -58,18 +58,18 @@ typedef enum uart_stop_bit {
UART_STOP_BIT_2 = 1
} UART_STOP_BIT;
int32_t uart_init(UART_TypeDef *uart, uint32_t baudrate);
int32_t uart_config_stopbit(UART_TypeDef *uart, UART_STOP_BIT stopbit);
int32_t uart_write(UART_TypeDef *uart, uint8_t val);
uint8_t uart_read(UART_TypeDef *uart);
int32_t uart_set_tx_watermark(UART_TypeDef *uart, uint32_t watermark);
int32_t uart_enable_txint(UART_TypeDef *uart);
int32_t uart_disable_txint(UART_TypeDef *uart);
int32_t uart_set_rx_watermark(UART_TypeDef *uart, uint32_t watermark);
int32_t uart_enable_rxint(UART_TypeDef *uart);
int32_t uart_disable_rxint(UART_TypeDef *uart);
int32_t uart_init(UART_TypeDef* uart, uint32_t baudrate);
int32_t uart_config_stopbit(UART_TypeDef* uart, UART_STOP_BIT stopbit);
int32_t uart_write(UART_TypeDef* uart, uint8_t val);
uint8_t uart_read(UART_TypeDef* uart);
int32_t uart_set_tx_watermark(UART_TypeDef* uart, uint32_t watermark);
int32_t uart_enable_txint(UART_TypeDef* uart);
int32_t uart_disable_txint(UART_TypeDef* uart);
int32_t uart_set_rx_watermark(UART_TypeDef* uart, uint32_t watermark);
int32_t uart_enable_rxint(UART_TypeDef* uart);
int32_t uart_disable_rxint(UART_TypeDef* uart);
#ifdef __cplusplus
}
#endif
#endif /* _HBIRD_UART_H */
#endif /* _DEMOSOC_UART_H */

19
targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Include/nuclei_sdk_soc.h Normal file
View File

@ -0,0 +1,19 @@
// See LICENSE for license details.
#ifndef _NUCLEI_SDK_SOC_H
#define _NUCLEI_SDK_SOC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "demosoc.h"
#include "demosoc_uart.h"
#include "demosoc_gpio.h"
#include "demosoc_i2c.h"
#include "demosoc_spi.h"
#include "demosoc_pwm.h"
#ifdef __cplusplus
}
#endif
#endif

14
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Include/system_hbird.h → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Include/system_demosoc.h
View File

@ -17,15 +17,15 @@
* limitations under the License.
*/
/*******************************************************************************
* @file system_hbird.h
* @file system_demosoc.h
* @brief NMSIS Nuclei N/NX Device Peripheral Access Layer Header File for
* Device <Device>
* @version V1.00
* @date 17. Dec 2019
******************************************************************************/
#ifndef __SYSTEM_HBIRD_H__ /* ToDo: replace '<Device>' with your device name */
#define __SYSTEM_HBIRD_H__
#ifndef __SYSTEM_DEMOSOC_H__ /* ToDo: replace '<Device>' with your device name */
#define __SYSTEM_DEMOSOC_H__
#ifdef __cplusplus
extern "C" {
@ -40,14 +40,14 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) *
* \details
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
extern void SystemInit(void);
/**
* \brief Update SystemCoreClock variable.
* \details
* Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
extern void SystemCoreClockUpdate(void);
/**
* \brief Register an exception handler for exception code EXCn
@ -70,10 +70,10 @@ extern void ECLIC_Init(void);
* This function set vector mode, trigger mode and polarity, interrupt level and priority,
* assign handler for specific IRQn.
*/
extern int32_t ECLIC_Register_IRQ(IRQn_Type IRQn, uint8_t shv, ECLIC_TRIGGER_Type trig_mode, uint8_t lvl, uint8_t priority, void *handler);
extern int32_t ECLIC_Register_IRQ(IRQn_Type IRQn, uint8_t shv, ECLIC_TRIGGER_Type trig_mode, uint8_t lvl, uint8_t priority, void* handler);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_HBIRD_H__ */
#endif /* __SYSTEM_DEMOSOC_H__ */

37
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/Drivers/hbird_gpio.c → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/Drivers/demosoc_gpio.c
View File

@ -1,7 +1,7 @@
#include "hbird.h"
#include "hbird_gpio.h"
#include "demosoc.h"
#include "demosoc_gpio.h"
int32_t gpio_iof_config(GPIO_TypeDef *gpio, uint32_t mask, IOF_FUNC func)
int32_t gpio_iof_config(GPIO_TypeDef* gpio, uint32_t mask, IOF_FUNC func)
{
if (__RARELY(gpio == NULL)) {
return -1;
@ -24,7 +24,7 @@ int32_t gpio_iof_config(GPIO_TypeDef *gpio, uint32_t mask, IOF_FUNC func)
return 0;
}
int32_t gpio_enable_output(GPIO_TypeDef *gpio, uint32_t mask)
int32_t gpio_enable_output(GPIO_TypeDef* gpio, uint32_t mask)
{
if (__RARELY(gpio == NULL)) {
return -1;
@ -34,7 +34,7 @@ int32_t gpio_enable_output(GPIO_TypeDef *gpio, uint32_t mask)
return 0;
}
int32_t gpio_enable_input(GPIO_TypeDef *gpio, uint32_t mask)
int32_t gpio_enable_input(GPIO_TypeDef* gpio, uint32_t mask)
{
if (__RARELY(gpio == NULL)) {
return -1;
@ -44,7 +44,7 @@ int32_t gpio_enable_input(GPIO_TypeDef *gpio, uint32_t mask)
return 0;
}
int32_t gpio_write(GPIO_TypeDef *gpio, uint32_t mask, uint32_t value)
int32_t gpio_write(GPIO_TypeDef* gpio, uint32_t mask, uint32_t value)
{
if (__RARELY(gpio == NULL)) {
return -1;
@ -58,7 +58,7 @@ int32_t gpio_write(GPIO_TypeDef *gpio, uint32_t mask, uint32_t value)
return 0;
}
int32_t gpio_toggle(GPIO_TypeDef *gpio, uint32_t mask)
int32_t gpio_toggle(GPIO_TypeDef* gpio, uint32_t mask)
{
if (__RARELY(gpio == NULL)) {
return -1;
@ -68,7 +68,7 @@ int32_t gpio_toggle(GPIO_TypeDef *gpio, uint32_t mask)
}
int32_t gpio_read(GPIO_TypeDef *gpio, uint32_t mask)
int32_t gpio_read(GPIO_TypeDef* gpio, uint32_t mask)
{
if (__RARELY(gpio == NULL)) {
return -1;
@ -76,34 +76,37 @@ int32_t gpio_read(GPIO_TypeDef *gpio, uint32_t mask)
return gpio->INPUT_VAL & mask;
}
int32_t gpio_set_pue(GPIO_TypeDef *gpio, uint32_t mask, uint32_t value)
int32_t gpio_set_pue(GPIO_TypeDef* gpio, uint32_t mask, uint32_t value)
{
if (__RARELY(gpio == NULL)) {
return -1;
}
gpio->PULLUP_EN |= (mask & value);
mask = gpio->PULLUP_EN & (~mask);
gpio->PULLUP_EN = (mask | value);
return 0;
}
int32_t gpio_set_ds(GPIO_TypeDef *gpio, uint32_t mask, uint32_t value)
int32_t gpio_set_ds(GPIO_TypeDef* gpio, uint32_t mask, uint32_t value)
{
if (__RARELY(gpio == NULL)) {
return -1;
}
gpio->DRIVE |= (mask & value);
mask = gpio->DRIVE & (~mask);
gpio->DRIVE = (mask | value);
return 0;
}
int32_t gpio_set_outxor(GPIO_TypeDef *gpio, uint32_t mask, uint32_t value)
int32_t gpio_set_outxor(GPIO_TypeDef* gpio, uint32_t mask, uint32_t value)
{
if (__RARELY(gpio == NULL)) {
return -1;
}
gpio->OUTPUT_XOR |= (mask & value);
mask = gpio->OUTPUT_XOR & (~mask);
gpio->OUTPUT_XOR = (mask | value);
return 0;
}
int32_t gpio_enable_interrupt(GPIO_TypeDef *gpio, uint32_t mask, GPIO_INT_TYPE type)
int32_t gpio_enable_interrupt(GPIO_TypeDef* gpio, uint32_t mask, GPIO_INT_TYPE type)
{
if (__RARELY(gpio == NULL)) {
return -1;
@ -127,7 +130,7 @@ int32_t gpio_enable_interrupt(GPIO_TypeDef *gpio, uint32_t mask, GPIO_INT_TYPE t
return 0;
}
int32_t gpio_disable_interrupt(GPIO_TypeDef *gpio, uint32_t mask, GPIO_INT_TYPE type)
int32_t gpio_disable_interrupt(GPIO_TypeDef* gpio, uint32_t mask, GPIO_INT_TYPE type)
{
if (__RARELY(gpio == NULL)) {
return -1;
@ -151,7 +154,7 @@ int32_t gpio_disable_interrupt(GPIO_TypeDef *gpio, uint32_t mask, GPIO_INT_TYPE
return 0;
}
int32_t gpio_clear_interrupt(GPIO_TypeDef *gpio, uint32_t mask, GPIO_INT_TYPE type)
int32_t gpio_clear_interrupt(GPIO_TypeDef* gpio, uint32_t mask, GPIO_INT_TYPE type)
{
if (__RARELY(gpio == NULL)) {
return -1;

27
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/Drivers/hbird_uart.c → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/Drivers/demosoc_uart.c
View File

@ -1,7 +1,7 @@
#include "hbird.h"
#include "hbird_uart.h"
#include "demosoc.h"
#include "demosoc_uart.h"
int32_t uart_init(UART_TypeDef *uart, uint32_t baudrate)
int32_t uart_init(UART_TypeDef* uart, uint32_t baudrate)
{
if (__RARELY(uart == NULL)) {
return -1;
@ -12,7 +12,7 @@ int32_t uart_init(UART_TypeDef *uart, uint32_t baudrate)
return 0;
}
int32_t uart_config_stopbit(UART_TypeDef *uart, UART_STOP_BIT stopbit)
int32_t uart_config_stopbit(UART_TypeDef* uart, UART_STOP_BIT stopbit)
{
if (__RARELY(uart == NULL)) {
return -1;
@ -23,7 +23,7 @@ int32_t uart_config_stopbit(UART_TypeDef *uart, UART_STOP_BIT stopbit)
return 0;
}
int32_t uart_write(UART_TypeDef *uart, uint8_t val)
int32_t uart_write(UART_TypeDef* uart, uint8_t val)
{
if (__RARELY(uart == NULL)) {
return -1;
@ -35,7 +35,7 @@ int32_t uart_write(UART_TypeDef *uart, uint8_t val)
return 0;
}
uint8_t uart_read(UART_TypeDef *uart)
uint8_t uart_read(UART_TypeDef* uart)
{
uint32_t reg;
if (__RARELY(uart == NULL)) {
@ -43,12 +43,11 @@ uint8_t uart_read(UART_TypeDef *uart)
}
do {
reg = uart->RXFIFO;
}
while (reg & UART_RXFIFO_EMPTY);
} while (reg & UART_RXFIFO_EMPTY);
return (uint8_t)(reg & 0xFF);
}
int32_t uart_set_tx_watermark(UART_TypeDef *uart, uint32_t watermark)
int32_t uart_set_tx_watermark(UART_TypeDef* uart, uint32_t watermark)
{
if (__RARELY(uart == NULL)) {
return -1;
@ -58,7 +57,7 @@ int32_t uart_set_tx_watermark(UART_TypeDef *uart, uint32_t watermark)
return 0;
}
int32_t uart_enable_txint(UART_TypeDef *uart)
int32_t uart_enable_txint(UART_TypeDef* uart)
{
if (__RARELY(uart == NULL)) {
return -1;
@ -67,7 +66,7 @@ int32_t uart_enable_txint(UART_TypeDef *uart)
return 0;
}
int32_t uart_disable_txint(UART_TypeDef *uart)
int32_t uart_disable_txint(UART_TypeDef* uart)
{
if (__RARELY(uart == NULL)) {
return -1;
@ -76,7 +75,7 @@ int32_t uart_disable_txint(UART_TypeDef *uart)
return 0;
}
int32_t uart_set_rx_watermark(UART_TypeDef *uart, uint32_t watermark)
int32_t uart_set_rx_watermark(UART_TypeDef* uart, uint32_t watermark)
{
if (__RARELY(uart == NULL)) {
return -1;
@ -86,7 +85,7 @@ int32_t uart_set_rx_watermark(UART_TypeDef *uart, uint32_t watermark)
return 0;
}
int32_t uart_enable_rxint(UART_TypeDef *uart)
int32_t uart_enable_rxint(UART_TypeDef* uart)
{
if (__RARELY(uart == NULL)) {
return -1;
@ -95,7 +94,7 @@ int32_t uart_enable_rxint(UART_TypeDef *uart)
return 0;
}
int32_t uart_disable_rxint(UART_TypeDef *uart)
int32_t uart_disable_rxint(UART_TypeDef* uart)
{
if (__RARELY(uart == NULL)) {
return -1;

5
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/GCC/intexc_hbird.S → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/GCC/intexc_demosoc.S
View File

@ -16,9 +16,9 @@
* limitations under the License.
*/
/******************************************************************************
* \file intexc_hbird.S
* \file intexc_demosoc.S
* \brief NMSIS Interrupt and Exception Handling Template File
* for Nuclei HummingBird evaluation SoC which support Nuclei N/NX class cores
* for Nuclei Demo SoC which support Nuclei N/NX class cores
* \version V1.00
* \date 17 Dec 2019
*
@ -174,6 +174,7 @@ exc_entry:
* system_Device.c, you can adjust it as you want
*/
call core_exception_handler
/* Restore the necessary CSR registers */
RESTORE_CSR_CONTEXT
/* Restore the caller saving registers (context) */

8
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/GCC/startup_hbird.S → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/GCC/startup_demosoc.S
View File

@ -16,9 +16,9 @@
* limitations under the License.
*/
/******************************************************************************
* \file startup_hbird.S
* \file startup_demosoc.S
* \brief NMSIS Nuclei N/NX Class Core based Core Device Startup File for
* Nuclei HummingBird evaluation SoC which support Nuclei N/NX class cores
* Nuclei Demo SoC which support Nuclei N/NX class cores
* \version V1.00
* \date 17. Dec 2019
*
@ -90,6 +90,7 @@
.weak eclic_irq50_handler
.globl vector_base
.type vector_base, @object
vector_base:
#if defined(DOWNLOAD_MODE) && (DOWNLOAD_MODE != DOWNLOAD_MODE_FLASH)
j _start /* 0: Reserved, Jump to _start when reset for ILM/FlashXIP mode.*/
@ -164,7 +165,7 @@ vector_base:
.section .init
.globl _start
.type _start,@function
.type _start, @function
/**
* Reset Handler called on controller reset
@ -212,7 +213,6 @@ _start:
* will share common entry.
*/
la t0, exc_entry
// la t0, HalTrapEntry
csrw CSR_MTVEC, t0
/* Set the interrupt processing mode to ECLIC mode */

2
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/Stubs/clock_getres.c → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/Stubs/clock_getres.c
View File

@ -5,7 +5,7 @@
#include <stdint.h>
/* Get resolution of clock. */
__WEAK int clock_getres(clockid_t clock_id, struct timespec *res)
__WEAK int clock_getres(clockid_t clock_id, struct timespec* res)
{
res->tv_sec = 0;
res->tv_nsec = 1000000000 / SystemCoreClock;

4
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/Stubs/clock_gettime.c → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/Stubs/clock_gettime.c
View File

@ -4,10 +4,10 @@
#include <time.h>
#include <sys/time.h>
extern int _gettimeofday(struct timeval *tp, void *tzp);
extern int _gettimeofday(struct timeval* tp, void* tzp);
/* Get current value of CLOCK and store it in tp. */
__WEAK int clock_gettime(clockid_t clock_id, struct timespec *tp)
__WEAK int clock_gettime(clockid_t clock_id, struct timespec* tp)
{
struct timeval tv;
int retval = -1;

2
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/Stubs/clock_settime.c → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/Stubs/clock_settime.c
View File

@ -4,7 +4,7 @@
#include <time.h>
/* Set CLOCK to value TP. */
__WEAK int clock_settime(clockid_t clock_id, const struct timespec *tp)
__WEAK int clock_settime(clockid_t clock_id, const struct timespec* tp)
{
return -1;
}

0
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/Stubs/close.c → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/Stubs/close.c
View File

2
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/Stubs/execve.c → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/Stubs/execve.c
View File

@ -5,7 +5,7 @@
#undef errno
extern int errno;
__WEAK int _execve(char *name, char **argv, char **env)
__WEAK int _execve(char* name, char** argv, char** env)
{
errno = ENOMEM;
return -1;

2
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/Stubs/exit.c → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/Stubs/exit.c
View File

@ -3,7 +3,7 @@
__WEAK void _exit(int fd)
{
while(1) {
while (1) {
__WFI();
}
}

0
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/Stubs/fork.c → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/Stubs/fork.c
View File

2
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/Stubs/fstat.c → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/Stubs/fstat.c
View File

@ -7,7 +7,7 @@
#undef errno
extern int errno;
__WEAK int _fstat(int file, struct stat *st)
__WEAK int _fstat(int file, struct stat* st)
{
if ((STDOUT_FILENO == file) || (STDERR_FILENO == file)) {
st->st_mode = S_IFCHR;

0
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/Stubs/getpid.c → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/Stubs/getpid.c
View File

2
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/Stubs/gettimeofday.c → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/Stubs/gettimeofday.c
View File

@ -3,7 +3,7 @@
#include <sys/time.h>
#include "nuclei_sdk_soc.h"
__WEAK int _gettimeofday(struct timeval *tp, void *tzp)
__WEAK int _gettimeofday(struct timeval* tp, void* tzp)
{
uint64_t cycles;

0
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/Stubs/isatty.c → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/Stubs/isatty.c
View File

0
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/Stubs/kill.c → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/Stubs/kill.c
View File

2
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/Stubs/link.c → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/Stubs/link.c
View File

@ -5,7 +5,7 @@
#undef errno
extern int errno;
int _link(char *old, char *new)
int _link(char* old, char* new)
{
errno = EMLINK;
return -1;

0
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/Stubs/lseek.c → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/Stubs/lseek.c
View File

2
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/Stubs/open.c → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/Stubs/open.c
View File

@ -5,7 +5,7 @@
#undef errno
extern int errno;
__WEAK int _open(const char *name, int flags, int mode)
__WEAK int _open(const char* name, int flags, int mode)
{
errno = ENOSYS;
return -1;

2
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/Stubs/read.c → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/Stubs/read.c
View File

@ -13,7 +13,7 @@ __WEAK ssize_t _read(int fd, void* ptr, size_t len)
return -1;
}
uint8_t *readbuf = (uint8_t *)ptr;
uint8_t* readbuf = (uint8_t*)ptr;
readbuf[0] = uart_read(SOC_DEBUG_UART);
#ifdef UART_AUTO_ECHO
uart_write(SOC_DEBUG_UART, readbuf[0]);

8
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/Stubs/sbrk.c → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/Stubs/sbrk.c
View File

@ -4,16 +4,16 @@
#include <stddef.h>
#include <unistd.h>
__WEAK void *_sbrk(ptrdiff_t incr)
__WEAK void* _sbrk(ptrdiff_t incr)
{
extern char _end[];
extern char _heap_end[];
static char *curbrk = _end;
static char* curbrk = _end;
if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) {
return (void *)(-1);
return (void*)(-1);
}
curbrk += incr;
return (void *)(curbrk - incr);
return (void*)(curbrk - incr);
}

2
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/Stubs/stat.c → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/Stubs/stat.c
View File

@ -2,7 +2,7 @@
#include "nuclei_sdk_soc.h"
#include <sys/stat.h>
__WEAK int _stat(char *file, struct stat *st)
__WEAK int _stat(char* file, struct stat* st)
{
st->st_mode = S_IFCHR;
return 0;

4
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/Stubs/times.c → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/Stubs/times.c
View File

@ -4,9 +4,9 @@
#include <time.h>
#include "nuclei_sdk_soc.h"
extern int _gettimeofday(struct timeval *, void *);
extern int _gettimeofday(struct timeval*, void*);
__WEAK clock_t _times(struct tms *buf)
__WEAK clock_t _times(struct tms* buf)
{
static struct timeval t0;
struct timeval t;

4
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/Stubs/unlink.c → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/Stubs/unlink.c
View File

@ -1,12 +1,12 @@
/* See LICENSE of license details. */
#include <errno.h>
#include "nuclei_sdk_hal.h"
#include <nuclei_sdk_hal.h>
#undef errno
extern int errno;
__WEAK int _unlink(const char *name)
__WEAK int _unlink(const char* name)
{
return -1;
}

2
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/Stubs/wait.c → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/Stubs/wait.c
View File

@ -6,7 +6,7 @@
#undef errno
extern int errno;
__WEAK int _wait(int *status)
__WEAK int _wait(int* status)
{
errno = ECHILD;
return -1;

4
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/Stubs/write.c → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/Stubs/write.c
View File

@ -3,7 +3,7 @@
#include <errno.h>
#include <unistd.h>
#include <sys/types.h>
#include "nuclei_sdk_hal.h"
#include <nuclei_sdk_hal.h>
__WEAK ssize_t _write(int fd, const void* ptr, size_t len)
{
@ -11,7 +11,7 @@ __WEAK ssize_t _write(int fd, const void* ptr, size_t len)
return -1;
}
const uint8_t *writebuf = (const uint8_t *)ptr;
const uint8_t* writebuf = (const uint8_t*)ptr;
for (size_t i = 0; i < len; i++) {
if (writebuf[i] == '\n') {
uart_write(SOC_DEBUG_UART, '\r');

0
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/hbird_common.c → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/demosoc_common.c
View File

42
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/system_hbird.c → targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/system_demosoc.c
View File

@ -17,17 +17,16 @@
* limitations under the License.
*/
/******************************************************************************
* @file system_hbird.c
* @file system_demosoc.c
* @brief NMSIS Nuclei Core Device Peripheral Access Layer Source File for
* Nuclei HummingBird evaluation SoC which support Nuclei N/NX class cores
* Nuclei Demo SoC which support Nuclei N/NX class cores
* @version V1.00
* @date 22. Nov 2019
******************************************************************************/
#include <stdint.h>
#include <stdio.h>
#include "nuclei_sdk_hal.h"
#include "los_arch_interrupt.h"
#include "los_debug.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
@ -62,7 +61,7 @@
* Thus one must assure that the variable always reflects the actual system clock speed.
*
* \attention
* Be aware that a value stored to \c SystemCoreClock during low level initializaton (i.e. \c SystemInit()) might get
* Be aware that a value stored to \c SystemCoreClock during low level initialization (i.e. \c SystemInit()) might get
* overwritten by C libray startup code and/or .bss section initialization.
* Thus its highly recommended to call \ref SystemCoreClockUpdate at the beginning of the user \c main() routine.
*
@ -100,7 +99,7 @@ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Clock Frequency (Core Clock)
* during program execution. The function evaluates the clock register settings and calculates
* the current core clock.
*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */
{
/* ToDo: add code to calculate the system frequency based upon the current
* register settings.
@ -118,7 +117,7 @@ void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
* with a variable clock speed, it updates the variable \ref SystemCoreClock.
* SystemInit is called from the file <b>startup<i>_device</i></b>.
*/
void SystemInit (void)
void SystemInit(void)
{
/* ToDo: add code to initialize the system
* Warn: do not use global variables because this function is called before
@ -147,7 +146,7 @@ void SystemInit (void)
* - Exception code 0 - 11, totally 12 exceptions are mapped to SystemExceptionHandlers[0:11]
* - Exception for NMI is also re-routed to exception handling(exception code 0xFFF) in startup code configuration, the handler itself is mapped to SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM]
*/
static unsigned long SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM+1];
static unsigned long SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM + 1];
/**
* \brief Exception Handler Function Typedef
@ -155,7 +154,7 @@ static unsigned long SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM+1];
* This typedef is only used internal in this system_<Device>.c file.
* It is used to do type conversion for registered exception handler before calling it.
*/
typedef void (*EXC_HANDLER) (unsigned long mcause, unsigned long sp);
typedef void (*EXC_HANDLER)(unsigned long mcause, unsigned long sp);
/**
* \brief System Default Exception Handler
@ -166,10 +165,11 @@ typedef void (*EXC_HANDLER) (unsigned long mcause, unsigned long sp);
static void system_default_exception_handler(unsigned long mcause, unsigned long sp)
{
/* TODO: Uncomment this if you have implement printf function */
printf("MCAUSE: 0x%lx\r\n", mcause);
printf("MEPC : 0x%lx\r\n", __RV_CSR_READ(CSR_MEPC));
printf("MTVAL : 0x%lx\r\n", __RV_CSR_READ(CSR_MBADADDR));
while(1);
printf("MCAUSE : 0x%lx\r\n", mcause);
printf("MDCAUSE: 0x%lx\r\n", __RV_CSR_READ(CSR_MDCAUSE));
printf("MEPC : 0x%lx\r\n", __RV_CSR_READ(CSR_MEPC));
printf("MTVAL : 0x%lx\r\n", __RV_CSR_READ(CSR_MTVAL));
while (1);
}
/**
@ -181,7 +181,7 @@ static void system_default_exception_handler(unsigned long mcause, unsigned long
*/
static void Exception_Init(void)
{
for (int i = 0; i < MAX_SYSTEM_EXCEPTION_NUM+1; i++) {
for (int i = 0; i < MAX_SYSTEM_EXCEPTION_NUM + 1; i++) {
SystemExceptionHandlers[i] = (unsigned long)system_default_exception_handler;
}
}
@ -238,10 +238,6 @@ uint32_t core_exception_handler(unsigned long mcause, unsigned long sp)
uint32_t EXCn = (uint32_t)(mcause & 0X00000fff);
EXC_HANDLER exc_handler;
PRINTK("----------------All Task infomation ------------\r\n");
HalDisplayTaskInfo();
PRINTK("---------------exc handler infomation -----------\r\n");
if ((EXCn < MAX_SYSTEM_EXCEPTION_NUM) && (EXCn >= 0)) {
exc_handler = (EXC_HANDLER)SystemExceptionHandlers[EXCn];
} else if (EXCn == NMI_EXCn) {
@ -302,10 +298,10 @@ void ECLIC_Init(void)
* - This function use to configure specific eclic interrupt and register its interrupt handler and enable its interrupt.
* - If the vector table is placed in read-only section(FLASHXIP mode), handler could not be installed
*/
int32_t ECLIC_Register_IRQ(IRQn_Type IRQn, uint8_t shv, ECLIC_TRIGGER_Type trig_mode, uint8_t lvl, uint8_t priority, void *handler)
int32_t ECLIC_Register_IRQ(IRQn_Type IRQn, uint8_t shv, ECLIC_TRIGGER_Type trig_mode, uint8_t lvl, uint8_t priority, void* handler)
{
if ((IRQn > SOC_INT_MAX) || (shv > ECLIC_VECTOR_INTERRUPT) \
|| (trig_mode > ECLIC_NEGTIVE_EDGE_TRIGGER )) {
|| (trig_mode > ECLIC_NEGTIVE_EDGE_TRIGGER)) {
return -1;
}
@ -338,7 +334,7 @@ int32_t ECLIC_Register_IRQ(IRQn_Type IRQn, uint8_t shv, ECLIC_TRIGGER_Type trig_
void _premain_init(void)
{
/* TODO: Add your own initialization code here, called before main */
/* __ICACHE_PRESENT and __DCACHE_PRESENT are defined in hbird.h */
/* __ICACHE_PRESENT and __DCACHE_PRESENT are defined in demosoc.h */
#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT == 1
EnableICache();
#endif
@ -352,7 +348,7 @@ void _premain_init(void)
SystemBannerPrint();
/* Initialize exception default handlers */
Exception_Init();
/* ECLIC initilization, mainly MTH and NLBIT */
/* ECLIC initialization, mainly MTH and NLBIT */
ECLIC_Init();
}
@ -369,7 +365,7 @@ void _postmain_fini(int status)
{
/* TODO: Add your own finishing code here, called after main */
#ifdef SIMULATION_XLSPIKE
extern void xlspike_exit(int status);
extern void xlspike_exit(int status);
xlspike_exit(status);
#endif
}

19
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Include/nuclei_sdk_soc.h
View File

@ -1,19 +0,0 @@
// See LICENSE for license details.
#ifndef _NUCLEI_SDK_SOC_H
#define _NUCLEI_SDK_SOC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "hbird.h"
#include "hbird_uart.h"
#include "hbird_gpio.h"
#include "hbird_i2c.h"
#include "hbird_spi.h"
#include "hbird_pwm.h"
#ifdef __cplusplus
}
#endif
#endif

5
targets/riscv_nuclei_demo_soc_gcc/SoC/hbird/Common/Source/Stubs/stub.h
View File

@ -1,5 +0,0 @@
static inline int _stub(int err)
{
return -1;
}