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!245 解决arm9编译冲突的问题 

Merge pull request !245 from JerryH/arm9
This commit is contained in:
openharmony_ci 2021-08-03 11:57:47 +00:00 committed by Gitee
parent 1a56599021 c1a6245368
commit b195b40bf2
4 changed files with 35 additions and 39 deletions
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24
kernel/arch/arm/arm9/gcc/los_dispatch.S
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@ -29,18 +29,18 @@
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */
.equ OS_PSR_THUMB, 0x20U .equ OS_PSR_THUMB, 0x20
.equ OS_PSR_INT_DIS, 0xC0U .equ OS_PSR_INT_DIS, 0xC0
.equ OS_PSR_FIQ_DIS, 0x40U .equ OS_PSR_FIQ_DIS, 0x40
.equ OS_PSR_IRQ_DIS, 0x80U .equ OS_PSR_IRQ_DIS, 0x80
.equ OS_PSR_MODE_MASK, 0x1FU .equ OS_PSR_MODE_MASK, 0x1F
.equ OS_PSR_MODE_USR, 0x10U .equ OS_PSR_MODE_USR, 0x10
.equ OS_PSR_MODE_FIQ, 0x11U .equ OS_PSR_MODE_FIQ, 0x11
.equ OS_PSR_MODE_IRQ, 0x12U .equ OS_PSR_MODE_IRQ, 0x12
.equ OS_PSR_MODE_SVC, 0x13U .equ OS_PSR_MODE_SVC, 0x13
.equ OS_PSR_MODE_ABT, 0x17U .equ OS_PSR_MODE_ABT, 0x17
.equ OS_PSR_MODE_UND, 0x1BU .equ OS_PSR_MODE_UND, 0x1B
.equ OS_PSR_MODE_SYS, 0x1FU .equ OS_PSR_MODE_SYS, 0x1F
.global HalStartToRun .global HalStartToRun
.global OsTaskEntryArm .global OsTaskEntryArm

22
kernel/arch/arm/arm9/gcc/los_exc.S
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@ -29,17 +29,17 @@
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */
.equ OS_PSR_INT_DIS, 0xC0U .equ OS_PSR_INT_DIS, 0xC0
.equ OS_PSR_FIQ_DIS, 0x40U .equ OS_PSR_FIQ_DIS, 0x40
.equ OS_PSR_IRQ_DIS, 0x80U .equ OS_PSR_IRQ_DIS, 0x80
.equ OS_PSR_MODE_MASK, 0x1FU .equ OS_PSR_MODE_MASK, 0x1F
.equ OS_PSR_MODE_USR, 0x10U .equ OS_PSR_MODE_USR, 0x10
.equ OS_PSR_MODE_FIQ, 0x11U .equ OS_PSR_MODE_FIQ, 0x11
.equ OS_PSR_MODE_IRQ, 0x12U .equ OS_PSR_MODE_IRQ, 0x12
.equ OS_PSR_MODE_SVC, 0x13U .equ OS_PSR_MODE_SVC, 0x13
.equ OS_PSR_MODE_ABT, 0x17U .equ OS_PSR_MODE_ABT, 0x17
.equ OS_PSR_MODE_UND, 0x1BU .equ OS_PSR_MODE_UND, 0x1B
.equ OS_PSR_MODE_SYS, 0x1FU .equ OS_PSR_MODE_SYS, 0x1F
.equ OS_EXCEPT_RESET, 0x00 .equ OS_EXCEPT_RESET, 0x00
.equ OS_EXCEPT_UNDEF_INSTR, 0x01 .equ OS_EXCEPT_UNDEF_INSTR, 0x01

10
kernel/arch/arm/arm9/gcc/los_timer.c
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@ -140,15 +140,11 @@ WEAK VOID HalTickUnlock(VOID)
WRITE_UINT32(value, OS_TIMER_CTL_REG_ADDR); WRITE_UINT32(value, OS_TIMER_CTL_REG_ADDR);
} }
VOID HalEnterSleep(LOS_SysSleepEnum sleep) UINT32 HalEnterSleep(VOID)
{ {
#if (LOSCFG_BASE_CORE_SCHED_SLEEP == 1)
if (sleep == OS_SYS_DEEP_SLEEP) {
OsSchedToSleep();
}
#endif
dsb(); dsb();
wfi(); wfi();
isb(); isb();
return LOS_OK;
} }

18
kernel/arch/arm/arm9/gcc/reset_vector.S
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@ -29,15 +29,15 @@
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */
.equ CPSR_IRQ_DISABLE, 0x80U .equ CPSR_IRQ_DISABLE, 0x80
.equ CPSR_FIQ_DISABLE, 0x40U .equ CPSR_FIQ_DISABLE, 0x40
.equ CPSR_THUMB_ENABLE, 0x20U .equ CPSR_THUMB_ENABLE, 0x20
.equ CPSR_USER_MODE, 0x10U .equ CPSR_USER_MODE, 0x10
.equ CPSR_FIQ_MODE, 0x11U .equ CPSR_FIQ_MODE, 0x11
.equ CPSR_IRQ_MODE, 0x12U .equ CPSR_IRQ_MODE, 0x12
.equ CPSR_SVC_MODE, 0x13U .equ CPSR_SVC_MODE, 0x13
.equ CPSR_ABT_MODE, 0x17U .equ CPSR_ABT_MODE, 0x17
.equ CPSR_UNDEF_MODE, 0x1BU .equ CPSR_UNDEF_MODE, 0x1B
.global __exc_stack_top .global __exc_stack_top
.global __irq_stack_top .global __irq_stack_top