From bff65877a281ac1cdcbefd325dcd3ad4933edac9 Mon Sep 17 00:00:00 2001
From: kenneth <459864689@qq.com>
Date: Thu, 3 Jun 2021 20:45:12 +0800
Subject: [PATCH] fix: correct the counter of exception type

correct the counter of exception type from 19 to 21

close https://gitee.com/openharmony/kernel_liteos_m/issues/I3SR54

Signed-off-by: kenneth <459864689@qq.com>
---
 kernel/arch/arm/cortex-m3/keil/los_arch_interrupt.h             | 2 +-
 kernel/arch/arm/cortex-m33/gcc/los_arch_interrupt.h             | 2 +-
 kernel/arch/arm/cortex-m33/iar/NTZ/los_arch_interrupt.h         | 2 +-
 .../arch/arm/cortex-m33/iar/TZ/non_secure/los_arch_interrupt.h  | 2 +-
 kernel/arch/arm/cortex-m4/gcc/los_arch_interrupt.h              | 2 +-
 kernel/arch/arm/cortex-m4/iar/los_arch_interrupt.h              | 2 +-
 kernel/arch/arm/cortex-m7/gcc/los_arch_interrupt.h              | 2 +-
 kernel/arch/arm/cortex-m7/iar/los_arch_interrupt.h              | 2 +-
 8 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/kernel/arch/arm/cortex-m3/keil/los_arch_interrupt.h b/kernel/arch/arm/cortex-m3/keil/los_arch_interrupt.h
index 008b97d3..3c98b745 100644
--- a/kernel/arch/arm/cortex-m3/keil/los_arch_interrupt.h
+++ b/kernel/arch/arm/cortex-m3/keil/los_arch_interrupt.h
@@ -687,7 +687,7 @@ VOID HalHwiInit();
 typedef struct TagExcInfo {
     /**< Exception occurrence phase: 0 means that an exception occurs in initialization, 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
     UINT16 phase;
-    /**< Exception type. When exceptions occur, check the numbers 1 - 19 listed above */
+    /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
     UINT16 type;
     /**< If the exact address access error indicates the wrong access address when the exception occurred */
     UINT32 faultAddr;
diff --git a/kernel/arch/arm/cortex-m33/gcc/los_arch_interrupt.h b/kernel/arch/arm/cortex-m33/gcc/los_arch_interrupt.h
index 008b97d3..3c98b745 100644
--- a/kernel/arch/arm/cortex-m33/gcc/los_arch_interrupt.h
+++ b/kernel/arch/arm/cortex-m33/gcc/los_arch_interrupt.h
@@ -687,7 +687,7 @@ VOID HalHwiInit();
 typedef struct TagExcInfo {
     /**< Exception occurrence phase: 0 means that an exception occurs in initialization, 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
     UINT16 phase;
-    /**< Exception type. When exceptions occur, check the numbers 1 - 19 listed above */
+    /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
     UINT16 type;
     /**< If the exact address access error indicates the wrong access address when the exception occurred */
     UINT32 faultAddr;
diff --git a/kernel/arch/arm/cortex-m33/iar/NTZ/los_arch_interrupt.h b/kernel/arch/arm/cortex-m33/iar/NTZ/los_arch_interrupt.h
index 6ff797f7..e02d529c 100644
--- a/kernel/arch/arm/cortex-m33/iar/NTZ/los_arch_interrupt.h
+++ b/kernel/arch/arm/cortex-m33/iar/NTZ/los_arch_interrupt.h
@@ -687,7 +687,7 @@ VOID HalHwiInit();
 typedef struct TagExcInfo {
     /**< Exception occurrence phase: 0 means that an exception occurs in initialization, 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
     UINT16 phase;
-    /**< Exception type. When exceptions occur, check the numbers 1 - 19 listed above */
+    /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
     UINT16 type;
     /**< If the exact address access error indicates the wrong access address when the exception occurred */
     UINT32 faultAddr;
diff --git a/kernel/arch/arm/cortex-m33/iar/TZ/non_secure/los_arch_interrupt.h b/kernel/arch/arm/cortex-m33/iar/TZ/non_secure/los_arch_interrupt.h
index 6ff797f7..e02d529c 100644
--- a/kernel/arch/arm/cortex-m33/iar/TZ/non_secure/los_arch_interrupt.h
+++ b/kernel/arch/arm/cortex-m33/iar/TZ/non_secure/los_arch_interrupt.h
@@ -687,7 +687,7 @@ VOID HalHwiInit();
 typedef struct TagExcInfo {
     /**< Exception occurrence phase: 0 means that an exception occurs in initialization, 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
     UINT16 phase;
-    /**< Exception type. When exceptions occur, check the numbers 1 - 19 listed above */
+    /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
     UINT16 type;
     /**< If the exact address access error indicates the wrong access address when the exception occurred */
     UINT32 faultAddr;
diff --git a/kernel/arch/arm/cortex-m4/gcc/los_arch_interrupt.h b/kernel/arch/arm/cortex-m4/gcc/los_arch_interrupt.h
index 008b97d3..3c98b745 100644
--- a/kernel/arch/arm/cortex-m4/gcc/los_arch_interrupt.h
+++ b/kernel/arch/arm/cortex-m4/gcc/los_arch_interrupt.h
@@ -687,7 +687,7 @@ VOID HalHwiInit();
 typedef struct TagExcInfo {
     /**< Exception occurrence phase: 0 means that an exception occurs in initialization, 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
     UINT16 phase;
-    /**< Exception type. When exceptions occur, check the numbers 1 - 19 listed above */
+    /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
     UINT16 type;
     /**< If the exact address access error indicates the wrong access address when the exception occurred */
     UINT32 faultAddr;
diff --git a/kernel/arch/arm/cortex-m4/iar/los_arch_interrupt.h b/kernel/arch/arm/cortex-m4/iar/los_arch_interrupt.h
index 008b97d3..3c98b745 100644
--- a/kernel/arch/arm/cortex-m4/iar/los_arch_interrupt.h
+++ b/kernel/arch/arm/cortex-m4/iar/los_arch_interrupt.h
@@ -687,7 +687,7 @@ VOID HalHwiInit();
 typedef struct TagExcInfo {
     /**< Exception occurrence phase: 0 means that an exception occurs in initialization, 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
     UINT16 phase;
-    /**< Exception type. When exceptions occur, check the numbers 1 - 19 listed above */
+    /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
     UINT16 type;
     /**< If the exact address access error indicates the wrong access address when the exception occurred */
     UINT32 faultAddr;
diff --git a/kernel/arch/arm/cortex-m7/gcc/los_arch_interrupt.h b/kernel/arch/arm/cortex-m7/gcc/los_arch_interrupt.h
index 008b97d3..3c98b745 100644
--- a/kernel/arch/arm/cortex-m7/gcc/los_arch_interrupt.h
+++ b/kernel/arch/arm/cortex-m7/gcc/los_arch_interrupt.h
@@ -687,7 +687,7 @@ VOID HalHwiInit();
 typedef struct TagExcInfo {
     /**< Exception occurrence phase: 0 means that an exception occurs in initialization, 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
     UINT16 phase;
-    /**< Exception type. When exceptions occur, check the numbers 1 - 19 listed above */
+    /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
     UINT16 type;
     /**< If the exact address access error indicates the wrong access address when the exception occurred */
     UINT32 faultAddr;
diff --git a/kernel/arch/arm/cortex-m7/iar/los_arch_interrupt.h b/kernel/arch/arm/cortex-m7/iar/los_arch_interrupt.h
index 008b97d3..3c98b745 100644
--- a/kernel/arch/arm/cortex-m7/iar/los_arch_interrupt.h
+++ b/kernel/arch/arm/cortex-m7/iar/los_arch_interrupt.h
@@ -687,7 +687,7 @@ VOID HalHwiInit();
 typedef struct TagExcInfo {
     /**< Exception occurrence phase: 0 means that an exception occurs in initialization, 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
     UINT16 phase;
-    /**< Exception type. When exceptions occur, check the numbers 1 - 19 listed above */
+    /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
     UINT16 type;
     /**< If the exact address access error indicates the wrong access address when the exception occurred */
     UINT32 faultAddr;