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task: risc-v系统异常时取消对medeleg寄存器的保存 

部分开源架构不支持该寄存器，且非常用寄存器

Close #I60IS5
Signed-off-by: zhushengle <zhushengle@huawei.com>
Change-Id: I8db31f84a24cc6143513c725691e4ba780ca99e9
This commit is contained in:
zhushengle 2022-11-10 16:07:37 +08:00
parent 2f08268983
commit 914913fab6
1 changed files with 1 additions and 2 deletions
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3
arch/risc-v/riscv32/gcc/los_exc.S
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@ -139,8 +139,7 @@ HalTrapEntry:
sw a0, 0 * REGBYTES(sp) sw a0, 0 * REGBYTES(sp)
csrr t0, mtval csrr t0, mtval
sw t0, 1 * REGBYTES(sp) sw t0, 1 * REGBYTES(sp)
csrr t0, medeleg sw zero, 2 * REGBYTES(sp)
sw t0, 2 * REGBYTES(sp)
sw gp, 3 * REGBYTES(sp) sw gp, 3 * REGBYTES(sp)
mv a0, sp mv a0, sp
csrw mscratch, sp csrw mscratch, sp