diff --git a/kernel/arch/arm/cortex-m3/keil/los_exc.S b/kernel/arch/arm/cortex-m3/keil/los_exc.S
index 96f338db..c37cc67b 100644
--- a/kernel/arch/arm/cortex-m3/keil/los_exc.S
+++ b/kernel/arch/arm/cortex-m3/keil/los_exc.S
@@ -195,7 +195,7 @@ _hwiActiveCheck
     RBIT  R2, R3
     CLZ   R2, R2
     AND   R12, R12, #1
-    ADD   R2, R2, R12, LSL #5               ; calculate R2 (hwi number) as uwPid
+    ADD   R2, R2, R12, LSL #5               ; calculate R2 (hwi number) as pid
 
 _ExcInMSP
     CMP   LR, #0XFFFFFFED
diff --git a/kernel/arch/arm/cortex-m33/gcc/NTZ/los_exc.S b/kernel/arch/arm/cortex-m33/gcc/NTZ/los_exc.S
index 5660c577..bfe407da 100755
--- a/kernel/arch/arm/cortex-m33/gcc/NTZ/los_exc.S
+++ b/kernel/arch/arm/cortex-m33/gcc/NTZ/los_exc.S
@@ -268,7 +268,7 @@ _hwiActiveCheck:
     RBIT  R2, R3
     CLZ   R2, R2
     AND   R12, R12, #1
-    ADD   R2, R2, R12, LSL #5               // calculate R2 (hwi number) as uwPid
+    ADD   R2, R2, R12, LSL #5               // calculate R2 (hwi number) as pid
     .fnend
 
     .type _ExcInMSP, %function
@@ -282,10 +282,7 @@ _ExcInMSP:
     PUSH  {R3}
     MRS   R12, PRIMASK                  // store message-->exc: disable int?
     PUSH {R4-R12}                       // store message-->exc: {R4-R12}
-#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined(__FPU_USED) && (__FPU_USED == 1U)))
     VPUSH {D8-D15}
-#endif
     B     _handleEntry
   .fnend
 
@@ -341,10 +338,7 @@ _hwiActiveCheckNext:
 
     MRS   R12, PRIMASK
     PUSH {R4-R12}
-#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined(__FPU_USED) && (__FPU_USED == 1U)))
     VPUSH {D8-D15}
-#endif
 
     // copy auto saved task register
 
diff --git a/kernel/arch/arm/cortex-m33/gcc/TZ/non_secure/los_exc.S b/kernel/arch/arm/cortex-m33/gcc/TZ/non_secure/los_exc.S
index e95b12c5..654a75c6 100755
--- a/kernel/arch/arm/cortex-m33/gcc/TZ/non_secure/los_exc.S
+++ b/kernel/arch/arm/cortex-m33/gcc/TZ/non_secure/los_exc.S
@@ -252,7 +252,7 @@ _hwiActiveCheck:
     RBIT  R2, R3
     CLZ   R2, R2
     AND   R12, R12, #1
-    ADD   R2, R2, R12, LSL #5               // calculate R2 (hwi number) as uwPid
+    ADD   R2, R2, R12, LSL #5               // calculate R2 (hwi number) as pid
     .fnend
 
     .type _ExcInMSP, %function
@@ -266,10 +266,7 @@ _ExcInMSP:
     PUSH  {R3}
     MRS   R12, PRIMASK                  // store message-->exc: disable int?
     PUSH {R4-R12}                       // store message-->exc: {R4-R12}
-#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined(__FPU_USED) && (__FPU_USED == 1U)))
     VPUSH {D8-D15}
-#endif
     B     _handleEntry
   .fnend
 
@@ -325,10 +322,7 @@ _hwiActiveCheckNext:
 
     MRS   R12, PRIMASK
     PUSH {R4-R12}
-#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined(__FPU_USED) && (__FPU_USED == 1U)))
     VPUSH {D8-D15}
-#endif
 
     // copy auto saved task register
 
diff --git a/kernel/arch/arm/cortex-m33/gcc/los_exc.S b/kernel/arch/arm/cortex-m33/gcc/los_exc.S
index af0753ab..ac963eec 100644
--- a/kernel/arch/arm/cortex-m33/gcc/los_exc.S
+++ b/kernel/arch/arm/cortex-m33/gcc/los_exc.S
@@ -268,7 +268,7 @@ _hwiActiveCheck:
     RBIT  R2, R3
     CLZ   R2, R2
     AND   R12, R12, #1
-    ADD   R2, R2, R12, LSL #5               // calculate R2 (hwi number) as uwPid
+    ADD   R2, R2, R12, LSL #5               // calculate R2 (hwi number) as pid
     .fnend
 
     .type _ExcInMSP, %function
@@ -282,10 +282,7 @@ _ExcInMSP:
     PUSH  {R3}
     MRS   R12, PRIMASK                  // store message-->exc: disable int?
     PUSH {R4-R12}                       // store message-->exc: {R4-R12}
-#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined(__FPU_USED) && (__FPU_USED == 1U)))
     VPUSH {D8-D15}
-#endif
     B     _handleEntry
   .fnend
 
@@ -341,10 +338,7 @@ _hwiActiveCheckNext:
 
     MRS   R12, PRIMASK
     PUSH {R4-R12}
-#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined(__FPU_USED) && (__FPU_USED == 1U)))
     VPUSH {D8-D15}
-#endif
 
     // copy auto saved task register
 
diff --git a/kernel/arch/arm/cortex-m33/iar/TZ/non_secure/los_exc.S b/kernel/arch/arm/cortex-m33/iar/TZ/non_secure/los_exc.S
index d954304d..c46912ca 100644
--- a/kernel/arch/arm/cortex-m33/iar/TZ/non_secure/los_exc.S
+++ b/kernel/arch/arm/cortex-m33/iar/TZ/non_secure/los_exc.S
@@ -184,7 +184,7 @@ _hwiActiveCheck
     RBIT  R2, R3
     CLZ   R2, R2
     AND   R12, R12, #1
-    ADD   R2, R2, R12, LSL #5               ; calculate R2 (hwi number) as uwPid
+    ADD   R2, R2, R12, LSL #5               ; calculate R2 (hwi number) as pid
 
 _ExcInMSP
     CMP   LR, #0XFFFFFFED
diff --git a/kernel/arch/arm/cortex-m4/gcc/los_exc.S b/kernel/arch/arm/cortex-m4/gcc/los_exc.S
index b2106500..d1aefe68 100644
--- a/kernel/arch/arm/cortex-m4/gcc/los_exc.S
+++ b/kernel/arch/arm/cortex-m4/gcc/los_exc.S
@@ -267,7 +267,7 @@ _hwiActiveCheck:
     RBIT  R2, R3
     CLZ   R2, R2
     AND   R12, R12, #1
-    ADD   R2, R2, R12, LSL #5               // calculate R2 (hwi number) as uwPid
+    ADD   R2, R2, R12, LSL #5               // calculate R2 (hwi number) as pid
     .fnend
 
     .type _ExcInMSP, %function
diff --git a/kernel/arch/arm/cortex-m4/iar/los_exc.S b/kernel/arch/arm/cortex-m4/iar/los_exc.S
index 7c26aba9..8d4d71f4 100644
--- a/kernel/arch/arm/cortex-m4/iar/los_exc.S
+++ b/kernel/arch/arm/cortex-m4/iar/los_exc.S
@@ -195,7 +195,7 @@ _hwiActiveCheck
     RBIT  R2, R3
     CLZ   R2, R2
     AND   R12, R12, #1
-    ADD   R2, R2, R12, LSL #5               ; calculate R2 (hwi number) as uwPid
+    ADD   R2, R2, R12, LSL #5               ; calculate R2 (hwi number) as pid
 
 _ExcInMSP
     CMP   LR, #0xFFFFFFED
diff --git a/kernel/arch/arm/cortex-m7/gcc/los_exc.S b/kernel/arch/arm/cortex-m7/gcc/los_exc.S
index bef3bc89..ac963eec 100644
--- a/kernel/arch/arm/cortex-m7/gcc/los_exc.S
+++ b/kernel/arch/arm/cortex-m7/gcc/los_exc.S
@@ -268,7 +268,7 @@ _hwiActiveCheck:
     RBIT  R2, R3
     CLZ   R2, R2
     AND   R12, R12, #1
-    ADD   R2, R2, R12, LSL #5               // calculate R2 (hwi number) as uwPid
+    ADD   R2, R2, R12, LSL #5               // calculate R2 (hwi number) as pid
     .fnend
 
     .type _ExcInMSP, %function
@@ -282,10 +282,7 @@ _ExcInMSP:
     PUSH  {R3}
     MRS   R12, PRIMASK                  // store message-->exc: disable int?
     PUSH {R4-R12}                       // store message-->exc: {R4-R12}
-#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined(__FPU_USED) && (__FPU_USED == 1U)))
     VPUSH {D8-D15}
-#endif
     B     _handleEntry
   .fnend
 
diff --git a/kernel/arch/arm/cortex-m7/iar/los_exc.S b/kernel/arch/arm/cortex-m7/iar/los_exc.S
index f1efbf3c..28bd44db 100644
--- a/kernel/arch/arm/cortex-m7/iar/los_exc.S
+++ b/kernel/arch/arm/cortex-m7/iar/los_exc.S
@@ -195,7 +195,7 @@ _hwiActiveCheck
     RBIT  R2, R3
     CLZ   R2, R2
     AND   R12, R12, #1
-    ADD   R2, R2, R12, LSL #5               ; calculate R2 (hwi number) as uwPid
+    ADD   R2, R2, R12, LSL #5               ; calculate R2 (hwi number) as pid
 
 _ExcInMSP
     CMP   LR, #0XFFFFFFED