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Description: liteos-m refactoring

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Reviewed-by: wangmihu, zhushengle
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likailong
2020-12-02 19:40:34 +08:00
parent f7d1409762
commit 72c4acf01e
160 changed files with 15478 additions and 13235 deletions
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kernel/arch/arm/cortex-m3/keil/cmsis/ARMCM3.h Executable file
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/**************************************************************************//**
* @file ARMCM3.h
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMCM3 Device Series
* @version V1.08
* @date 23. November 2012
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef ARMCM3_H
#define ARMCM3_H
#ifdef __cplusplus
extern "C" {
#endif
/* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn
{
/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 HardFault Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
/* ---------------------- ARMCM3 Specific Interrupt Numbers --------------------- */
WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
RTC_IRQn = 1, /*!< Real Time Clock Interrupt */
TIM0_IRQn = 2, /*!< Timer0 / Timer1 Interrupt */
TIM2_IRQn = 3, /*!< Timer2 / Timer3 Interrupt */
MCIA_IRQn = 4, /*!< MCIa Interrupt */
MCIB_IRQn = 5, /*!< MCIb Interrupt */
UART0_IRQn = 6, /*!< UART0 Interrupt */
UART1_IRQn = 7, /*!< UART1 Interrupt */
UART2_IRQn = 8, /*!< UART2 Interrupt */
UART4_IRQn = 9, /*!< UART4 Interrupt */
AACI_IRQn = 10, /*!< AACI / AC97 Interrupt */
CLCD_IRQn = 11, /*!< CLCD Combined Interrupt */
ENET_IRQn = 12, /*!< Ethernet Interrupt */
USBDC_IRQn = 13, /*!< USB Device Interrupt */
USBHC_IRQn = 14, /*!< USB Host Controller Interrupt */
CHLCD_IRQn = 15, /*!< Character LCD Interrupt */
FLEXRAY_IRQn = 16, /*!< Flexray Interrupt */
CAN_IRQn = 17, /*!< CAN Interrupt */
LIN_IRQn = 18, /*!< LIN Interrupt */
I2C_IRQn = 19, /*!< I2C ADC/DAC Interrupt */
CPU_CLCD_IRQn = 28, /*!< CPU CLCD Combined Interrupt */
UART3_IRQn = 30, /*!< UART3 Interrupt */
SPI_IRQn = 31, /*!< SPI Touchscreen Interrupt */
} IRQn_Type;
/* ================================================================================ */
/* ================ Processor and Core Peripheral Section ================ */
/* ================================================================================ */
/* -------- Configuration of the Cortex-M4 Processor and Core Peripherals ------- */
#define __CM3_REV 0x0201 /*!< Core revision r2p1 */
#define __MPU_PRESENT 1 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#include <core_cm3.h> /* Processor and core peripherals */
/* ================================================================================ */
/* ================ Device Specific Peripheral Section ================ */
/* ================================================================================ */
/* ------------------- Start of section using anonymous unions ------------------ */
#if defined(__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined(__ICCARM__)
#pragma language=extended
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__TMS470__)
/* anonymous unions are enabled by default */
#elif defined(__TASKING__)
#pragma warning 586
#else
#warning Not supported compiler type
#endif
/* ================================================================================ */
/* ================ CPU FPGA System (CPU_SYS) ================ */
/* ================================================================================ */
typedef struct
{
__I uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
__IO uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
__I uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
__IO uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
__I uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
__IO uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
uint32_t RESERVED0[2];
__IO uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
__IO uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
__IO uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
uint32_t RESERVED1[3];
__IO uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
__IO uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
} ARM_CPU_SYS_TypeDef;
/* ================================================================================ */
/* ================ DUT FPGA System (DUT_SYS) ================ */
/* ================================================================================ */
typedef struct
{
__I uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
__IO uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
__I uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
__IO uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
__IO uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
__I uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
__I uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
} ARM_DUT_SYS_TypeDef;
/* ================================================================================ */
/* ================ Timer (TIM) ================ */
/* ================================================================================ */
typedef struct
{
__IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
__I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
__IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
__O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
__I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
__I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
__IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
uint32_t RESERVED0[1];
__IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
__I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
__IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
__O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
__I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
__I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
__IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
} ARM_TIM_TypeDef;
/* ================================================================================ */
/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
/* ================================================================================ */
typedef struct
{
__IO uint32_t DR; /* Offset: 0x000 (R/W) Data */
union {
__I uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
__O uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
};
uint32_t RESERVED0[4];
__IO uint32_t FR; /* Offset: 0x018 (R/W) Flags */
uint32_t RESERVED1[1];
__IO uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
__IO uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
__IO uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
__IO uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
__IO uint32_t CR; /* Offset: 0x030 (R/W) Control */
__IO uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
__IO uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
__IO uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
__IO uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
__O uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
__IO uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
} ARM_UART_TypeDef;
/* -------------------- End of section using anonymous unions ------------------- */
#if defined(__CC_ARM)
#pragma pop
#elif defined(__ICCARM__)
/* leave anonymous unions enabled */
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__TMS470__)
/* anonymous unions are enabled by default */
#elif defined(__TASKING__)
#pragma warning restore
#else
#warning Not supported compiler type
#endif
/* ================================================================================ */
/* ================ Peripheral memory map ================ */
/* ================================================================================ */
/* -------------------------- CPU FPGA memory map ------------------------------- */
#define ARM_FLASH_BASE (0x00000000UL)
#define ARM_RAM_BASE (0x20000000UL)
#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000)
#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000)
/* -------------------------- DUT FPGA memory map ------------------------------- */
#define ARM_APB_BASE (0x40000000UL)
#define ARM_AHB_BASE (0x4FF00000UL)
#define ARM_DMC_BASE (0x60000000UL)
#define ARM_SMC_BASE (0xA0000000UL)
#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000)
#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000)
#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000)
#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000)
#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000)
#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000)
#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000)
/* ================================================================================ */
/* ================ Peripheral declaration ================ */
/* ================================================================================ */
/* -------------------------- CPU FPGA Peripherals ------------------------------ */
#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
/* -------------------------- DUT FPGA Peripherals ------------------------------ */
#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
#ifdef __cplusplus
}
#endif
#endif /* ARMCM3_H */

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kernel/arch/arm/cortex-m3/keil/cmsis/core_cm3.h Executable file
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kernel/arch/arm/cortex-m3/keil/cmsis/core_cmFunc.h Executable file
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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V3.20
* @date 25. February 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
#include <stdint.h>
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
__ASM volatile ("");
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
__ASM volatile ("");
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

688
kernel/arch/arm/cortex-m3/keil/cmsis/core_cmInstr.h Executable file
View File

@@ -0,0 +1,688 @@
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V3.20
* @date 05. March 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
#include <stdint.h>
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constrant "l"
* Otherwise, use general registers, specified by constrant "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (short)__builtin_bswap16(value);
#else
uint32_t result;
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << (32 - op2));
}
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint32_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

1
kernel/arch/arm/cortex-m4/iar/los_hw.h → kernel/arch/arm/cortex-m3/keil/los_context.h
View File

@@ -37,7 +37,6 @@
#ifndef _LOS_HW_H
#define _LOS_HW_H
#include "los_base.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {

163
kernel/arch/arm/cortex-m3/keil/los_dispatch.S Executable file
View File

@@ -0,0 +1,163 @@
;
; Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
; Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
;
; Redistribution and use in source and binary forms, with or without modification,
; are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice, this list of
; conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice, this list
; of conditions and the following disclaimer in the documentation and/or other materials
; provided with the distribution.
;
; 3. Neither the name of the copyright holder nor the names of its contributors may be used
; to endorse or promote products derived from this software without specific prior written
; permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
PRESERVE8
EXPORT LOS_IntLock
EXPORT LOS_IntUnLock
EXPORT LOS_IntRestore
EXPORT LOS_StartToRun
EXPORT osTaskSchedule
EXPORT osPendSV
IMPORT g_losTask
IMPORT g_taskSwitchHook
IMPORT g_taskScheduled
OS_NVIC_INT_CTRL EQU 0xE000ED04
OS_NVIC_SYSPRI2 EQU 0xE000ED20
OS_NVIC_PENDSV_PRI EQU 0xF0F00000
OS_NVIC_PENDSVSET EQU 0x10000000
OS_TASK_STATUS_RUNNING EQU 0x0010
AREA |.text|, CODE, READONLY
THUMB
REQUIRE8
LOS_StartToRun
LDR R4, =OS_NVIC_SYSPRI2
LDR R5, =OS_NVIC_PENDSV_PRI
STR R5, [R4]
LDR R0, =g_taskScheduled
MOV R1, #1
STR R1, [R0]
MOV R0, #2
MSR CONTROL, R0
LDR R0, =g_losTask
LDR R2, [R0, #4]
LDR R0, =g_losTask
STR R2, [R0]
LDR R3, =g_losTask
LDR R0, [R3]
LDRH R7, [R0 , #4]
MOV R8, #OS_TASK_STATUS_RUNNING
ORR R7, R7, R8
STRH R7, [R0 , #4]
LDR R12, [R0]
;ADD R12, R12, #100
ADD R12, R12, #36
LDMFD R12!, {R0-R7}
;ADD R12, R12, #72
MSR PSP, R12
;VPUSH S0;
;VPOP S0;
MOV LR, R5
;MSR xPSR, R7
CPSIE I
BX R6
LOS_IntLock
MRS R0, PRIMASK
CPSID I
BX LR
LOS_IntUnLock
MRS R0, PRIMASK
CPSIE I
BX LR
LOS_IntRestore
MSR PRIMASK, R0
BX LR
osTaskSchedule
LDR R0, =OS_NVIC_INT_CTRL
LDR R1, =OS_NVIC_PENDSVSET
STR R1, [R0]
BX LR
osPendSV
MRS R12, PRIMASK
CPSID I
LDR R2, =g_taskSwitchHook
LDR R2, [R2]
CBZ R2, TaskSwitch
PUSH {R12, LR}
BLX R2
POP {R12, LR}
TaskSwitch
MRS R0, PSP
STMFD R0!, {R4-R12}
;VSTMDB R0!, {D8-D15}
LDR R5, =g_losTask
LDR R6, [R5]
STR R0, [R6]
LDRH R7, [R6 , #4]
MOV R8,#OS_TASK_STATUS_RUNNING
BIC R7, R7, R8
STRH R7, [R6 , #4]
LDR R0, =g_losTask
LDR R0, [R0, #4]
STR R0, [R5]
LDRH R7, [R0 , #4]
MOV R8, #OS_TASK_STATUS_RUNNING
ORR R7, R7, R8
STRH R7, [R0 , #4]
LDR R1, [R0]
;VLDMIA R1!, {D8-D15}
LDMFD R1!, {R4-R12}
MSR PSP, R1
MSR PRIMASK, R12
BX LR
END

149
kernel/arch/arm/cortex-m3/keil/los_hw.c Executable file
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/*
* Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_task.h"
#include "securec.h"
#include "ARMCM3.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
/* ****************************************************************************
Function : OsTaskExit
Description : Task exit function
Input : None
Output : None
Return : None
**************************************************************************** */
LITE_OS_SEC_TEXT_MINOR VOID OsTaskExit(VOID)
{
LOS_IntLock();
for(;;);
}
/* ****************************************************************************
Function : OsTskStackInit
Description : Task stack initialization function
Input : taskID --- TaskID
stackSize --- Total size of the stack
topStack --- Top of task's stack
Output : None
Return : Context pointer
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT VOID *OsTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
{
TaskContext *context = NULL;
errno_t result;
/* initialize the task stack, write magic num to stack top */
result = memset_s(topStack, stackSize, (INT32)(OS_TASK_STACK_INIT & 0xFF), stackSize);
if (result != EOK) {
printf("memset_s is failed:%s[%d]\r\n", __FUNCTION__, __LINE__);
}
*((UINT32 *)(topStack)) = OS_TASK_MAGIC_WORD;
context = (TaskContext *)(((UINTPTR)topStack + stackSize) - sizeof(TaskContext));
#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined(__FPU_USED) && (__FPU_USED == 1U)))
context->S16 = 0xAA000010;
context->S17 = 0xAA000011;
context->S18 = 0xAA000012;
context->S19 = 0xAA000013;
context->S20 = 0xAA000014;
context->S21 = 0xAA000015;
context->S22 = 0xAA000016;
context->S23 = 0xAA000017;
context->S24 = 0xAA000018;
context->S25 = 0xAA000019;
context->S26 = 0xAA00001A;
context->S27 = 0xAA00001B;
context->S28 = 0xAA00001C;
context->S29 = 0xAA00001D;
context->S30 = 0xAA00001E;
context->S31 = 0xAA00001F;
context->S0 = 0xAA000000;
context->S1 = 0xAA000001;
context->S2 = 0xAA000002;
context->S3 = 0xAA000003;
context->S4 = 0xAA000004;
context->S5 = 0xAA000005;
context->S6 = 0xAA000006;
context->S7 = 0xAA000007;
context->S8 = 0xAA000008;
context->S9 = 0xAA000009;
context->S10 = 0xAA00000A;
context->S11 = 0xAA00000B;
context->S12 = 0xAA00000C;
context->S13 = 0xAA00000D;
context->S14 = 0xAA00000E;
context->S15 = 0xAA00000F;
context->FPSCR = 0x00000000;
context->NO_NAME = 0xAA000011;
#endif
context->uwR4 = 0x04040404L;
context->uwR5 = 0x05050505L;
context->uwR6 = 0x06060606L;
context->uwR7 = 0x07070707L;
context->uwR8 = 0x08080808L;
context->uwR9 = 0x09090909L;
context->uwR10 = 0x10101010L;
context->uwR11 = 0x11111111L;
context->uwPriMask = 0;
context->uwR0 = taskID;
context->uwR1 = 0x01010101L;
context->uwR2 = 0x02020202L;
context->uwR3 = 0x03030303L;
context->uwR12 = 0x12121212L;
context->uwLR = (UINT32)(UINTPTR)OsTaskExit;
context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
context->uwxPSR = 0x01000000L;
return (VOID *)context;
}
LITE_OS_SEC_TEXT_INIT VOID OsEnterSleep(VOID)
{
__DSB();
__WFI();
__ISB();
}
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */

287
kernel/arch/arm/cortex-m3/keil/los_hw_exc.S Executable file
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@@ -0,0 +1,287 @@
;
; Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
; Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
;
; Redistribution and use in source and binary forms, with or without modification,
; are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice, this list of
; conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice, this list
; of conditions and the following disclaimer in the documentation and/or other materials
; provided with the distribution.
;
; 3. Neither the name of the copyright holder nor the names of its contributors may be used
; to endorse or promote products derived from this software without specific prior written
; permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
PRESERVE8
AREA |.text|, CODE, READONLY
THUMB
EXPORT OsExcNMI
EXPORT OsExcHardFault
EXPORT OsExcMemFault
EXPORT OsExcBusFault
EXPORT OsExcUsageFault
EXPORT OsExcSvcCall
IMPORT OsExcHandleEntry
;IMPORT g_vuwLosFlag
;IMPORT g_curNestCount
IMPORT g_uwExcTbl
IMPORT g_taskScheduled
OS_FLG_BGD_ACTIVE EQU 0x0002
OS_EXC_CAUSE_NMI EQU 16
OS_EXC_CAUSE_HARDFAULT EQU 17
HF_DEBUGEVT EQU 20
HF_VECTBL EQU 21
FLAG_ADDR_VALID EQU 0x10000
FLAG_HWI_ACTIVE EQU 0x20000
FLAG_NO_FLOAT EQU 0x10000000
OS_NVIC_FSR EQU 0xE000ED28 ;include BusFault/MemFault/UsageFault State Regeister
OS_NVIC_HFSR EQU 0xE000ED2C ;HardFault State Regeister
OS_NVIC_BFAR EQU 0xE000ED38
OS_NVIC_MMAR EQU 0xE000ED34
OS_NVIC_ACT_BASE EQU 0xE000E300
OS_NVIC_SHCSRS EQU 0xE000ED24
OS_NVIC_SHCSR_MASK EQU 0xC00
OsExcNMI
MOV R0, #OS_EXC_CAUSE_NMI
MOV R1, #0
B osExcDispatch
OsExcHardFault
MOV R0, #OS_EXC_CAUSE_HARDFAULT
LDR R2, =OS_NVIC_HFSR
LDR R2, [R2]
MOV R1, #HF_DEBUGEVT
ORR R0, R0, R1, LSL #0x8
TST R2, #0x80000000
BNE osExcDispatch ; DEBUGEVT
AND R0, R0 , #0x000000FF
MOV R1, #HF_VECTBL
ORR R0, R0, R1, LSL #0x8
TST R2, #0x00000002
BNE osExcDispatch ; VECTBL
;if not DEBUGEVT and VECTBL then is FORCED
AND R0, R0, #0x000000FF
LDR R2, =OS_NVIC_FSR
LDR R2, [R2]
TST R2, #0x8000 ; BFARVALID
BNE _HFBusFault ; BusFault
TST R2, #0x80 ; MMARVALID
BNE _HFMemFault ; MemFault
MOV R12,#0
B osHFExcCommonBMU
_HFBusFault
LDR R1, =OS_NVIC_BFAR
LDR R1, [R1]
MOV R12, #FLAG_ADDR_VALID
B osHFExcCommonBMU
_HFMemFault
LDR R1, =OS_NVIC_MMAR
LDR R1, [R1]
MOV R12, #FLAG_ADDR_VALID
osHFExcCommonBMU
CLZ R2, R2
LDR R3, =g_uwExcTbl
ADD R3, R3, R2
LDRB R2, [R3]
ORR R0, R0, R2, LSL #0x8
ORR R0, R0 ,R12
B osExcDispatch
OsExcSvcCall
TST LR, #0x4
ITE EQ
MRSEQ R0, MSP
MRSNE R0, PSP
LDR R1, [R0,#24]
LDRB R0, [R1,#-2]
MOV R1, #0
B osExcDispatch
OsExcBusFault
LDR R0, =OS_NVIC_FSR
LDR R0, [R0]
TST R0, #0x8000 ; BFARVALID
BEQ _ExcBusNoADDR
LDR R1, =OS_NVIC_BFAR
LDR R1, [R1]
MOV R12, #FLAG_ADDR_VALID
AND R0, R0, #0x1F00
B osExcCommonBMU
_ExcBusNoADDR
MOV R12,#0
B osExcCommonBMU
OsExcMemFault
LDR R0, =OS_NVIC_FSR
LDR R0, [R0]
TST R0, #0x80 ; MMARVALID
BEQ _ExcMemNoADDR
LDR R1, =OS_NVIC_MMAR
LDR R1, [R1]
MOV R12, #FLAG_ADDR_VALID
AND R0, R0, #0x1B
B osExcCommonBMU
_ExcMemNoADDR
MOV R12,#0
B osExcCommonBMU
OsExcUsageFault
LDR R0, =OS_NVIC_FSR
LDR R0, [R0]
MOV R1, #0x030F
LSL R1, R1, #16
AND R0, R0, R1
MOV R12, #0
osExcCommonBMU
CLZ R0, R0
LDR R3, =g_uwExcTbl
ADD R3, R3, R0
LDRB R0, [R3]
ORR R0, R0, R12
; R0 -- EXCCAUSE(bit 16 is 1 if EXCADDR valid), R1 -- EXCADDR
osExcDispatch
LDR R2, =OS_NVIC_ACT_BASE
MOV R12, #8 ; R12 is hwi check loop counter
_hwiActiveCheck
LDR R3, [R2] ; R3 store active hwi register when exc
CMP R3, #0
BEQ _hwiActiveCheckNext
; exc occured in IRQ
ORR R0, R0, #FLAG_HWI_ACTIVE
RBIT R2, R3
CLZ R2, R2
AND R12, R12, #1
ADD R2, R2, R12, LSL #5 ; calculate R2 (hwi number) as uwPid
_ExcInMSP
CMP LR, #0XFFFFFFED
BNE _NoFloatInMsp
ADD R3, R13, #104
PUSH {R3}
MRS R12, PRIMASK ; store message-->exc: disable int?
PUSH {R4-R12} ; store message-->exc: {R4-R12}
;VPUSH {D8-D15}
B _handleEntry
_NoFloatInMsp
ADD R3, R13, #32
PUSH {R3} ; save IRQ SP ; store message-->exc: MSP(R13)
MRS R12, PRIMASK ; store message-->exc: disable int?
PUSH {R4-R12} ; store message-->exc: {R4-R12}
ORR R0, R0, #FLAG_NO_FLOAT
B _handleEntry
_hwiActiveCheckNext
ADD R2, R2, #4 ; next NVIC ACT ADDR
SUBS R12, R12, #1
BNE _hwiActiveCheck
;/*NMI interrupt excption*/
LDR R2, =OS_NVIC_SHCSRS
LDRH R2,[R2]
LDR R3,=OS_NVIC_SHCSR_MASK
AND R2, R2,R3
CMP R2,#0
BNE _ExcInMSP
; exc occured in Task or Init or exc
; reserved for register info from task stack
LDR R2, =g_taskScheduled
LDR R2, [R2]
TST R2, #1 ; OS_FLG_BGD_ACTIVE
BEQ _ExcInMSP ; if exc occured in Init then branch
CMP LR, #0xFFFFFFED ;auto push floating registers
BNE _NoFloatInPsp
; exc occured in Task
MOV R2, R13
SUB R13, #96 ; add 8 Bytes reg(for STMFD)
MRS R3, PSP
ADD R12, R3, #104
PUSH {R12} ; save task SP
MRS R12, PRIMASK
PUSH {R4-R12}
;VPUSH {D8-D15}
; copy auto saved task register
LDMFD R3!, {R4-R11} ; R4-R11 store PSP reg(auto push when exc in task)
;VLDMIA R3!, {D8-D15}
;VSTMDB R2!, {D8-D15}
STMFD R2!, {R4-R11}
B _handleEntry
_NoFloatInPsp
MOV R2, R13 ;no auto push floating registers
SUB R13, #32 ; add 8 Bytes reg(for STMFD)
MRS R3, PSP
ADD R12, R3, #32
PUSH {R12} ; save task SP
MRS R12, PRIMASK
PUSH {R4-R12}
LDMFD R3, {R4-R11} ; R4-R11 store PSP reg(auto push when exc in task)
STMFD R2!, {R4-R11}
ORR R0, R0, #FLAG_NO_FLOAT
_handleEntry
MOV R3, R13 ; R13:the 4th param
CPSID I
CPSID F
B OsExcHandleEntry
NOP
END

267
kernel/arch/arm/cortex-m3/keil/los_hw_tick.c Executable file
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/*
* Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_tick.h"
#include "los_interrupt.h"
#include "ARMCM3.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cpluscplus */
#endif /* __cpluscplus */
#define TICK_CHECK 0x4000000
#define CYCLE_CHECK 0xFFFFFFFFU
#define SHIFT_32_BIT 32
/* ****************************************************************************
Function : OsTickStart
Description : Configure Tick Interrupt Start
Input : none
output : none
return : LOS_OK - Success , or LOS_ERRNO_TICK_CFG_INVALID - failed
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT UINT32 OsTickStart(VOID)
{
UINT32 ret;
if ((OS_SYS_CLOCK == 0) ||
(LOSCFG_BASE_CORE_TICK_PER_SECOND == 0) ||
(LOSCFG_BASE_CORE_TICK_PER_SECOND > OS_SYS_CLOCK)) {
return LOS_ERRNO_TICK_CFG_INVALID;
}
#if (OS_HWI_WITH_ARG == YES)
OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)OsTickHandler, NULL);
#else
OsSetVector(SysTick_IRQn, OsTickHandler);
#endif
g_cyclesPerTick = OS_SYS_CLOCK / LOSCFG_BASE_CORE_TICK_PER_SECOND;
g_ullTickCount = 0;
ret = SysTick_Config(g_cyclesPerTick);
if (ret == 1) {
return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
}
return LOS_OK;
}
#if (LOSCFG_KERNEL_TICKLESS == YES)
/* ****************************************************************************
Function : LOS_SysTickReload
Description : reconfig systick, and clear SysTick_IRQn
Input : cyclesPerTick --- cycles Per Tick
output : none
return : none
**************************************************************************** */
LITE_OS_SEC_TEXT_MINOR VOID LOS_SysTickReload(UINT32 cyclesPerTick)
{
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
NVIC_ClearPendingIRQ(SysTick_IRQn);
SysTick->LOAD = (UINT32)(cyclesPerTick - 1UL); /* set reload register */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
}
#endif
/* ****************************************************************************
Function : LOS_SysTickCurrCycleGet
Description : Get System cycle count
Input : none
output : none
return : hwCycle --- the system cycle count
**************************************************************************** */
LITE_OS_SEC_TEXT_MINOR UINT32 LOS_SysTickCurrCycleGet(VOID)
{
UINT32 hwCycle;
UINTPTR intSave;
intSave = LOS_IntLock();
hwCycle = SysTick->VAL;
/* tick has come, but may interrupt environment, not counting the Tick interrupt response, to do +1 */
if ((SCB->ICSR & TICK_CHECK) != 0) {
hwCycle = SysTick->VAL;
hwCycle += g_cyclesPerTick;
}
LOS_IntRestore(intSave);
return hwCycle;
}
/* ****************************************************************************
Function : LOS_GetCpuCycle
Description : Get System cycle count
Input : none
output : cntHi --- CpuTick High 4 byte
cntLo --- CpuTick Low 4 byte
return : none
**************************************************************************** */
LITE_OS_SEC_TEXT_MINOR VOID LOS_GetCpuCycle(UINT32 *cntHi, UINT32 *cntLo)
{
UINT64 swTick;
UINT64 cycle;
UINT32 hwCycle;
UINTPTR intSave;
intSave = LOS_IntLock();
swTick = g_ullTickCount;
hwCycle = SysTick->VAL;
/* tick has come, but may interrupt environment, not counting the Tick interrupt response, to do +1 */
if ((SCB->ICSR & TICK_CHECK) != 0) {
hwCycle = SysTick->VAL;
swTick++;
}
cycle = (((swTick) * g_cyclesPerTick) + (g_cyclesPerTick - hwCycle));
*cntHi = cycle >> SHIFT_32_BIT;
*cntLo = cycle & CYCLE_CHECK;
LOS_IntRestore(intSave);
return;
}
/* ****************************************************************************
Function : LOS_GetSystickCycle
Description : Get Sys tick cycle count
Input : none
output : cntHi --- SysTick count High 4 byte
cntLo --- SysTick count Low 4 byte
return : none
**************************************************************************** */
LITE_OS_SEC_TEXT_MINOR VOID LOS_GetSystickCycle(UINT32 *cntHi, UINT32 *cntLo)
{
UINT64 swTick;
UINT64 cycle;
UINT32 hwCycle;
UINTPTR intSave;
UINT32 systickLoad;
UINT32 systickCur;
intSave = LOS_IntLock();
swTick = g_ullTickCount;
systickLoad = SysTick->LOAD;
systickCur = SysTick->VAL;
if (systickLoad < systickCur) {
LOS_IntRestore(intSave);
return;
}
hwCycle = systickLoad - systickCur;
/* tick has come, but may interrupt environment, not counting the Tick interrupt response, to do +1 */
if ((SCB->ICSR & TICK_CHECK) != 0) {
hwCycle = systickLoad - systickCur;
swTick++;
}
cycle = hwCycle + swTick * systickLoad;
*cntHi = cycle >> SHIFT_32_BIT;
*cntLo = cycle & CYCLE_CHECK;
LOS_IntRestore(intSave);
return;
}
#define MAX_HOUR 24
#define MAX_MINUTES 60
#define MAX_SECONDS 60
#define MILSEC 1000
#define RTC_WAKEUPCLOCK_RTCCLK 32768
#define RTC_WAKEUPCLOCK_RTCCLK_DIV 16
#define RTC_CALIBRATE_SLEEP_TIME 8
#define MACHINE_CYCLE_DEALAY_TIMES 4000
static BOOL g_sysSleepFlag = FALSE;
VOID LOS_TickLock(VOID)
{
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
}
VOID LOS_TickUnlock(VOID)
{
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
}
BOOL LOS_GetSysSleepFlag(VOID)
{
return g_sysSleepFlag;
}
VOID LOS_ClearSysSleepFlag(VOID)
{
g_sysSleepFlag = FALSE;
}
VOID LOS_EnterSleep(LOS_SysSleepEnum sleep)
{
__DSB();
__WFI();
__ISB();
}
VOID LOS_SystemWakeup(UINT32 hwiIndex)
{
}
//extern unsigned int SystemCoreClock;
void LOS_HalDelay(UINT32 ticks)
{
UINT32 delayTimes;
#if 0
/* there are 4 machine cycle in loop */
if ((ticks * (SystemCoreClock / MACHINE_CYCLE_DEALAY_TIMES)) >= 0xffffffff) {
delayTimes = 0xffffffff;
} else {
delayTimes = ticks * (SystemCoreClock / MACHINE_CYCLE_DEALAY_TIMES);
}
while (delayTimes) {
delayTimes = delayTimes - 1;
}
#endif
}
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cpluscplus */
#endif /* __cpluscplus */

450
kernel/arch/arm/cortex-m3/keil/los_interrupt.c Executable file
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@@ -0,0 +1,450 @@
/*
* Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_interrupt.h"
#include <stdarg.h>
#include "los_debug.h"
#include "los_task.h"
#if (LOSCFG_KERNEL_TICKLESS == YES)
#include "los_tick.h"
#endif
#include "ARMCM3.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
/*lint -save -e40 -e522 -e533*/
__weak VOID SysTickHandler(VOID)
{
return;
}
UINT32 g_vuwIntCount = 0;
/*lint -restore*/
#ifdef __ICCARM__
#pragma location = ".data.vector"
#elif defined(__CC_ARM) || defined(__GNUC__)
LITE_OS_SEC_VEC
#endif
HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT] = {
(HWI_PROC_FUNC)0, // [0] Top of Stack
(HWI_PROC_FUNC)Reset_Handler, // [1] reset
(HWI_PROC_FUNC)OsHwiDefaultHandler, // [2] NMI Handler
(HWI_PROC_FUNC)OsHwiDefaultHandler, // [3] Hard Fault Handler
(HWI_PROC_FUNC)OsHwiDefaultHandler, // [4] MPU Fault Handler
(HWI_PROC_FUNC)OsHwiDefaultHandler, // [5] Bus Fault Handler
(HWI_PROC_FUNC)OsHwiDefaultHandler, // [6] Usage Fault Handler
(HWI_PROC_FUNC)0, // [7] Reserved
(HWI_PROC_FUNC)0, // [8] Reserved
(HWI_PROC_FUNC)0, // [9] Reserved
(HWI_PROC_FUNC)0, // [10] Reserved
(HWI_PROC_FUNC)OsHwiDefaultHandler, // [11] SVCall Handler
(HWI_PROC_FUNC)OsHwiDefaultHandler, // [12] Debug Monitor Handler
(HWI_PROC_FUNC)0, // [13] Reserved
(HWI_PROC_FUNC)osPendSV, // [14] PendSV Handler
(HWI_PROC_FUNC)SysTickHandler, // [15] SysTick Handler
};
#if (OS_HWI_WITH_ARG == YES)
HWI_SLAVE_FUNC g_hwiSlaveForm[OS_VECTOR_CNT] = {{ (HWI_PROC_FUNC)0, (HWI_ARG_T)0 }};
#else
HWI_PROC_FUNC g_hwiSlaveForm[OS_VECTOR_CNT] = {0};
#endif
/* ****************************************************************************
Function : OsIntNumGet
Description : Get a interrupt number
Input : None
Output : None
Return : Interrupt Indexes number
**************************************************************************** */
LITE_OS_SEC_TEXT_MINOR UINT32 OsIntNumGet(VOID)
{
return __get_IPSR();
}
/* ****************************************************************************
Function : OsHwiDefaultHandler
Description : default handler of the hardware interrupt
Input : None
Output : None
Return : None
**************************************************************************** */
/*lint -e529*/
LITE_OS_SEC_TEXT_MINOR VOID OsHwiDefaultHandler(VOID)
{
UINT32 irqNum = OsIntNumGet();
PRINT_ERR("%s irqnum:%d\n", __FUNCTION__, irqNum);
while (1) {}
}
/* ****************************************************************************
Function : OsInterrupt
Description : Hardware interrupt entry function
Input : None
Output : None
Return : None
**************************************************************************** */
LITE_OS_SEC_TEXT VOID OsInterrupt(VOID)
{
UINT32 hwiIndex;
UINT32 intSave;
#if (LOSCFG_KERNEL_RUNSTOP == YES)
SCB->SCR &= (UINT32) ~((UINT32)SCB_SCR_SLEEPDEEP_Msk);
#endif
intSave = LOS_IntLock();
g_vuwIntCount++;
LOS_IntRestore(intSave);
hwiIndex = OsIntNumGet();
#if (LOSCFG_KERNEL_TICKLESS == YES)
osUpdateKernelTickCount(hwiIndex);
#endif
#if (OS_HWI_WITH_ARG == YES)
if (g_hwiSlaveForm[hwiIndex].pfnHandler != 0) {
g_hwiSlaveForm[hwiIndex].pfnHandler((VOID *)g_hwiSlaveForm[hwiIndex].pParm);
}
#else
if (g_hwiSlaveForm[hwiIndex] != 0) {
g_hwiSlaveForm[hwiIndex]();
}
#endif
intSave = LOS_IntLock();
g_vuwIntCount--;
LOS_IntRestore(intSave);
}
/* ****************************************************************************
Function : LOS_HwiCreate
Description : create hardware interrupt
Input : hwiNum --- hwi num to create
hwiPrio --- priority of the hwi
mode --- unused
handler --- hwi handler
arg --- param of the hwi handler
Output : None
Return : LOS_OK on success or error code on failure
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT UINT32 LOS_HwiCreate(HWI_HANDLE_T hwiNum,
HWI_PRIOR_T hwiPrio,
HWI_MODE_T mode,
HWI_PROC_FUNC handler,
HWI_ARG_T arg)
{
UINTPTR intSave;
if (handler == NULL) {
return OS_ERRNO_HWI_PROC_FUNC_NULL;
}
if (hwiNum >= OS_HWI_MAX_NUM) {
return OS_ERRNO_HWI_NUM_INVALID;
}
if (g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] != (HWI_PROC_FUNC)OsHwiDefaultHandler) {
return OS_ERRNO_HWI_ALREADY_CREATED;
}
if (hwiPrio > OS_HWI_PRIO_LOWEST) {
return OS_ERRNO_HWI_PRIO_INVALID;
}
intSave = LOS_IntLock();
#if (OS_HWI_WITH_ARG == YES)
OsSetVector(hwiNum, handler, arg);
#else
OsSetVector(hwiNum, handler);
#endif
NVIC_EnableIRQ((IRQn_Type)hwiNum);
NVIC_SetPriority((IRQn_Type)hwiNum, hwiPrio);
LOS_IntRestore(intSave);
return LOS_OK;
}
/* ****************************************************************************
Function : LOS_HwiDelete
Description : Delete hardware interrupt
Input : hwiNum --- hwi num to delete
Output : None
Return : LOS_OK on success or error code on failure
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT UINT32 LOS_HwiDelete(HWI_HANDLE_T hwiNum)
{
UINT32 intSave;
if (hwiNum >= OS_HWI_MAX_NUM) {
return OS_ERRNO_HWI_NUM_INVALID;
}
NVIC_DisableIRQ((IRQn_Type)hwiNum);
intSave = LOS_IntLock();
g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)OsHwiDefaultHandler;
LOS_IntRestore(intSave);
return LOS_OK;
}
#define OS_NVIC_INT_CTRL_SIZE 4
#define OS_NVIC_SHCSR_SIZE 4
#define FAULT_STATUS_REG_BIT 32
#define USGFAULT (1 << 18)
#define BUSFAULT (1 << 17)
#define MEMFAULT (1 << 16)
#define DIV0FAULT (1 << 4)
#define HARDFAULT_IRQN (-13)
static ExcInfoArray g_excArray[OS_EXC_TYPE_MAX];
UINT32 g_curNestCount = 0;
static ExcInfo g_excInfo;
static EVENT_CB_S g_excEvent;
UINT8 g_uwExcTbl[FAULT_STATUS_REG_BIT] = {
0, 0, 0, 0, 0, 0, OS_EXC_UF_DIVBYZERO, OS_EXC_UF_UNALIGNED,
0, 0, 0, 0, OS_EXC_UF_NOCP, OS_EXC_UF_INVPC, OS_EXC_UF_INVSTATE, OS_EXC_UF_UNDEFINSTR,
0, 0, 0, OS_EXC_BF_STKERR, OS_EXC_BF_UNSTKERR, OS_EXC_BF_IMPRECISERR, OS_EXC_BF_PRECISERR, OS_EXC_BF_IBUSERR,
0, 0, 0, OS_EXC_MF_MSTKERR, OS_EXC_MF_MUNSTKERR, 0, OS_EXC_MF_DACCVIOL, OS_EXC_MF_IACCVIOL
};
__attribute__((noinline)) VOID LOS_Panic(const CHAR *fmt, ...)
{
va_list ap;
va_start(ap,fmt);
PRINT_ERR(fmt, ap);
va_end(ap);
asm volatile ("swi 0");
}
UINT32 OsExcNvicDump(UINT32 index, UINT32 *excContent)
{
UINT32 *base = NULL;
UINT32 len = 0,i,j;
#define OS_NR_NVIC_EXC_DUMP_Types 7
UINT32 rgNvicBases[OS_NR_NVIC_EXC_DUMP_Types] = {OS_NVIC_SETENA_BASE, OS_NVIC_SETPEND_BASE,
OS_NVIC_INT_ACT_BASE, OS_NVIC_PRI_BASE, OS_NVIC_EXCPRI_BASE, OS_NVIC_SHCSR, OS_NVIC_INT_CTRL};
UINT32 rgNvicLens[OS_NR_NVIC_EXC_DUMP_Types] = {OS_NVIC_INT_ENABLE_SIZE, OS_NVIC_INT_PEND_SIZE,
OS_NVIC_INT_ACT_SIZE, OS_NVIC_INT_PRI_SIZE, OS_NVIC_EXCPRI_SIZE, OS_NVIC_SHCSR_SIZE, OS_NVIC_INT_CTRL_SIZE};
char strRgEnable[] = "enable";
char strRgPending[] = "pending";
char strRgActive[] = "active";
char strRgPriority[] = "priority";
char strRgException[] = "exception";
char strRgShcsr[] = "shcsr";
char strRgIntCtrl[] = "control";
char *strRgs[] = {strRgEnable, strRgPending, strRgActive, strRgPriority, strRgException, strRgShcsr, strRgIntCtrl};
(VOID)index;
(VOID)excContent;
PRINTK("OS exception NVIC dump: \n");
for (i = 0; i < OS_NR_NVIC_EXC_DUMP_Types; i++) {
base = (UINT32 *)rgNvicBases[i];
len = rgNvicLens[i];
PRINTK("interrupt %s register, base address: 0x%x, size: 0x%x\n", strRgs[i], base, len);
len = (len >> 2);
for (j = 0; j < len; j++) {
PRINTK("0x%x ", *(base + j));
}
PRINTK("\n");
}
}
UINT32 OsExcContextDump(UINT32 index, UINT32 *excContent)
{
(VOID)index;
(VOID)excContent;
PRINTK("OS exception context dump:\n");
PRINTK("Phase = 0x%x\n", g_excInfo.phase);
PRINTK("Type = 0x%x\n", g_excInfo.type);
PRINTK("FaultAddr = 0x%x\n", g_excInfo.faultAddr);
PRINTK("ThrdPid = 0x%x\n", g_excInfo.thrdPid);
PRINTK("R0 = 0x%x\n", g_excInfo.context->uwR0);
PRINTK("R1 = 0x%x\n", g_excInfo.context->uwR1);
PRINTK("R2 = 0x%x\n", g_excInfo.context->uwR2);
PRINTK("R3 = 0x%x\n", g_excInfo.context->uwR3);
PRINTK("R4 = 0x%x\n", g_excInfo.context->uwR4);
PRINTK("R5 = 0x%x\n", g_excInfo.context->uwR5);
PRINTK("R6 = 0x%x\n", g_excInfo.context->uwR6);
PRINTK("R7 = 0x%x\n", g_excInfo.context->uwR7);
PRINTK("R8 = 0x%x\n", g_excInfo.context->uwR8);
PRINTK("R9 = 0x%x\n", g_excInfo.context->uwR9);
PRINTK("R10 = 0x%x\n", g_excInfo.context->uwR10);
PRINTK("R11 = 0x%x\n", g_excInfo.context->uwR11);
PRINTK("R12 = 0x%x\n", g_excInfo.context->uwR12);
PRINTK("PriMask = 0x%x\n", g_excInfo.context->uwPriMask);
PRINTK("SP = 0x%x\n", g_excInfo.context->uwSP);
PRINTK("LR = 0x%x\n", g_excInfo.context->uwLR);
PRINTK("PC = 0x%x\n", g_excInfo.context->uwPC);
PRINTK("xPSR = 0x%x\n", g_excInfo.context->uwxPSR);
}
VOID OsDumpMsg(VOID)
{
UINT32 index = 0;
for (index = 0; index < (OS_EXC_TYPE_MAX - 1); index++) {
if (g_excArray[index].uwValid == FALSE) {
continue;
}
g_excArray[index].pFnExcInfoCb(index, g_excArray[index].pArg);
}
}
VOID OsExcNotify(VOID)
{
UINT32 ret = LOS_EventWrite(&g_excEvent, OS_EXC_EVENT);
if (ret != LOS_OK) {
PRINT_ERR("event notify failed\n");
}
}
LITE_OS_SEC_TEXT_INIT VOID OsExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid,
EXC_CONTEXT_S *excBufAddr)
{
UINT16 tmpFlag = (excType >> 16) & OS_NULL_SHORT;
g_curNestCount++;
g_vuwIntCount++;
g_excInfo.nestCnt = g_curNestCount;
g_excInfo.type = excType & OS_NULL_SHORT;
if (tmpFlag & OS_EXC_FLAG_FAULTADDR_VALID) {
g_excInfo.faultAddr = faultAddr;
} else {
g_excInfo.faultAddr = OS_EXC_IMPRECISE_ACCESS_ADDR;
}
if (g_losTask.runTask != NULL) {
if (tmpFlag & OS_EXC_FLAG_IN_HWI) {
g_excInfo.phase = OS_EXC_IN_HWI;
g_excInfo.thrdPid = pid;
} else {
g_excInfo.phase = OS_EXC_IN_TASK;
g_excInfo.thrdPid = g_losTask.runTask->taskID;
}
} else {
g_excInfo.phase = OS_EXC_IN_INIT;
g_excInfo.thrdPid = OS_NULL_INT;
}
if (excType & OS_EXC_FLAG_NO_FLOAT) {
g_excInfo.context = (EXC_CONTEXT_S *)((CHAR *)excBufAddr - LOS_OFF_SET_OF(EXC_CONTEXT_S, uwR4));
} else {
g_excInfo.context = excBufAddr;
}
OsDumpMsg();
OsExcNotify();
LOS_Reboot();
}
VOID OsExcRegister(ExcInfoType type, EXC_INFO_SAVE_CALLBACK func, VOID *arg)
{
ExcInfoArray *excInfo = NULL;
if ((type >= OS_EXC_TYPE_MAX) || (func == NULL)) {
PRINT_ERR("OsExcRegister ERROR!\n");
return;
}
excInfo = &(g_excArray[type]);
excInfo->uwType = type;
excInfo->pFnExcInfoCb = func;
excInfo->pArg = arg;
excInfo->uwValid = TRUE;
}
void OsBackTrace()
{
}
/* ****************************************************************************
Function : OsHwiInit
Description : initialization of the hardware interrupt
Input : None
Output : None
Return : None
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT VOID OsHwiInit()
{
UINT32 index;
UINT32 ret;
for (index = OS_SYS_VECTOR_CNT; index < OS_VECTOR_CNT; index++) {
g_hwiForm[index] = (HWI_PROC_FUNC)OsHwiDefaultHandler;
}
/* Exception handler register */
g_hwiForm[HARDFAULT_IRQN + OS_SYS_VECTOR_CNT] = OsExcHardFault;
g_hwiForm[NonMaskableInt_IRQn + OS_SYS_VECTOR_CNT] = OsExcNMI;
g_hwiForm[MemoryManagement_IRQn + OS_SYS_VECTOR_CNT] = OsExcMemFault;
g_hwiForm[BusFault_IRQn + OS_SYS_VECTOR_CNT] = OsExcBusFault;
g_hwiForm[UsageFault_IRQn + OS_SYS_VECTOR_CNT] = OsExcUsageFault;
g_hwiForm[SVCall_IRQn + OS_SYS_VECTOR_CNT] = OsExcSvcCall;
/* Interrupt vector table location */
SCB->VTOR = (UINT32)(UINTPTR)g_hwiForm;
#if (__CORTEX_M >= 0x03U) /* only for Cortex-M3 and above */
NVIC_SetPriorityGrouping(OS_NVIC_AIRCR_PRIGROUP);
#endif
/* Enable USGFAULT, BUSFAULT, MEMFAULT */
*(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
/* Enable DIV 0 and unaligned exception */
*(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT;
/* Init Exception Event */
ret = LOS_EventInit(&g_excEvent);
if (ret != LOS_OK) {
PRINT_ERR("[EXC]init excepiton event failed!\n");
return;
}
OsExcRegister(OS_EXC_TYPE_CONTEXT, (EXC_INFO_SAVE_CALLBACK)OsExcContextDump, NULL);
OsExcRegister(OS_EXC_TYPE_NVIC, (EXC_INFO_SAVE_CALLBACK)OsExcNvicDump, NULL);
return;
}
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */

1824
kernel/arch/arm/cortex-m4/iar/los_hwi.h → kernel/arch/arm/cortex-m3/keil/los_interrupt.h
View File

File diff suppressed because it is too large Load Diff

54
kernel/arch/arm/cortex-m3/keil/los_vendor.s Executable file
View File

@@ -0,0 +1,54 @@
;/*----------------------------------------------------------------------------
;* Huawei - LiteOS
;*----------------------------------------------------------------------------
;* Name: LOS_VENDOR.S
;* Purpose: Thread scheduler
;* Rev.: V1.0.0
;*----------------------------------------------------------------------------
;*
;* Copyright (c) 2014, Huawei Technologies Co., Ltd.
;* All rights reserved.
;* Permission to use, copy, modify, and distribute this software for any
;* purpose with or without fee is hereby granted, provided that the above
;* copyright notice and this permission notice appear in all copies.
;*THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
;*WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
;*MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
;*ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
;*WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
;*ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
;*OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
;*---------------------------------------------------------------------------*/
PRESERVE8
AREA RESET, CODE, READONLY
THUMB
IMPORT ||Image$$ARM_LIB_STACKHEAP$$ZI$$Limit||
IMPORT OsHwiDefaultHandler
EXPORT _BootVectors
EXPORT Reset_Handler
_BootVectors
DCD ||Image$$ARM_LIB_STACKHEAP$$ZI$$Limit||
DCD Reset_Handler
DCD OsHwiDefaultHandler
DCD OsHwiDefaultHandler
Reset_Handler
CPSID I
IMPORT LOS_HardBootInit
BL LOS_HardBootInit
IMPORT __main
LDR R0, =__main
BX R0
ALIGN
END

194
kernel/arch/arm/cortex-m4/iar/los_context.h Executable file
View File

@@ -0,0 +1,194 @@
/*
* Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @defgroup los_hw hardware
* @ingroup kernel
*/
#ifndef _LOS_HW_H
#define _LOS_HW_H
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
/* *
* @ingroup los_hw
* The initialization value of stack space.
*/
#define EMPTY_STACK 0xCACA
/* *
* @ingroup los_hw
* Trigger a task.
*/
#define OsTaskTrap() __asm(" TRAP #31")
/* *
* @ingroup los_hw
* Check task schedule.
*/
#define LOS_CHECK_SCHEDULE ((!g_losTaskLock))
/* *
* @ingroup los_hw
* Define the type of a task context control block.
*/
typedef struct tagTskContext {
#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined(__FPU_USED) && (__FPU_USED == 1U)))
UINT32 S16;
UINT32 S17;
UINT32 S18;
UINT32 S19;
UINT32 S20;
UINT32 S21;
UINT32 S22;
UINT32 S23;
UINT32 S24;
UINT32 S25;
UINT32 S26;
UINT32 S27;
UINT32 S28;
UINT32 S29;
UINT32 S30;
UINT32 S31;
#endif
UINT32 uwR4;
UINT32 uwR5;
UINT32 uwR6;
UINT32 uwR7;
UINT32 uwR8;
UINT32 uwR9;
UINT32 uwR10;
UINT32 uwR11;
UINT32 uwPriMask;
UINT32 uwR0;
UINT32 uwR1;
UINT32 uwR2;
UINT32 uwR3;
UINT32 uwR12;
UINT32 uwLR;
UINT32 uwPC;
UINT32 uwxPSR;
#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined(__FPU_USED) && (__FPU_USED == 1U)))
UINT32 S0;
UINT32 S1;
UINT32 S2;
UINT32 S3;
UINT32 S4;
UINT32 S5;
UINT32 S6;
UINT32 S7;
UINT32 S8;
UINT32 S9;
UINT32 S10;
UINT32 S11;
UINT32 S12;
UINT32 S13;
UINT32 S14;
UINT32 S15;
UINT32 FPSCR;
UINT32 NO_NAME;
#endif
} TaskContext;
/* *
* @ingroup los_hw
* @brief: Task stack initialization.
*
* @par Description:
* This API is used to initialize the task stack.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param taskID [IN] Type#UINT32: TaskID.
* @param stackSize [IN] Type#UINT32: Total size of the stack.
* @param topStack [IN] Type#VOID *: Top of task's stack.
*
* @retval: context Type#TaskContext *.
* @par Dependency:
* <ul><li>los_hw.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
extern VOID *OsTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack);
/**
* @ingroup los_hw
* @brief: Function to task exit.
*
* @par Description:
* This API is used to exit task.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param None.
*
* @retval: None.
* @par Dependency:
* <ul><li>los_hw.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
LITE_OS_SEC_TEXT_MINOR VOID OsTaskExit(VOID);
/* *
* @ingroup los_hw
* @brief: The M3 wait interrupt instruction.
*
* @par Description:
* This API is used to make CPU enter to power-save mode.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param None.
*
* @retval: None.
* @par Dependency:
* <ul><li>los_hw.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
extern VOID OsEnterSleep(VOID);
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_HW_H */

0
kernel/arch/arm/cortex-m4/iar/los_dispatch_iar.S → kernel/arch/arm/cortex-m4/iar/los_dispatch.S
View File

363
kernel/arch/arm/cortex-m4/iar/los_exc.c
View File

@@ -1,363 +0,0 @@
/*
* Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdio.h>
#include "los_exc_pri.h"
#include "los_memcheck_pri.h"
#ifdef LOSCFG_LIB_LIBC
#include "string.h"
#endif
#include "securec.h"
#include "los_printf.h"
#include "los_config.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
#define EXC_INT_STATUS_LEN OS_NVIC_INT_ENABLE_SIZE + OS_NVIC_INT_PEND_SIZE + OS_NVIC_INT_ACT_SIZE + \
OS_NVIC_INT_PRI_SIZE + OS_NVIC_EXCPRI_SIZE + OS_NVIC_SHCSR_SIZE + OS_NVIC_INT_CTRL_SIZE
#define TASK_ARRAY_INIT_VALUE 0xff
#define FAULT_STATUS_REG_BIT 32
#define OS_NVIC_INT_CTRL_SIZE 4
#define OS_NVIC_SHCSR_SIZE 4
#define USGFAULT (1 << 18)
#define BUSFAULT (1 << 17)
#define MEMFAULT (1 << 16)
#define DIV0FAULT (1 << 4)
#define CORE_TYPE_CORTEX_M4 2
#define HARDFAULT_IRQN (-13)
static VOID *g_excContent;
UINT32 g_curNestCount = 0;
ExcInfo g_excInfo;
__attribute__((noinline)) VOID LOS_Panic(const CHAR *fmt, ...)
{
va_list ap;
va_start(ap,fmt);
PRINT_ERR(fmt, ap);
va_end(ap);
asm volatile ("swi 0");
}
UINT8 g_uwExcTbl[FAULT_STATUS_REG_BIT] = {
0, 0, 0, 0, 0, 0, OS_EXC_UF_DIVBYZERO, OS_EXC_UF_UNALIGNED,
0, 0, 0, 0, OS_EXC_UF_NOCP, OS_EXC_UF_INVPC, OS_EXC_UF_INVSTATE, OS_EXC_UF_UNDEFINSTR,
0, 0, 0, OS_EXC_BF_STKERR, OS_EXC_BF_UNSTKERR, OS_EXC_BF_IMPRECISERR, OS_EXC_BF_PRECISERR, OS_EXC_BF_IBUSERR,
0, 0, 0, OS_EXC_MF_MSTKERR, OS_EXC_MF_MUNSTKERR, 0, OS_EXC_MF_DACCVIOL, OS_EXC_MF_IACCVIOL
};
UINT32 g_excArraySize = 0;
ExcInfoArray g_excArray[OS_EXC_TYPE_MAX - 1];
UINT32 g_LR_regs = 0;
UINT32 g_PC_regs = 0;
LITE_OS_SEC_TEXT_INIT VOID OsExcInfoDisplay(ExcInfo *exc)
{
PRINT_INFO("Phase = 0x%x\n", exc->phase);
PRINT_INFO("Type = 0x%x\n", exc->type);
PRINT_INFO("FaultAddr = 0x%x\n", exc->faultAddr);
PRINT_INFO("ThrdPid = 0x%x\n", exc->thrdPid);
PRINT_INFO("R0 = 0x%x\n", exc->context->uwR0);
PRINT_INFO("R1 = 0x%x\n", exc->context->uwR1);
PRINT_INFO("R2 = 0x%x\n", exc->context->uwR2);
PRINT_INFO("R3 = 0x%x\n", exc->context->uwR3);
PRINT_INFO("R4 = 0x%x\n", exc->context->uwR4);
PRINT_INFO("R5 = 0x%x\n", exc->context->uwR5);
PRINT_INFO("R6 = 0x%x\n", exc->context->uwR6);
PRINT_INFO("R7 = 0x%x\n", exc->context->uwR7);
PRINT_INFO("R8 = 0x%x\n", exc->context->uwR8);
PRINT_INFO("R9 = 0x%x\n", exc->context->uwR9);
PRINT_INFO("R10 = 0x%x\n", exc->context->uwR10);
PRINT_INFO("R11 = 0x%x\n", exc->context->uwR11);
PRINT_INFO("R12 = 0x%x\n", exc->context->uwR12);
PRINT_INFO("PriMask = 0x%x\n", exc->context->uwPriMask);
PRINT_INFO("SP = 0x%x\n", exc->context->uwSP);
PRINT_INFO("LR = 0x%x\n", exc->context->uwLR);
PRINT_INFO("PC = 0x%x\n", exc->context->uwPC);
PRINT_INFO("xPSR = 0x%x\n", exc->context->uwxPSR);
g_LR_regs = exc->context->uwLR;
g_PC_regs = exc->context->uwPC;
}
LITE_OS_SEC_TEXT_INIT VOID OsExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid,
EXC_CONTEXT_S *excBufAddr)
{
UINT16 tmpFlag = (excType >> 16) & OS_NULL_SHORT;
g_curNestCount++;
g_vuwIntCount++;
g_excInfo.nestCnt = g_curNestCount;
g_excInfo.type = excType & OS_NULL_SHORT;
g_excContent = (UINT32 *)g_aucTaskArray;
if (tmpFlag & OS_EXC_FLAG_FAULTADDR_VALID) {
g_excInfo.faultAddr = faultAddr;
} else {
g_excInfo.faultAddr = OS_EXC_IMPRECISE_ACCESS_ADDR;
}
if (g_losTask.runTask != NULL) {
if (tmpFlag & OS_EXC_FLAG_IN_HWI) {
g_excInfo.phase = OS_EXC_IN_HWI;
g_excInfo.thrdPid = pid;
} else {
g_excInfo.phase = OS_EXC_IN_TASK;
g_excInfo.thrdPid = g_losTask.runTask->taskID;
}
} else {
g_excInfo.phase = OS_EXC_IN_INIT;
g_excInfo.thrdPid = OS_NULL_INT;
}
if (excType & OS_EXC_FLAG_NO_FLOAT) {
g_excInfo.context = (EXC_CONTEXT_S *)((CHAR *)excBufAddr - LOS_OFF_SET_OF(EXC_CONTEXT_S, uwR4));
} else {
g_excInfo.context = excBufAddr;
}
OsExcSave2DDR();
OsExcInfoDisplay(&g_excInfo);
LOS_Reboot();
}
static VOID OsExcSaveIntStatus()
{
UINT32 ret;
UINT32 failCnt = 0;
*((UINT32 *)g_excContent) = OS_EXC_TYPE_NVIC;
g_excContent = (UINT8 *)g_excContent + sizeof(UINT32);
*((UINT32 *)g_excContent) = EXC_INT_STATUS_LEN;
g_excContent = (UINT8 *)g_excContent + sizeof(UINT32);
ret = memcpy_s(g_excContent, MAX_EXC_MEM_SIZE, (const VOID *)OS_NVIC_SETENA_BASE, OS_NVIC_INT_ENABLE_SIZE);
g_excContent = (UINT8 *)g_excContent + OS_NVIC_INT_ENABLE_SIZE;
failCnt += (ret == EOK) ? 0 : 1;
ret = memcpy_s(g_excContent, MAX_EXC_MEM_SIZE, (const VOID *)OS_NVIC_SETPEND_BASE, OS_NVIC_INT_PEND_SIZE);
g_excContent = (UINT8 *)g_excContent + OS_NVIC_INT_PEND_SIZE;
failCnt += (ret == EOK) ? 0 : 1;
ret = memcpy_s(g_excContent, MAX_EXC_MEM_SIZE, (const VOID *)OS_NVIC_INT_ACT_BASE, OS_NVIC_INT_ACT_SIZE);
g_excContent = (UINT8 *)g_excContent + OS_NVIC_INT_ACT_SIZE;
failCnt += (ret == EOK) ? 0 : 1;
ret = memcpy_s(g_excContent, MAX_EXC_MEM_SIZE, (const VOID *)OS_NVIC_PRI_BASE, OS_NVIC_INT_PRI_SIZE);
g_excContent = (UINT8 *)g_excContent + OS_NVIC_INT_PRI_SIZE;
failCnt += (ret == EOK) ? 0 : 1;
ret = memcpy_s(g_excContent, MAX_EXC_MEM_SIZE, (const VOID *)OS_NVIC_EXCPRI_BASE, OS_NVIC_EXCPRI_SIZE);
g_excContent = (UINT8 *)g_excContent + OS_NVIC_EXCPRI_SIZE;
failCnt += (ret == EOK) ? 0 : 1;
ret = memcpy_s(g_excContent, MAX_EXC_MEM_SIZE, (const VOID *)OS_NVIC_SHCSR, OS_NVIC_SHCSR_SIZE);
g_excContent = (UINT8 *)g_excContent + sizeof(UINT32);
failCnt += (ret == EOK) ? 0 : 1;
ret = memcpy_s(g_excContent, MAX_EXC_MEM_SIZE, (const VOID *)OS_NVIC_INT_CTRL, OS_NVIC_INT_CTRL_SIZE);
g_excContent = (UINT8 *)g_excContent + sizeof(UINT32);
failCnt += (ret == EOK) ? 0 : 1;
if (failCnt != 0) {
PRINT_ERR("OsExcSaveIntStatus copy register info failed, cnt:%d\n", failCnt);
}
return;
}
VOID OsExcRegister(ExcInfoType type, EXC_INFO_SAVE_CALLBACK func, VOID *arg)
{
ExcInfoArray *excInfo = NULL;
if ((type == 0) || (type >= OS_EXC_TYPE_MAX) || (func == NULL)) {
PRINT_ERR("OsExcRegister ERROR!\n");
return;
}
excInfo = &(g_excArray[type - 1]);
excInfo->uwType = type;
excInfo->pFnExcInfoCb = func;
excInfo->pArg = arg;
excInfo->uwValid = TRUE;
}
static VOID OsExcSaveSysInfo(ExcInfoType type, EXC_INFO_SAVE_CALLBACK func, UINT32 loop, UINT32 length, UINT32 index)
{
UINT32 ret;
UINT32 buffer[OS_EXC_MAX_BUF_LEN];
*((UINT32 *)g_excContent) = type;
g_excContent = (UINT8 *)g_excContent + sizeof(UINT32);
*((UINT32 *)g_excContent) = length * (loop - index);
g_excContent = (UINT8 *)g_excContent + sizeof(UINT32);
for (; index < loop; index++) {
(VOID)memset_s(buffer, sizeof(UINT32) * OS_EXC_MAX_BUF_LEN, 0, sizeof(UINT32) * OS_EXC_MAX_BUF_LEN);
ret = func(index, (VOID *)buffer);
if (ret == LOS_OK) {
if (memcpy_s(g_excContent, MAX_EXC_MEM_SIZE, (VOID *)buffer, length) != EOK) {
PRINT_ERR("OsExcSaveSysInfo copy buffer failed\n");
return;
}
g_excContent = (UINT8 *)g_excContent + length;
} else {
g_excContent = (UINT8 *)g_excContent + length;
}
}
}
static VOID OsExcSaveInfo(ExcInfoType type, EXC_INFO_SAVE_CALLBACK func, VOID *arg)
{
UINT32 length;
UINT32 index;
UINT32 loop;
UINT32 taskSwitchCount = 0;
TaskSwitchInfo *taskSwitchInfo = NULL;
if (arg == NULL) {
return;
}
switch (type) {
case OS_EXC_TYPE_TSK: /* save task info */
length = sizeof(TSK_INFO_S);
loop = *(UINT32 *)arg;
index = 0;
break;
case OS_EXC_TYPE_QUE: /* save queue info */
length = sizeof(QUEUE_INFO_S);
loop = *(UINT32 *)arg + 1;
index = 1;
break;
case OS_EXC_TYPE_NVIC:
(VOID)func(0, 0);
goto END;
case OS_EXC_TYPE_TSK_SWITCH: /* save task switch info */
// not necessary, just for macro int library
taskSwitchInfo = arg;
taskSwitchCount = taskSwitchInfo->cntInfo.maxCnt;
length = sizeof(UINT32) + sizeof(CHAR) * LOS_TASK_NAMELEN;
if (taskSwitchInfo->cntInfo.isFull) {
index = taskSwitchInfo->idx;
loop = index + taskSwitchCount;
} else {
index = 0;
loop = taskSwitchInfo->idx;
}
break;
case OS_EXC_TYPE_MEM: /* save mem info */
length = sizeof(MEM_INFO_S);
loop = *(UINT32 *)arg;
index = 0;
break;
default:
goto END;
}
OsExcSaveSysInfo(type, (EXC_INFO_SAVE_CALLBACK)func, loop, length, index);
END:
return;
}
static VOID OsExcSave2DDR(VOID)
{
UINT32 index = 0;
UINT32 ret;
UINT32 failCnt = 0;
ret = memset_s(g_aucTaskArray, MAX_EXC_MEM_SIZE, TASK_ARRAY_INIT_VALUE, g_excArraySize);
if (ret != EOK) {
PRINT_ERR("memset failed\n");
return;
}
/* define core type */
*((UINT32 *)g_excContent) = CORE_TYPE_CORTEX_M4; // 1 is cortex-M3, 2 is cortex-M4
g_excContent = (UINT8 *)g_excContent + sizeof(UINT32);
/* save exception info */
*((UINT32 *)g_excContent) = OS_EXC_TYPE_CONTEXT;
g_excContent = (UINT8 *)g_excContent + sizeof(UINT32);
*((UINT32 *)g_excContent) = sizeof(ExcInfo) - sizeof(UINT32) + sizeof(EXC_CONTEXT_S);
g_excContent = (UINT8 *)g_excContent + sizeof(UINT32);
ret = memcpy_s((VOID *)g_excContent, MAX_EXC_MEM_SIZE, (VOID *)&g_excInfo, sizeof(ExcInfo) - sizeof(UINT32));
g_excContent = (UINT8 *)g_excContent + sizeof(ExcInfo) - sizeof(UINT32);
failCnt += (ret == EOK) ? 0 : 1;
ret = memcpy_s((VOID *)g_excContent, MAX_EXC_MEM_SIZE, g_excInfo.context, sizeof(EXC_CONTEXT_S));
g_excContent = (UINT8 *)g_excContent + sizeof(EXC_CONTEXT_S);
failCnt += (ret == EOK) ? 0 : 1;
if (failCnt != 0) {
PRINT_ERR("OsExcSave2DDR copy exc info failed, cnt:%d\n", failCnt);
}
for (index = 0; index < (OS_EXC_TYPE_MAX - 1); index++) {
if (g_excArray[index].uwValid == FALSE) {
continue;
}
OsExcSaveInfo(g_excArray[index].uwType, g_excArray[index].pFnExcInfoCb, g_excArray[index].pArg);
}
*((UINT32 *)g_excContent) = OS_EXC_TYPE_MAX;
g_excContent = (UINT8 *)g_excContent + sizeof(UINT32);
return;
}
LITE_OS_SEC_TEXT_INIT VOID OsExcInit(UINT32 arraySize)
{
g_hwiForm[HARDFAULT_IRQN + OS_SYS_VECTOR_CNT] = OsExcHardFault;
g_hwiForm[NonMaskableInt_IRQn + OS_SYS_VECTOR_CNT] = OsExcNMI;
g_hwiForm[MemoryManagement_IRQn + OS_SYS_VECTOR_CNT] = OsExcMemFault;
g_hwiForm[BusFault_IRQn + OS_SYS_VECTOR_CNT] = OsExcBusFault;
g_hwiForm[UsageFault_IRQn + OS_SYS_VECTOR_CNT] = OsExcUsageFault;
g_hwiForm[SVCall_IRQn + OS_SYS_VECTOR_CNT] = OsExcSvcCall;
/* Enable USGFAULT, BUSFAULT, MEMFAULT */
*(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
/* Enable DIV 0 and unaligned exception */
*(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT;
g_excArraySize = arraySize;
OsExcRegister(OS_EXC_TYPE_NVIC, (EXC_INFO_SAVE_CALLBACK)OsExcSaveIntStatus, NULL);
}
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */

265
kernel/arch/arm/cortex-m4/iar/los_exc.h
View File

@@ -1,265 +0,0 @@
/*
* Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_EXC_H
#define _LOS_EXC_H
#include "los_sys.h"
#include "los_config.h"
#include "los_base.h"
#include "los_task_pri.h"
#include "los_queue.h"
#include "los_memcheck.h"
#include "los_sys_pri.h"
#ifdef LOSCFG_LIB_LIBC
#include "string.h"
#endif
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cpluscplus */
#endif /* __cpluscplus */
#define OS_EXC_IN_INIT 0
#define OS_EXC_IN_TASK 1
#define OS_EXC_IN_HWI 2
#define OS_EXC_MAX_BUF_LEN 25
#define OS_EXC_MAX_NEST_DEPTH 1
#define OS_NVIC_SHCSR 0xE000ED24
#define OS_NVIC_CCR 0xE000ED14
#define OS_NVIC_INT_ENABLE_SIZE 0x20
#define OS_NVIC_INT_PRI_SIZE 0xF0
#define OS_NVIC_EXCPRI_SIZE 0xC
#define OS_NVIC_INT_PEND_SIZE OS_NVIC_INT_ACT_SIZE
#define OS_NVIC_INT_ACT_SIZE OS_NVIC_INT_ENABLE_SIZE
#define OS_EXC_FLAG_NO_FLOAT 0x10000000
#define OS_EXC_FLAG_FAULTADDR_VALID 0x01
#define OS_EXC_FLAG_IN_HWI 0x02
#define OS_EXC_IMPRECISE_ACCESS_ADDR 0xABABABAB
/**
*@ingroup los_exc
* the struct of register files
*
* description: the register files that saved when exception triggered
*
* notes:the following register with prefix 'uw' correspond to the registers in the cpu data sheet.
*/
typedef struct tagExcContext {
//handler save
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
UINT32 S16;
UINT32 S17;
UINT32 S18;
UINT32 S19;
UINT32 S20;
UINT32 S21;
UINT32 S22;
UINT32 S23;
UINT32 S24;
UINT32 S25;
UINT32 S26;
UINT32 S27;
UINT32 S28;
UINT32 S29;
UINT32 S30;
UINT32 S31;
#endif
UINT32 uwR4;
UINT32 uwR5;
UINT32 uwR6;
UINT32 uwR7;
UINT32 uwR8;
UINT32 uwR9;
UINT32 uwR10;
UINT32 uwR11;
UINT32 uwPriMask;
//auto save
UINT32 uwSP;
UINT32 uwR0;
UINT32 uwR1;
UINT32 uwR2;
UINT32 uwR3;
UINT32 uwR12;
UINT32 uwLR;
UINT32 uwPC;
UINT32 uwxPSR;
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED) && (__FPU_USED== 1U)))
UINT32 S0;
UINT32 S1;
UINT32 S2;
UINT32 S3;
UINT32 S4;
UINT32 S5;
UINT32 S6;
UINT32 S7;
UINT32 S8;
UINT32 S9;
UINT32 S10;
UINT32 S11;
UINT32 S12;
UINT32 S13;
UINT32 S14;
UINT32 S15;
UINT32 FPSCR;
UINT32 NO_NAME;
#endif
}EXC_CONTEXT_S;
typedef UINT32 (*EXC_INFO_SAVE_CALLBACK)(UINT32, VOID*);
typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *);
VOID OsExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr);
/**
* @ingroup los_hwi
* @brief: Exception initialization.
*
* @par Description:
* This API is used to configure the exception function vector table.
*
* @attention:
* <ul><li>None.</li></ul>
*
*@param uwArraySize [IN] Memory size of exception.
*
* @retval: None
* @par Dependency:
* <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
VOID OsExcInit(UINT32 uwArraySize);
extern VOID OsExcNMI(VOID);
extern VOID OsExcHardFault(VOID);
extern VOID OsExcMemFault(VOID);
extern VOID OsExcBusFault(VOID);
extern VOID OsExcUsageFault(VOID);
extern VOID OsExcSvcCall(VOID);
extern UINT8 g_aucTaskArray[];
inline void OsBackTrace(){}
/**
*@ingroup los_exc
*@brief Kernel panic function.
*
*@par Description:
*Stack function that prints kernel panics.
*@attention After this function is called and stack information is printed, the system will fail to respond.
*@attention The input parameter can be NULL.
*@param fmt [IN] Type #char* : variadic argument.
*
*@retval #None.
*
*@par Dependency:
*los_exc.h: the header file that contains the API declaration.
*@see None.
*/
VOID LOS_Panic(const CHAR *fmt, ...);
#define OS_EXC_BF_STKERR 1
#define OS_EXC_BF_UNSTKERR 2
#define OS_EXC_BF_IMPRECISERR 3
#define OS_EXC_BF_PRECISERR 4
#define OS_EXC_BF_IBUSERR 5
#define OS_EXC_MF_MSTKERR 6
#define OS_EXC_MF_MUNSTKERR 7
#define OS_EXC_MF_DACCVIOL 8
#define OS_EXC_MF_IACCVIOL 9
#define OS_EXC_UF_DIVBYZERO 10
#define OS_EXC_UF_UNALIGNED 11
#define OS_EXC_UF_NOCP 12
#define OS_EXC_UF_INVPC 13
#define OS_EXC_UF_INVSTATE 14
#define OS_EXC_UF_UNDEFINSTR 15
#define OS_EXC_CAUSE_NMI 16
#define OS_EXC_CAUSE_HARDFAULT 17
#define OS_EXC_CAUSE_TASK_EXIT 18
#define OS_EXC_CAUSE_FATAL_ERR 19
#define OS_EXC_CAUSE_DEBUGEVT 20
#define OS_EXC_CAUSE_VECTBL 21
typedef struct tagExcInfo {
UINT16 phase;
UINT16 type;
UINT32 faultAddr;
UINT32 thrdPid;
UINT16 nestCnt;
UINT16 reserved;
EXC_CONTEXT_S * context;
} ExcInfo;
extern UINT32 g_curNestCount;
extern UINT32 g_vuwIntCount;
static VOID OsExcSave2DDR(VOID);
VOID OsExcInfoDisplay(ExcInfo *exc);
extern TaskSwitchInfo g_taskSwitchInfo;
extern UINT8 g_uwExcTbl[32];
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cpluscplus */
#endif /* __cpluscplus */
#endif /* _LOS_EXC_H */

98
kernel/arch/arm/cortex-m4/iar/los_exc_pri.h
View File

@@ -1,98 +0,0 @@
/*
* Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_EXC_PRI_H
#define _LOS_EXC_PRI_H
#include "los_exc.h"
#include "los_sys_pri.h"
#ifdef LOSCFG_LIB_LIBC
#include "string.h"
#endif
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
typedef enum {
OS_EXC_TYPE_CONTEXT = 0,
OS_EXC_TYPE_TSK = 1,
OS_EXC_TYPE_QUE = 2,
OS_EXC_TYPE_NVIC = 3,
OS_EXC_TYPE_TSK_SWITCH = 4,
OS_EXC_TYPE_MEM = 5,
OS_EXC_TYPE_MAX = 6
} ExcInfoType;
typedef struct tagExcInfoCallBackArray {
ExcInfoType uwType;
UINT32 uwValid;
EXC_INFO_SAVE_CALLBACK pFnExcInfoCb;
VOID* pArg;
} ExcInfoArray;
#define MAX_SCENE_INFO_SIZE (8 + sizeof(ExcInfo) - 4 + sizeof(EXC_CONTEXT_S))
#define MAX_TSK_INFO_SIZE (8 + sizeof(TSK_INFO_S) * (LOSCFG_BASE_CORE_TSK_LIMIT + 1))
#define MAX_INT_INFO_SIZE (8 + 0x164)
#if (LOSCFG_BASE_IPC_QUEUE == YES)
#define MAX_QUEUE_INFO_SIZE (8 + sizeof(QUEUE_INFO_S) * LOSCFG_BASE_IPC_QUEUE_LIMIT)
#else
#define MAX_QUEUE_INFO_SIZE (0)
#endif
#if (LOSCFG_BASE_CORE_EXC_TSK_SWITCH == YES)
#define MAX_SWITCH_INFO_SIZE (8 + (sizeof(UINT32) + sizeof(CHAR) * LOS_TASK_NAMELEN) * OS_TASK_SWITCH_INFO_COUNT)
#else
#define MAX_SWITCH_INFO_SIZE (0)
#endif
#if (LOSCFG_BASE_MEM_NODE_INTEGRITY_CHECK == YES)
#define MAX_MEM_INFO_SIZE (8 + sizeof(MEM_INFO_S) * OS_SYS_MEM_NUM)
#else
#define MAX_MEM_INFO_SIZE (0)
#endif
#define MAX_EXC_MEM_SIZE ( 4 + MAX_SCENE_INFO_SIZE + MAX_TSK_INFO_SIZE + MAX_QUEUE_INFO_SIZE + MAX_INT_INFO_SIZE + MAX_SWITCH_INFO_SIZE + MAX_MEM_INFO_SIZE + 4)
VOID OsExcRegister(ExcInfoType type, EXC_INFO_SAVE_CALLBACK func, VOID *arg);
VOID LOS_Reboot(VOID);
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif

4
kernel/arch/arm/cortex-m4/iar/los_hw.c
View File

@@ -29,10 +29,8 @@
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_task_pri.h"
#include "los_hw.h"
#include "los_task.h"
#include "securec.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {

0
kernel/arch/arm/cortex-m4/iar/los_hw_exc_iar.S → kernel/arch/arm/cortex-m4/iar/los_hw_exc.S
View File

13
kernel/arch/arm/cortex-m4/iar/los_hw_tick.c
View File

@@ -29,12 +29,8 @@
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_tick_pri.h"
#include "los_base.h"
#include "los_task_pri.h"
#include "los_swtmr.h"
#include "los_hwi.h"
#include "los_tick.h"
#include "los_interrupt.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
@@ -245,11 +241,11 @@ VOID LOS_EnterSleep(LOS_SysSleepEnum sleep)
VOID LOS_SystemWakeup(UINT32 hwiIndex)
{
}
extern unsigned int SystemCoreClock;
//extern unsigned int SystemCoreClock;
void LOS_HalDelay(UINT32 ticks)
{
UINT32 delayTimes;
#if 0
/* there are 4 machine cycle in loop */
if ((ticks * (SystemCoreClock / MACHINE_CYCLE_DEALAY_TIMES)) >= 0xffffffff) {
delayTimes = 0xffffffff;
@@ -260,6 +256,7 @@ void LOS_HalDelay(UINT32 ticks)
while (delayTimes) {
delayTimes = delayTimes - 1;
}
#endif
}
#ifdef __cplusplus

263
kernel/arch/arm/cortex-m4/iar/los_hwi.c → kernel/arch/arm/cortex-m4/iar/los_interrupt.c
View File

@@ -28,15 +28,14 @@
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_hwi.h"
#include "los_sr.h"
#include "los_printf.h"
#include "los_interrupt.h"
#include <stdarg.h>
#include "los_debug.h"
#include "los_task.h"
#if (LOSCFG_KERNEL_TICKLESS == YES)
#include "los_tickless_pri.h"
#include "los_tick.h"
#endif
#ifdef __cplusplus
#if __cplusplus
extern "C" {
@@ -48,7 +47,6 @@ __weak VOID SysTickHandler(VOID)
{
return;
}
UINT32 g_vuwIntCount = 0;
/*lint -restore*/
#ifdef __ICCARM__
@@ -56,7 +54,6 @@ UINT32 g_vuwIntCount = 0;
#elif defined(__CC_ARM) || defined(__GNUC__)
LITE_OS_SEC_VEC
#endif
HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT] = {
(HWI_PROC_FUNC)0, // [0] Top of Stack
(HWI_PROC_FUNC)Reset_Handler, // [1] reset
@@ -75,6 +72,9 @@ HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT] = {
(HWI_PROC_FUNC)osPendSV, // [14] PendSV Handler
(HWI_PROC_FUNC)SysTickHandler, // [15] SysTick Handler
};
#if (OS_HWI_WITH_ARG == YES)
HWI_SLAVE_FUNC g_hwiSlaveForm[OS_VECTOR_CNT] = {{ (HWI_PROC_FUNC)0, (HWI_ARG_T)0 }};
#else
@@ -149,29 +149,6 @@ LITE_OS_SEC_TEXT VOID OsInterrupt(VOID)
LOS_IntRestore(intSave);
}
/* ****************************************************************************
Function : OsHwiInit
Description : initialization of the hardware interrupt
Input : None
Output : None
Return : None
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT VOID OsHwiInit()
{
UINT32 index;
for (index = OS_SYS_VECTOR_CNT; index < OS_VECTOR_CNT; index++) {
g_hwiForm[index] = (HWI_PROC_FUNC)OsHwiDefaultHandler;
}
/* Interrupt vector table location */
SCB->VTOR = (UINT32)(UINTPTR)g_hwiForm;
#if (__CORTEX_M >= 0x03U) /* only for Cortex-M3 and above */
NVIC_SetPriorityGrouping(OS_NVIC_AIRCR_PRIGROUP);
#endif
return;
}
/* ****************************************************************************
Function : LOS_HwiCreate
Description : create hardware interrupt
@@ -247,10 +224,228 @@ LITE_OS_SEC_TEXT_INIT UINT32 LOS_HwiDelete(HWI_HANDLE_T hwiNum)
return LOS_OK;
}
#define OS_NVIC_INT_CTRL_SIZE 4
#define OS_NVIC_SHCSR_SIZE 4
#define FAULT_STATUS_REG_BIT 32
#define USGFAULT (1 << 18)
#define BUSFAULT (1 << 17)
#define MEMFAULT (1 << 16)
#define DIV0FAULT (1 << 4)
#define HARDFAULT_IRQN (-13)
static ExcInfoArray g_excArray[OS_EXC_TYPE_MAX];
UINT32 g_curNestCount = 0;
static ExcInfo g_excInfo;
static EVENT_CB_S g_excEvent;
UINT8 g_uwExcTbl[FAULT_STATUS_REG_BIT] = {
0, 0, 0, 0, 0, 0, OS_EXC_UF_DIVBYZERO, OS_EXC_UF_UNALIGNED,
0, 0, 0, 0, OS_EXC_UF_NOCP, OS_EXC_UF_INVPC, OS_EXC_UF_INVSTATE, OS_EXC_UF_UNDEFINSTR,
0, 0, 0, OS_EXC_BF_STKERR, OS_EXC_BF_UNSTKERR, OS_EXC_BF_IMPRECISERR, OS_EXC_BF_PRECISERR, OS_EXC_BF_IBUSERR,
0, 0, 0, OS_EXC_MF_MSTKERR, OS_EXC_MF_MUNSTKERR, 0, OS_EXC_MF_DACCVIOL, OS_EXC_MF_IACCVIOL
};
__attribute__((noinline)) VOID LOS_Panic(const CHAR *fmt, ...)
{
va_list ap;
va_start(ap,fmt);
PRINT_ERR(fmt, ap);
va_end(ap);
asm volatile ("swi 0");
}
UINT32 OsExcNvicDump(UINT32 index, UINT32 *excContent)
{
UINT32 *base = NULL;
UINT32 len = 0,i,j;
#define OS_NR_NVIC_EXC_DUMP_Types 7
UINT32 rgNvicBases[OS_NR_NVIC_EXC_DUMP_Types] = {OS_NVIC_SETENA_BASE, OS_NVIC_SETPEND_BASE,
OS_NVIC_INT_ACT_BASE, OS_NVIC_PRI_BASE, OS_NVIC_EXCPRI_BASE, OS_NVIC_SHCSR, OS_NVIC_INT_CTRL};
UINT32 rgNvicLens[OS_NR_NVIC_EXC_DUMP_Types] = {OS_NVIC_INT_ENABLE_SIZE, OS_NVIC_INT_PEND_SIZE,
OS_NVIC_INT_ACT_SIZE, OS_NVIC_INT_PRI_SIZE, OS_NVIC_EXCPRI_SIZE, OS_NVIC_SHCSR_SIZE, OS_NVIC_INT_CTRL_SIZE};
char strRgEnable[] = "enable";
char strRgPending[] = "pending";
char strRgActive[] = "active";
char strRgPriority[] = "priority";
char strRgException[] = "exception";
char strRgShcsr[] = "shcsr";
char strRgIntCtrl[] = "control";
char *strRgs[] = {strRgEnable, strRgPending, strRgActive, strRgPriority, strRgException, strRgShcsr, strRgIntCtrl};
(VOID)index;
(VOID)excContent;
PRINTK("OS exception NVIC dump: \n");
for (i = 0; i < OS_NR_NVIC_EXC_DUMP_Types; i++) {
base = (UINT32 *)rgNvicBases[i];
len = rgNvicLens[i];
PRINTK("interrupt %s register, base address: 0x%x, size: 0x%x\n", strRgs[i], base, len);
len = (len >> 2);
for (j = 0; j < len; j++) {
PRINTK("0x%x ", *(base + j));
}
PRINTK("\n");
}
}
UINT32 OsExcContextDump(UINT32 index, UINT32 *excContent)
{
(VOID)index;
(VOID)excContent;
PRINTK("OS exception context dump:\n");
PRINTK("Phase = 0x%x\n", g_excInfo.phase);
PRINTK("Type = 0x%x\n", g_excInfo.type);
PRINTK("FaultAddr = 0x%x\n", g_excInfo.faultAddr);
PRINTK("ThrdPid = 0x%x\n", g_excInfo.thrdPid);
PRINTK("R0 = 0x%x\n", g_excInfo.context->uwR0);
PRINTK("R1 = 0x%x\n", g_excInfo.context->uwR1);
PRINTK("R2 = 0x%x\n", g_excInfo.context->uwR2);
PRINTK("R3 = 0x%x\n", g_excInfo.context->uwR3);
PRINTK("R4 = 0x%x\n", g_excInfo.context->uwR4);
PRINTK("R5 = 0x%x\n", g_excInfo.context->uwR5);
PRINTK("R6 = 0x%x\n", g_excInfo.context->uwR6);
PRINTK("R7 = 0x%x\n", g_excInfo.context->uwR7);
PRINTK("R8 = 0x%x\n", g_excInfo.context->uwR8);
PRINTK("R9 = 0x%x\n", g_excInfo.context->uwR9);
PRINTK("R10 = 0x%x\n", g_excInfo.context->uwR10);
PRINTK("R11 = 0x%x\n", g_excInfo.context->uwR11);
PRINTK("R12 = 0x%x\n", g_excInfo.context->uwR12);
PRINTK("PriMask = 0x%x\n", g_excInfo.context->uwPriMask);
PRINTK("SP = 0x%x\n", g_excInfo.context->uwSP);
PRINTK("LR = 0x%x\n", g_excInfo.context->uwLR);
PRINTK("PC = 0x%x\n", g_excInfo.context->uwPC);
PRINTK("xPSR = 0x%x\n", g_excInfo.context->uwxPSR);
}
VOID OsDumpMsg(VOID)
{
UINT32 index = 0;
for (index = 0; index < (OS_EXC_TYPE_MAX - 1); index++) {
if (g_excArray[index].uwValid == FALSE) {
continue;
}
g_excArray[index].pFnExcInfoCb(index, g_excArray[index].pArg);
}
}
VOID OsExcNotify(VOID)
{
UINT32 ret = LOS_EventWrite(&g_excEvent, OS_EXC_EVENT);
if (ret != LOS_OK) {
PRINT_ERR("event notify failed\n");
}
}
LITE_OS_SEC_TEXT_INIT VOID OsExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid,
EXC_CONTEXT_S *excBufAddr)
{
UINT16 tmpFlag = (excType >> 16) & OS_NULL_SHORT;
g_curNestCount++;
g_vuwIntCount++;
g_excInfo.nestCnt = g_curNestCount;
g_excInfo.type = excType & OS_NULL_SHORT;
if (tmpFlag & OS_EXC_FLAG_FAULTADDR_VALID) {
g_excInfo.faultAddr = faultAddr;
} else {
g_excInfo.faultAddr = OS_EXC_IMPRECISE_ACCESS_ADDR;
}
if (g_losTask.runTask != NULL) {
if (tmpFlag & OS_EXC_FLAG_IN_HWI) {
g_excInfo.phase = OS_EXC_IN_HWI;
g_excInfo.thrdPid = pid;
} else {
g_excInfo.phase = OS_EXC_IN_TASK;
g_excInfo.thrdPid = g_losTask.runTask->taskID;
}
} else {
g_excInfo.phase = OS_EXC_IN_INIT;
g_excInfo.thrdPid = OS_NULL_INT;
}
if (excType & OS_EXC_FLAG_NO_FLOAT) {
g_excInfo.context = (EXC_CONTEXT_S *)((CHAR *)excBufAddr - LOS_OFF_SET_OF(EXC_CONTEXT_S, uwR4));
} else {
g_excInfo.context = excBufAddr;
}
OsDumpMsg();
OsExcNotify();
LOS_Reboot();
}
VOID OsExcRegister(ExcInfoType type, EXC_INFO_SAVE_CALLBACK func, VOID *arg)
{
ExcInfoArray *excInfo = NULL;
if ((type >= OS_EXC_TYPE_MAX) || (func == NULL)) {
PRINT_ERR("OsExcRegister ERROR!\n");
return;
}
excInfo = &(g_excArray[type]);
excInfo->uwType = type;
excInfo->pFnExcInfoCb = func;
excInfo->pArg = arg;
excInfo->uwValid = TRUE;
}
void OsBackTrace()
{
}
/* ****************************************************************************
Function : OsHwiInit
Description : initialization of the hardware interrupt
Input : None
Output : None
Return : None
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT VOID OsHwiInit()
{
UINT32 index;
UINT32 ret;
for (index = OS_SYS_VECTOR_CNT; index < OS_VECTOR_CNT; index++) {
g_hwiForm[index] = (HWI_PROC_FUNC)OsHwiDefaultHandler;
}
/* Exception handler register */
g_hwiForm[HARDFAULT_IRQN + OS_SYS_VECTOR_CNT] = OsExcHardFault;
g_hwiForm[NonMaskableInt_IRQn + OS_SYS_VECTOR_CNT] = OsExcNMI;
g_hwiForm[MemoryManagement_IRQn + OS_SYS_VECTOR_CNT] = OsExcMemFault;
g_hwiForm[BusFault_IRQn + OS_SYS_VECTOR_CNT] = OsExcBusFault;
g_hwiForm[UsageFault_IRQn + OS_SYS_VECTOR_CNT] = OsExcUsageFault;
g_hwiForm[SVCall_IRQn + OS_SYS_VECTOR_CNT] = OsExcSvcCall;
/* Interrupt vector table location */
SCB->VTOR = (UINT32)(UINTPTR)g_hwiForm;
#if (__CORTEX_M >= 0x03U) /* only for Cortex-M3 and above */
NVIC_SetPriorityGrouping(OS_NVIC_AIRCR_PRIGROUP);
#endif
/* Enable USGFAULT, BUSFAULT, MEMFAULT */
*(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
/* Enable DIV 0 and unaligned exception */
*(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT;
/* Init Exception Event */
ret = LOS_EventInit(&g_excEvent);
if (ret != LOS_OK) {
PRINT_ERR("[EXC]init excepiton event failed!\n");
return;
}
OsExcRegister(OS_EXC_TYPE_CONTEXT, (EXC_INFO_SAVE_CALLBACK)OsExcContextDump, NULL);
OsExcRegister(OS_EXC_TYPE_NVIC, (EXC_INFO_SAVE_CALLBACK)OsExcNvicDump, NULL);
return;
}
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */

1085
kernel/arch/arm/cortex-m4/iar/los_interrupt.h Executable file
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File diff suppressed because it is too large Load Diff

0
kernel/arch/risc-v/rvm32/include/asm/soc_common.h → kernel/arch/risc-v/asm/soc_common.h Normal file → Executable file
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60
kernel/arch/risc-v/include/los_exc.h
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@@ -1,60 +0,0 @@
/*
* Copyright (c) 2013-2020, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_EXC_H
#define _LOS_EXC_H
#include "los_hw.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* __cplusplus */
extern VOID LOS_Panic(const CHAR *fmt, ...);
extern VOID OsBackTrace(VOID);
extern VOID OsTaskBackTrace(UINT32 taskID);
STATIC INLINE UINTPTR GetFp(VOID)
{
UINTPTR fpSave = 0;
__asm__ __volatile__("mv %0, s0" : "=r"(fpSave));
return fpSave;
}
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif

123
kernel/arch/risc-v/include/los_hw.h
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@@ -1,123 +0,0 @@
/*
* Copyright (c) 2013-2020, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_HW_H
#define _LOS_HW_H
#include "los_typedef.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
/**
* @ingroup los_hw
* The initialization value of stack space.
*/
#define EMPTY_STACK 0xCACA
/**
* @ingroup los_hw
* Check task schedule.
*/
#define LOS_CHECK_SCHEDULE ((!g_losTaskLock) && (!OS_INT_ACTIVE))
/**
* @ingroup los_hw
* @brief Wait for interrupt.
*
* @par Description:
* <ul>
* <li>This API is used to suspend execution until interrupt or a debug request occurs.</li>
* </ul>
* @attention None.
*
* @param None.
*
* @retval: None.
*
* @par Dependency:
* los_hw.h: the header file that contains the API declaration.
* @see None.
* @since Huawei LiteOS V200R002C00
*/
extern VOID wfi(VOID);
/**
* @ingroup los_hw
* @brief: mem fence function.
*
* @par Description:
* This API is used to fence for memory.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param: None.
*
* @retval:None.
* @par Dependency:
* <ul><li>los_hw.h: the header file that contains the API declaration.</li></ul>
* @see None.
* @since Huawei LiteOS V200R002C00
*/
extern VOID mb(VOID);
/**
* @ingroup los_hw
* @brief: mem fence function.
*
* @par Description:
* This API is same as mb, it just for adaptation.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param: None.
*
* @retval:None.
* @par Dependency:
* <ul><li>los_hw.h: the header file that contains the API declaration.</li></ul>
* @see None.
* @since Huawei LiteOS V200R002C00
*/
extern VOID dsb(VOID);
extern VOID LOS_GetCpuCycle(UINT32 *cntHi, UINT32 *cntLo);
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_HW_H */

83
kernel/arch/risc-v/rvm32/include/los_hw_pri.h → kernel/arch/risc-v/los_context.h Normal file → Executable file
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@@ -29,10 +29,10 @@
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_HW_PRI_H
#define _LOS_HW_PRI_H
#ifndef _LOS_HW_H
#define _LOS_HW_H
#include "los_hw.h"
#include "los_compiler.h"
#ifdef __cplusplus
#if __cplusplus
@@ -40,6 +40,18 @@ extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
/**
* @ingroup los_hw
* The initialization value of stack space.
*/
#define EMPTY_STACK 0xCACA
/**
* @ingroup los_hw
* Check task schedule.
*/
#define LOS_CHECK_SCHEDULE ((!g_losTaskLock) && (!OS_INT_ACTIVE))
#define TP_INIT_VALUE 0x02020202L
#define SP_INIT_VALUE 0x03030303L
#define S11_INIT_VALUE 0x04040404L
@@ -117,8 +129,67 @@ STATIC INLINE UINTPTR GetSP(VOID)
extern VOID *OsTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack);
extern VOID OsTaskScheduleCheck(VOID);
extern VOID OsDisableIRQ(VOID);
extern VOID OsEnableIRQ(VOID);
/**
* @ingroup los_hw
* @brief Wait for interrupt.
*
* @par Description:
* <ul>
* <li>This API is used to suspend execution until interrupt or a debug request occurs.</li>
* </ul>
* @attention None.
*
* @param None.
*
* @retval: None.
*
* @par Dependency:
* los_hw.h: the header file that contains the API declaration.
* @see None.
* @since Huawei LiteOS V200R002C00
*/
extern VOID wfi(VOID);
/**
* @ingroup los_hw
* @brief: mem fence function.
*
* @par Description:
* This API is used to fence for memory.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param: None.
*
* @retval:None.
* @par Dependency:
* <ul><li>los_hw.h: the header file that contains the API declaration.</li></ul>
* @see None.
* @since Huawei LiteOS V200R002C00
*/
extern VOID mb(VOID);
/**
* @ingroup los_hw
* @brief: mem fence function.
*
* @par Description:
* This API is same as mb, it just for adaptation.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param: None.
*
* @retval:None.
* @par Dependency:
* <ul><li>los_hw.h: the header file that contains the API declaration.</li></ul>
* @see None.
* @since Huawei LiteOS V200R002C00
*/
extern VOID dsb(VOID);
#ifdef __cplusplus
#if __cplusplus
@@ -126,4 +197,4 @@ extern VOID OsEnableIRQ(VOID);
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_HW_PRI_H */
#endif /* _LOS_HW_H */

0
kernel/arch/risc-v/rvm32/src/los_dispatch.S → kernel/arch/risc-v/los_dispatch.S Normal file → Executable file
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170
kernel/arch/risc-v/rvm32/src/los_exc.c → kernel/arch/risc-v/los_exc.c Normal file → Executable file
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@@ -29,10 +29,11 @@
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_exc.h"
#include "los_exc_pri.h"
#include "los_task_pri.h"
#include "los_printf_pri.h"
#include <stdio.h>
#include <stdarg.h>
#include "los_interrupt.h"
#include "los_task.h"
#include "los_debug.h"
#include "riscv_hal.h"
#ifdef __cplusplus
@@ -41,8 +42,9 @@ extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
LosExcInfo g_excInfo;
static ExcInfoArray g_excArray[OS_EXC_TYPE_MAX];
LosExcInfo g_excInfo;
#define RISCV_EXC_TYPE_NUM 16
const CHAR g_excInformation[RISCV_EXC_TYPE_NUM][50] = {
{ "Instruction address misaligned!" },
@@ -69,6 +71,150 @@ const CHAR g_excInformation[RISCV_EXC_TYPE_NUM][50] = {
#define FP_ALIGN(value) (((UINT32)(value) & (UINT32)(LOSCFG_STACK_POINT_ALIGN_SIZE - 1)) == 0)
#define FP_CHECK(value) (OsBackTraceFpCheck(value) && ((UINT32)(value) != FP_INIT_VALUE) && FP_ALIGN(value))
LITE_OS_SEC_BSS UINT32 g_intCount = 0;
LITE_OS_SEC_BSS UINT32 g_hwiFormCnt[OS_HWI_MAX_NUM];
LITE_OS_SEC_DATA_INIT HWI_HANDLE_FORM_S g_hwiForm[OS_HWI_MAX_NUM] = {
{ .pfnHook = NULL, .uwParam = 0 }, // 0 User software interrupt handler
{ .pfnHook = NULL, .uwParam = 0 }, // 1 Supervisor software interrupt handler
{ .pfnHook = NULL, .uwParam = 0 }, // 2 Reserved
{ .pfnHook = OsHwiDefaultHandler, .uwParam = 0 }, // 3 Machine software interrupt handler
{ .pfnHook = NULL, .uwParam = 0 }, // 4 User timer interrupt handler
{ .pfnHook = NULL, .uwParam = 0 }, // 5 Supervisor timer interrupt handler
{ .pfnHook = NULL, .uwParam = 0 }, // 6 Reserved
{ .pfnHook = OsHwiDefaultHandler, .uwParam = 0 }, // 7 Machine timer interrupt handler
{ .pfnHook = NULL, .uwParam = 0 }, // 8 User external interrupt handler
{ .pfnHook = NULL, .uwParam = 0 }, // 9 Supervisor external interrupt handler
{ .pfnHook = NULL, .uwParam = 0 }, // 10 Reserved
{ .pfnHook = OsHwiDefaultHandler, .uwParam = 0 }, // 11 Machine external interrupt handler
{ .pfnHook = OsHwiDefaultHandler, .uwParam = 0 }, // 12 NMI handler
{ .pfnHook = NULL, .uwParam = 0 }, // 13 Reserved
{ .pfnHook = NULL, .uwParam = 0 }, // 14 Reserved
{ .pfnHook = NULL, .uwParam = 0 }, // 15 Reserved
{ .pfnHook = NULL, .uwParam = 0 }, // 16 Reserved
{ .pfnHook = NULL, .uwParam = 0 }, // 17 Reserved
{ .pfnHook = NULL, .uwParam = 0 }, // 18 Reserved
{ .pfnHook = NULL, .uwParam = 0 }, // 19 Reserved
{ .pfnHook = NULL, .uwParam = 0 }, // 20 Reserved
{ .pfnHook = NULL, .uwParam = 0 }, // 21 Reserved
{ .pfnHook = NULL, .uwParam = 0 }, // 22 Reserved
{ .pfnHook = NULL, .uwParam = 0 }, // 23 Reserved
{ .pfnHook = NULL, .uwParam = 0 }, // 24 Reserved
{ .pfnHook = NULL, .uwParam = 0 }, // 25 Reserved
};
LITE_OS_SEC_TEXT_INIT VOID OsHwiDefaultHandler(UINTPTR arg)
{
(VOID)arg;
PRINT_ERR("default handler\n");
while (1) {
}
}
LITE_OS_SEC_TEXT_INIT VOID OsHwiInit(VOID)
{
UINT32 index;
for (index = OS_RISCV_SYS_VECTOR_CNT; index < OS_HWI_MAX_NUM; index++) {
g_hwiForm[index].pfnHook = OsHwiDefaultHandler;
g_hwiForm[index].uwParam = 0;
}
}
typedef VOID (*HwiProcFunc)(UINTPTR);
LITE_OS_SEC_TEXT_INIT VOID OsHwiInterruptDone(HWI_HANDLE_T hwiNum)
{
g_intCount++;
HWI_HANDLE_FORM_S *hwiForm = &g_hwiForm[hwiNum];
HwiProcFunc func = (HwiProcFunc)(hwiForm->pfnHook);
func(hwiForm->uwParam);
++g_hwiFormCnt[hwiNum];
g_intCount--;
}
LITE_OS_SEC_TEXT UINT32 OsGetHwiFormCnt(HWI_HANDLE_T hwiNum)
{
if (hwiNum < OS_HWI_MAX_NUM) {
return g_hwiFormCnt[hwiNum];
}
return LOS_NOK;
}
LITE_OS_SEC_TEXT HWI_HANDLE_FORM_S *OsGetHwiForm(VOID)
{
return g_hwiForm;
}
/*****************************************************************************
Function : LOS_HwiCreate
Description : create hardware interrupt
Input : hwiNum --- hwi num to create
hwiPrio --- priority of the hwi
hwiMode --- hwi interrupt mode
hwiHandler --- hwi handler
irqParam --- param of the hwi handler
Output : None
Return : LOS_OK on success or error code on failure
*****************************************************************************/
LITE_OS_SEC_TEXT UINT32 LOS_HwiCreate(HWI_HANDLE_T hwiNum,
HWI_PRIOR_T hwiPrio,
HWI_MODE_T hwiMode,
HWI_PROC_FUNC hwiHandler,
HWI_IRQ_PARAM_S irqParam)
{
UINT32 intSave;
if (hwiHandler == NULL) {
return OS_ERRNO_HWI_PROC_FUNC_NULL;
}
if (hwiNum >= OS_HWI_MAX_NUM) {
return OS_ERRNO_HWI_NUM_INVALID;
}
if (g_hwiForm[hwiNum].pfnHook == NULL) {
return OS_ERRNO_HWI_NUM_INVALID;
} else if (g_hwiForm[hwiNum].pfnHook != OsHwiDefaultHandler) {
return OS_ERRNO_HWI_NUM_INVALID;
}
if ((hwiPrio < OS_HWI_PRIO_LOWEST) || (hwiPrio > OS_HWI_PRIO_HIGHEST)) {
return OS_ERRNO_HWI_PRIO_INVALID;
}
intSave = LOS_IntLock();
g_hwiForm[hwiNum].pfnHook = hwiHandler;
g_hwiForm[hwiNum].uwParam = irqParam;
if (hwiNum >= OS_RISCV_SYS_VECTOR_CNT) {
OsSetLocalInterPri(hwiNum, hwiPrio);
}
LOS_IntRestore(intSave);
return LOS_OK;
}
/*****************************************************************************
Function : LOS_HwiDelete
Description : Delete hardware interrupt
Input : hwiNum --- hwi num to delete
Return : LOS_OK on success or error code on failure
*****************************************************************************/
LITE_OS_SEC_TEXT UINT32 LOS_HwiDelete(HWI_HANDLE_T hwiNum, HWI_IRQ_PARAM_S irqParam)
{
UINT32 intSave;
if (hwiNum >= OS_HWI_MAX_NUM) {
return OS_ERRNO_HWI_NUM_INVALID;
}
intSave = LOS_IntLock();
g_hwiForm[hwiNum].pfnHook = OsHwiDefaultHandler;
g_hwiForm[hwiNum].uwParam = 0;
LOS_IntRestore(intSave);
return LOS_OK;
}
LITE_OS_SEC_TEXT VOID BackTraceSub(UINT32 fp)
{
UINT32 backFp = fp;
@@ -259,6 +405,20 @@ SYSTEM_DEATH:
}
}
VOID OsExcRegister(ExcInfoType type, EXC_INFO_SAVE_CALLBACK func, VOID *arg)
{
ExcInfoArray *excInfo = NULL;
if ((type >= OS_EXC_TYPE_MAX) || (func == NULL)) {
PRINT_ERR("OsExcRegister ERROR!\n");
return;
}
excInfo = &(g_excArray[type]);
excInfo->uwType = type;
excInfo->pFnExcInfoCb = func;
excInfo->pArg = arg;
excInfo->uwValid = TRUE;
}
/* stack protector */
UINT32 __stack_chk_guard = 0xd00a0dff;

7
kernel/arch/risc-v/rvm32/src/los_hw.c → kernel/arch/risc-v/los_hw.c Normal file → Executable file
View File

@@ -29,11 +29,10 @@
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_hw.h"
#include "los_hw_pri.h"
#include "los_task_pri.h"
#include "los_context.h"
#include "los_interrupt.h"
#include "los_task.h"
#include "los_memory.h"
#include "los_priqueue_pri.h"
#include "soc.h"
#ifdef __cplusplus

14
kernel/arch/risc-v/rvm32/src/los_hw_tick.c → kernel/arch/risc-v/los_hw_tick.c Normal file → Executable file
View File

@@ -29,9 +29,9 @@
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_hw_tick_pri.h"
#include "los_hwi.h"
#include "los_tick_pri.h"
#include "los_tick.h"
#include "los_config.h"
#include "los_interrupt.h"
#include "riscv_hal.h"
#ifdef __cplusplus
@@ -53,6 +53,14 @@ LITE_OS_SEC_TEXT_INIT UINT32 OsTickStart(VOID)
return LOS_OK;
}
/* ****************************************************************************
Function : LOS_GetCpuCycle
Description : Get System cycle count
Input : none
output : cntHi --- CpuTick High 4 byte
cntLo --- CpuTick Low 4 byte
return : none
**************************************************************************** */
LITE_OS_SEC_TEXT_MINOR VOID LOS_GetCpuCycle(UINT32 *cntHi, UINT32 *cntLo)
{
OsGetCpuCycle(cntHi, cntLo);

157
kernel/arch/risc-v/include/los_hwi.h → kernel/arch/risc-v/los_interrupt.h Normal file → Executable file
View File

@@ -31,8 +31,9 @@
#ifndef _LOS_HWI_H
#define _LOS_HWI_H
#include "securec.h"
#include "los_printf.h"
#include "los_compiler.h"
#include "los_config.h"
#include "los_context.h"
#ifdef __cplusplus
#if __cplusplus
@@ -97,6 +98,135 @@ typedef struct tagHwiHandleForm {
typedef UINTPTR HWI_IRQ_PARAM_S;
typedef struct {
UINT32 mcause;
UINT32 mtval;
UINT32 medeleg;
UINT32 gp;
TaskContext taskContext;
} LosExcContext;
typedef struct {
UINT16 nestCnt;
UINT16 type;
UINT32 thrID;
LosExcContext *context;
} LosExcInfo;
typedef enum {
OS_EXC_TYPE_CONTEXT = 0,
OS_EXC_TYPE_TSK = 1,
OS_EXC_TYPE_QUE = 2,
OS_EXC_TYPE_NVIC = 3,
OS_EXC_TYPE_TSK_SWITCH = 4,
OS_EXC_TYPE_MEM = 5,
OS_EXC_TYPE_MAX = 6
} ExcInfoType;
typedef UINT32 (*EXC_INFO_SAVE_CALLBACK)(UINT32, VOID*);
typedef struct {
ExcInfoType uwType;
UINT32 uwValid;
EXC_INFO_SAVE_CALLBACK pFnExcInfoCb;
VOID* pArg;
} ExcInfoArray;
#define MAX_EXC_MEM_SIZE 0
/**
* @ingroup los_hwi
* Highest priority of a hardware interrupt.
*/
#define OS_HWI_PRIO_HIGHEST 7
/**
* @ingroup los_hwi
* Lowest priority of a hardware interrupt.
*/
#define OS_HWI_PRIO_LOWEST 1
/**
* @ingroup los_hwi
* Count of HimiDeer system interrupt vector.
*/
#define OS_RISCV_SYS_VECTOR_CNT (RISCV_SYS_MAX_IRQ + 1)
/**
* @ingroup los_hwi
* Count of HimiDeer local interrupt vector 0 - 5, enabled by CSR mie 26 -31 bit.
*/
#define OS_RISCV_MIE_IRQ_VECTOR_CNT 6
/**
* @ingroup los_hwi
* Count of HimiDeer local interrupt vector 6 - 31, enabled by custom CSR locie0 0 - 25 bit.
*/
#define OS_RISCV_CUSTOM_IRQ_VECTOR_CNT RISCV_PLIC_VECTOR_CNT
/**
* @ingroup los_hwi
* Count of HimiDeer local IRQ interrupt vector.
*/
#define OS_RISCV_LOCAL_IRQ_VECTOR_CNT (OS_RISCV_MIE_IRQ_VECTOR_CNT + OS_RISCV_SYS_VECTOR_CNT)
/**
* @ingroup los_hwi
* Count of himideer interrupt vector.
*/
#define OS_RISCV_VECTOR_CNT (OS_RISCV_SYS_VECTOR_CNT + OS_RISCV_CUSTOM_IRQ_VECTOR_CNT)
/**
* Maximum number of supported hardware devices that generate hardware interrupts.
* The maximum number of hardware devices that generate hardware interrupts supported by hi3518ev200 is 32.
*/
#define OS_HWI_MAX_NUM OS_RISCV_VECTOR_CNT
/**
* Maximum interrupt number.
*/
#define OS_HWI_MAX ((OS_HWI_MAX_NUM) - 1)
/**
* Minimum interrupt number.
*/
#define OS_HWI_MIN 0
/**
* Maximum usable interrupt number.
*/
#define OS_USER_HWI_MAX OS_HWI_MAX
/**
* Minimum usable interrupt number.
*/
#define OS_USER_HWI_MIN OS_HWI_MIN
extern HWI_HANDLE_FORM_S g_hwiForm[OS_HWI_MAX_NUM];
extern VOID OsHwiInit(VOID);
extern UINT32 OsGetHwiFormCnt(HWI_HANDLE_T hwiNum);
extern HWI_HANDLE_FORM_S *OsGetHwiForm(VOID);
extern VOID OsHwiInterruptDone(HWI_HANDLE_T hwiNum);
extern VOID OsHwiDefaultHandler(UINTPTR arg);
extern VOID BackTraceSub(UINT32 fp);
extern VOID OsDisableIRQ(VOID);
extern VOID OsEnableIRQ(VOID);
extern VOID LOS_Panic(const CHAR *fmt, ...);
extern VOID OsBackTrace(VOID);
extern VOID OsTaskBackTrace(UINT32 taskID);
extern VOID OsExcInit(VOID);
extern VOID OsExcRegister(ExcInfoType type, EXC_INFO_SAVE_CALLBACK func, VOID *arg);
STATIC INLINE UINTPTR GetFp(VOID)
{
UINTPTR fpSave = 0;
__asm__ __volatile__("mv %0, s0" : "=r"(fpSave));
return fpSave;
}
extern UINT32 g_intCount;
/**
@@ -346,6 +476,29 @@ extern UINT32 LOS_IntLock(VOID);
*/
extern VOID LOS_IntRestore(UINT32 intSave);
/* *
* @ingroup los_hwi
* @brief Get value from xPSR register.
*
* @par Description:
* <ul>
* <li>This API is used to Get value from xPSR register.</li>
* </ul>
* @attention
* <ul>
* <li>None.</li>
* </ul>
*
* @param cntHi [IN] CpuTick High 4 byte
* @param cntLo [IN] CpuTick Low 4 byte
*
* @retval None.
* @par Dependency:
* <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
* @see LOS_IntRestore
*/
extern VOID LOS_GetCpuCycle(UINT32 *cntHi, UINT32 *cntLo);
/**
* @ingroup los_hwi
* @brief Delete hardware interrupt.

0
kernel/arch/risc-v/rvm32/src/los_trap.S → kernel/arch/risc-v/los_trap.S
View File

67
kernel/arch/risc-v/rvm32/include/los_exc_pri.h
View File

@@ -1,67 +0,0 @@
/*
* Copyright (c) 2013-2020, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_EXC_PRI_H
#define _LOS_EXC_PRI_H
#include "los_typedef.h"
#include "los_hw_pri.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
extern VOID BackTraceSub(UINT32 fp);
typedef struct {
UINT32 mcause;
UINT32 mtval;
UINT32 medeleg;
UINT32 gp;
TaskContext taskContext;
} LosExcContext;
typedef struct {
UINT16 nestCnt;
UINT16 type;
UINT32 thrID;
LosExcContext *context;
} LosExcInfo;
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_EXC_PRI_H */

53
kernel/arch/risc-v/rvm32/include/los_hw_tick_pri.h
View File

@@ -1,53 +0,0 @@
/*
* Copyright (c) 2013-2020, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_HW_TICK_PRI_H
#define _LOS_HW_TICK_PRI_H
#include "los_typedef.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
#define TICK_INTERRUPT_PRI 0x1
extern UINT32 g_cyclesPerTick;
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_HW_TICK_PRI_H */

135
kernel/arch/risc-v/rvm32/include/los_hwi_pri.h
View File

@@ -1,135 +0,0 @@
/*
* Copyright (c) 2013-2020, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_HWI_PRI_H
#define _LOS_HWI_PRI_H
#include "soc.h"
#include "los_hwi.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
/**
* @ingroup los_hwi
* The hwi form does not contain exceptions for cortex-A
*/
#define OS_HWI_FORM_EXC_NUM 0
#if OS_HWI_FORM_EXC_NUM != 0
#error "OS_HWI_FORM_EXC_NUM must be zero"
#endif
/**
* @ingroup los_hwi
* Highest priority of a hardware interrupt.
*/
#define OS_HWI_PRIO_HIGHEST 7
/**
* @ingroup los_hwi
* Lowest priority of a hardware interrupt.
*/
#define OS_HWI_PRIO_LOWEST 1
/**
* @ingroup los_hwi
* Count of HimiDeer system interrupt vector.
*/
#define OS_RISCV_SYS_VECTOR_CNT (RISCV_SYS_MAX_IRQ + 1)
/**
* @ingroup los_hwi
* Count of HimiDeer local interrupt vector 0 - 5, enabled by CSR mie 26 -31 bit.
*/
#define OS_RISCV_MIE_IRQ_VECTOR_CNT 6
/**
* @ingroup los_hwi
* Count of HimiDeer local interrupt vector 6 - 31, enabled by custom CSR locie0 0 - 25 bit.
*/
#define OS_RISCV_CUSTOM_IRQ_VECTOR_CNT RISCV_PLIC_VECTOR_CNT
/**
* @ingroup los_hwi
* Count of HimiDeer local IRQ interrupt vector.
*/
#define OS_RISCV_LOCAL_IRQ_VECTOR_CNT (OS_RISCV_MIE_IRQ_VECTOR_CNT + OS_RISCV_SYS_VECTOR_CNT)
/**
* @ingroup los_hwi
* Count of himideer interrupt vector.
*/
#define OS_RISCV_VECTOR_CNT (OS_RISCV_SYS_VECTOR_CNT + OS_RISCV_CUSTOM_IRQ_VECTOR_CNT)
/**
* Maximum number of supported hardware devices that generate hardware interrupts.
* The maximum number of hardware devices that generate hardware interrupts supported by hi3518ev200 is 32.
*/
#define OS_HWI_MAX_NUM OS_RISCV_VECTOR_CNT
/**
* Maximum interrupt number.
*/
#define OS_HWI_MAX ((OS_HWI_MAX_NUM) - 1)
/**
* Minimum interrupt number.
*/
#define OS_HWI_MIN 0
/**
* Maximum usable interrupt number.
*/
#define OS_USER_HWI_MAX OS_HWI_MAX
/**
* Minimum usable interrupt number.
*/
#define OS_USER_HWI_MIN OS_HWI_MIN
extern HWI_HANDLE_FORM_S g_hwiForm[OS_HWI_MAX_NUM];
extern VOID OsHwiInit(VOID);
extern UINT32 OsGetHwiFormCnt(HWI_HANDLE_T hwiNum);
extern HWI_HANDLE_FORM_S *OsGetHwiForm(VOID);
extern VOID OsHwiInterruptDone(HWI_HANDLE_T hwiNum);
extern VOID OsHwiDefaultHandler(UINTPTR arg);
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_HWI_PRI_H */

191
kernel/arch/risc-v/rvm32/src/los_hwi.c
View File

@@ -1,191 +0,0 @@
/*
* Copyright (c) 2013-2020, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_base.h"
#include "los_hwi_pri.h"
#include "riscv_hal.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
LITE_OS_SEC_BSS UINT32 g_intCount = 0;
LITE_OS_SEC_BSS UINT32 g_hwiFormCnt[OS_HWI_MAX_NUM];
LITE_OS_SEC_DATA_INIT HWI_HANDLE_FORM_S g_hwiForm[OS_HWI_MAX_NUM] = {
{ .pfnHook = NULL, .uwParam = 0 }, // 0 User software interrupt handler
{ .pfnHook = NULL, .uwParam = 0 }, // 1 Supervisor software interrupt handler
{ .pfnHook = NULL, .uwParam = 0 }, // 2 Reserved
{ .pfnHook = OsHwiDefaultHandler, .uwParam = 0 }, // 3 Machine software interrupt handler
{ .pfnHook = NULL, .uwParam = 0 }, // 4 User timer interrupt handler
{ .pfnHook = NULL, .uwParam = 0 }, // 5 Supervisor timer interrupt handler
{ .pfnHook = NULL, .uwParam = 0 }, // 6 Reserved
{ .pfnHook = OsHwiDefaultHandler, .uwParam = 0 }, // 7 Machine timer interrupt handler
{ .pfnHook = NULL, .uwParam = 0 }, // 8 User external interrupt handler
{ .pfnHook = NULL, .uwParam = 0 }, // 9 Supervisor external interrupt handler
{ .pfnHook = NULL, .uwParam = 0 }, // 10 Reserved
{ .pfnHook = OsHwiDefaultHandler, .uwParam = 0 }, // 11 Machine external interrupt handler
{ .pfnHook = OsHwiDefaultHandler, .uwParam = 0 }, // 12 NMI handler
{ .pfnHook = NULL, .uwParam = 0 }, // 13 Reserved
{ .pfnHook = NULL, .uwParam = 0 }, // 14 Reserved
{ .pfnHook = NULL, .uwParam = 0 }, // 15 Reserved
{ .pfnHook = NULL, .uwParam = 0 }, // 16 Reserved
{ .pfnHook = NULL, .uwParam = 0 }, // 17 Reserved
{ .pfnHook = NULL, .uwParam = 0 }, // 18 Reserved
{ .pfnHook = NULL, .uwParam = 0 }, // 19 Reserved
{ .pfnHook = NULL, .uwParam = 0 }, // 20 Reserved
{ .pfnHook = NULL, .uwParam = 0 }, // 21 Reserved
{ .pfnHook = NULL, .uwParam = 0 }, // 22 Reserved
{ .pfnHook = NULL, .uwParam = 0 }, // 23 Reserved
{ .pfnHook = NULL, .uwParam = 0 }, // 24 Reserved
{ .pfnHook = NULL, .uwParam = 0 }, // 25 Reserved
};
LITE_OS_SEC_TEXT_INIT VOID OsHwiDefaultHandler(UINTPTR arg)
{
(VOID)arg;
PRINT_ERR("default handler\n");
while (1) {
}
}
LITE_OS_SEC_TEXT_INIT VOID OsHwiInit(VOID)
{
UINT32 index;
for (index = OS_RISCV_SYS_VECTOR_CNT; index < OS_HWI_MAX_NUM; index++) {
g_hwiForm[index].pfnHook = OsHwiDefaultHandler;
g_hwiForm[index].uwParam = 0;
}
}
typedef VOID (*HwiProcFunc)(UINTPTR);
LITE_OS_SEC_TEXT_INIT VOID OsHwiInterruptDone(HWI_HANDLE_T hwiNum)
{
g_intCount++;
HWI_HANDLE_FORM_S *hwiForm = &g_hwiForm[hwiNum];
HwiProcFunc func = (HwiProcFunc)(hwiForm->pfnHook);
func(hwiForm->uwParam);
++g_hwiFormCnt[hwiNum];
g_intCount--;
}
LITE_OS_SEC_TEXT UINT32 OsGetHwiFormCnt(HWI_HANDLE_T hwiNum)
{
if (hwiNum < OS_HWI_MAX_NUM) {
return g_hwiFormCnt[hwiNum];
}
return LOS_NOK;
}
LITE_OS_SEC_TEXT HWI_HANDLE_FORM_S *OsGetHwiForm(VOID)
{
return g_hwiForm;
}
/*****************************************************************************
Function : LOS_HwiCreate
Description : create hardware interrupt
Input : hwiNum --- hwi num to create
hwiPrio --- priority of the hwi
hwiMode --- hwi interrupt mode
hwiHandler --- hwi handler
irqParam --- param of the hwi handler
Output : None
Return : LOS_OK on success or error code on failure
*****************************************************************************/
LITE_OS_SEC_TEXT UINT32 LOS_HwiCreate(HWI_HANDLE_T hwiNum,
HWI_PRIOR_T hwiPrio,
HWI_MODE_T hwiMode,
HWI_PROC_FUNC hwiHandler,
HWI_IRQ_PARAM_S irqParam)
{
UINT32 intSave;
if (hwiHandler == NULL) {
return OS_ERRNO_HWI_PROC_FUNC_NULL;
}
if (hwiNum >= OS_HWI_MAX_NUM) {
return OS_ERRNO_HWI_NUM_INVALID;
}
if (g_hwiForm[hwiNum].pfnHook == NULL) {
return OS_ERRNO_HWI_NUM_INVALID;
} else if (g_hwiForm[hwiNum].pfnHook != OsHwiDefaultHandler) {
return OS_ERRNO_HWI_NUM_INVALID;
}
if ((hwiPrio < OS_HWI_PRIO_LOWEST) || (hwiPrio > OS_HWI_PRIO_HIGHEST)) {
return OS_ERRNO_HWI_PRIO_INVALID;
}
intSave = LOS_IntLock();
g_hwiForm[hwiNum].pfnHook = hwiHandler;
g_hwiForm[hwiNum].uwParam = irqParam;
if (hwiNum >= OS_RISCV_SYS_VECTOR_CNT) {
OsSetLocalInterPri(hwiNum, hwiPrio);
}
LOS_IntRestore(intSave);
return LOS_OK;
}
/*****************************************************************************
Function : LOS_HwiDelete
Description : Delete hardware interrupt
Input : hwiNum --- hwi num to delete
Return : LOS_OK on success or error code on failure
*****************************************************************************/
LITE_OS_SEC_TEXT UINT32 LOS_HwiDelete(HWI_HANDLE_T hwiNum, HWI_IRQ_PARAM_S irqParam)
{
UINT32 intSave;
if (hwiNum >= OS_HWI_MAX_NUM) {
return OS_ERRNO_HWI_NUM_INVALID;
}
intSave = LOS_IntLock();
g_hwiForm[hwiNum].pfnHook = OsHwiDefaultHandler;
g_hwiForm[hwiNum].uwParam = 0;
LOS_IntRestore(intSave);
return LOS_OK;
}
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */