diff --git a/kernel/arch/arm/arm9/gcc/BUILD.gn b/kernel/arch/arm/arm9/gcc/BUILD.gn new file mode 100644 index 00000000..66f3d6b2 --- /dev/null +++ b/kernel/arch/arm/arm9/gcc/BUILD.gn @@ -0,0 +1,46 @@ +# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. +# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without modification, +# are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of +# conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list +# of conditions and the following disclaimer in the documentation and/or other materials +# provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific prior written +# permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +static_library("arch") { + sources = [ + "los_context.c", + "los_dispatch.S", + "los_exc.S", + "los_interrupt.c", + "los_timer.c", + "reset_vector.S", + ] + + include_dirs = [ + "../../../../../kernel/arch/include", + "../../../../../kernel/include", + "../../../../../utils", + "//third_party/bounds_checking_function/include", + ] +} diff --git a/kernel/arch/arm/arm9/gcc/los_arch_atomic.h b/kernel/arch/arm/arm9/gcc/los_arch_atomic.h new file mode 100644 index 00000000..19a6a1af --- /dev/null +++ b/kernel/arch/arm/arm9/gcc/los_arch_atomic.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. + * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _LOS_ARCH_ATOMIC_H +#define _LOS_ARCH_ATOMIC_H + +#include "los_compiler.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +/** + * @ingroup los_arch_atomic + * @brief Atomic exchange for 32-bit variable. + * + * @par Description: + * This API is used to implement the atomic exchange for 32-bit variable and return the previous value of the atomic variable. + * @attention + * + * + * @param v [IN] The variable pointer. + * @param val [IN] The exchange value. + * + * @retval #INT32 The previous value of the atomic variable + * @par Dependency: + * + * @see + */ +STATIC INLINE INT32 HalAtomicXchg32bits(volatile INT32 *v, INT32 val) +{ + return -1; +} + +/** + * @ingroup los_arch_atomic + * @brief Atomic auto-decrement. + * + * @par Description: + * This API is used to implement the atomic auto-decrement and return the result of auto-decrement. + * @attention + * + * + * @param v [IN] The addSelf variable pointer. + * + * @retval #INT32 The return value of variable auto-decrement. + * @par Dependency: + * + * @see + */ +STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v) +{ + return -1; +} + +/** + * @ingroup los_arch_atomic + * @brief Atomic exchange for 32-bit variable with compare. + * + * @par Description: + * This API is used to implement the atomic exchange for 32-bit variable, if the value of variable is equal to oldVal. + * @attention + * + * + * @param v [IN] The variable pointer. + * @param val [IN] The new value. + * @param oldVal [IN] The old value. + * + * @retval TRUE The previous value of the atomic variable is not equal to oldVal. + * @retval FALSE The previous value of the atomic variable is equal to oldVal. + * @par Dependency: + * + * @see + */ +STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal) +{ + return FALSE; +} + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#endif /* _LOS_ARCH_ATOMIC_H */ + diff --git a/kernel/arch/arm/arm9/gcc/los_arch_context.h b/kernel/arch/arm/arm9/gcc/los_arch_context.h new file mode 100644 index 00000000..7c60151b --- /dev/null +++ b/kernel/arch/arm/arm9/gcc/los_arch_context.h @@ -0,0 +1,180 @@ +/* + * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. + * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _LOS_ARCH_CONTEXT_H +#define _LOS_ARCH_CONTEXT_H + +#include "los_config.h" +#include "los_compiler.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#define PSR_T_ARM 0x00000000U +#define PSR_T_THUMB 0x00000020U +#define PSR_MODE_SVC 0x00000013U +#define PSR_MODE_SYS 0x0000001FU + +#define PSR_MODE_SVC_THUMB (PSR_MODE_SVC | PSR_T_THUMB) +#define PSR_MODE_SVC_ARM (PSR_MODE_SVC | PSR_T_ARM) + +#define PSR_MODE_SYS_THUMB (PSR_MODE_SYS | PSR_T_THUMB) +#define PSR_MODE_SYS_ARM (PSR_MODE_SYS | PSR_T_ARM) + +VOID OsTaskEntryArm(VOID); +VOID OsTaskEntryThumb(VOID); + +typedef struct TagTskContext { + UINT32 spsr; + UINT32 r0; + UINT32 r1; + UINT32 r2; + UINT32 r3; + UINT32 r4; + UINT32 r5; + UINT32 r6; + UINT32 r7; + UINT32 r8; + UINT32 r9; + UINT32 r10; + UINT32 r11; + UINT32 r12; + UINT32 lr; + UINT32 pc; +} TaskContext; + +/** + * @ingroup los_config + * @brief: Task start running function. + * + * @par Description: + * This API is used to start a task. + * + * @attention: + * + * + * @param: None. + * + * @retval None. + * + * @par Dependency: + * + * @see None. + */ +extern VOID HalStartToRun(VOID); + +/** + * @ingroup los_arch_context + * @brief Wait for interrupt. + * + * @par Description: + * + * @attention None. + * + * @param None. + * + * @retval: None. + * + * @par Dependency: + * los_arch_context.h: the header file that contains the API declaration. + * @see None. + */ +extern VOID wfi(VOID); + +/** + * @ingroup los_arch_context + * @brief: mem fence function. + * + * @par Description: + * This API is used to fence for memory. + * + * @attention: + * + * + * @param: None. + * + * @retval:None. + * @par Dependency: + * + * @see None. + */ +extern VOID dmb(VOID); + +/** + * @ingroup los_arch_context + * @brief: mem fence function. + * + * @par Description: + * This API is same as dmb, it just for adaptation. + * + * @attention: + * + * + * @param: None. + * + * @retval:None. + * @par Dependency: + * + * @see None. + */ +extern VOID dsb(VOID); + +/** + * @ingroup los_arch_context + * @brief: instruction fence function. + * + * @par Description: + * This API is used to fence for instruction. + * + * @attention: + * + * + * @param: None. + * + * @retval:None. + * @par Dependency: + * + * @see None. + */ +extern VOID isb(VOID); + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#endif /* _LOS_ARCH_CONTEXT_H */ diff --git a/kernel/arch/arm/arm9/gcc/los_arch_interrupt.h b/kernel/arch/arm/arm9/gcc/los_arch_interrupt.h new file mode 100644 index 00000000..83b68892 --- /dev/null +++ b/kernel/arch/arm/arm9/gcc/los_arch_interrupt.h @@ -0,0 +1,350 @@ +/* + * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. + * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _LOS_ARCH_INTERRUPT_H +#define _LOS_ARCH_INTERRUPT_H + +#include "los_config.h" +#include "los_compiler.h" +#include "los_interrupt.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +/* * + * @ingroup los_arch_interrupt + * Maximum number of used hardware interrupts. + */ +#ifndef OS_HWI_MAX_NUM +#define OS_HWI_MAX_NUM LOSCFG_PLATFORM_HWI_LIMIT +#endif + +/* * + * @ingroup los_arch_interrupt + * Highest priority of a hardware interrupt. + */ +#ifndef OS_HWI_PRIO_HIGHEST +#define OS_HWI_PRIO_HIGHEST 0 +#endif + +/* * + * @ingroup los_arch_interrupt + * Lowest priority of a hardware interrupt. + */ +#ifndef OS_HWI_PRIO_LOWEST +#define OS_HWI_PRIO_LOWEST 7 +#endif + + +/* * + * @ingroup los_arch_interrupt + * Define the type of a hardware interrupt vector table function. + */ +typedef VOID (**HWI_VECTOR_FUNC)(void); + +/* * + * @ingroup los_arch_interrupt + * Count of interrupts. + */ +extern UINT32 g_intCount; + +/* * + * @ingroup los_arch_interrupt + * Count of arm9 system interrupt vector. + */ +#define OS_SYS_VECTOR_CNT 0 + +/* * + * @ingroup los_arch_interrupt + * Count of arm9 interrupt vector. + */ +#define OS_VECTOR_CNT (OS_SYS_VECTOR_CNT + OS_HWI_MAX_NUM) + +/* * + * @ingroup los_arch_interrupt + * Hardware interrupt error code: Invalid interrupt number. + * + * Value: 0x02000900 + * + * Solution: Ensure that the interrupt number is valid. The value range of the interrupt number applicable for a Cortex-A7 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX]. + */ +#define OS_ERRNO_HWI_NUM_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00) + +/* * + * @ingroup los_arch_interrupt + * Hardware interrupt error code: Null hardware interrupt handling function. + * + * Value: 0x02000901 + * + * Solution: Pass in a valid non-null hardware interrupt handling function. + */ +#define OS_ERRNO_HWI_PROC_FUNC_NULL LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x01) + +/* * + * @ingroup los_arch_interrupt + * Hardware interrupt error code: Insufficient interrupt resources for hardware interrupt creation. + * + * Value: 0x02000902 + * + * Solution: Increase the configured maximum number of supported hardware interrupts. + */ +#define OS_ERRNO_HWI_CB_UNAVAILABLE LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x02) + +/* * + * @ingroup los_arch_interrupt + * Hardware interrupt error code: Insufficient memory for hardware interrupt initialization. + * + * Value: 0x02000903 + * + * Solution: Expand the configured memory. + */ +#define OS_ERRNO_HWI_NO_MEMORY LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x03) + +/* * + * @ingroup los_arch_interrupt + * Hardware interrupt error code: The interrupt has already been created. + * + * Value: 0x02000904 + * + * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created. + */ +#define OS_ERRNO_HWI_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x04) + +/* * + * @ingroup los_arch_interrupt + * Hardware interrupt error code: Invalid interrupt priority. + * + * Value: 0x02000905 + * + * Solution: Ensure that the interrupt priority is valid. The value range of the interrupt priority applicable for a Cortex-A7 platform is [0,15]. + */ +#define OS_ERRNO_HWI_PRIO_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05) + +/* * + * @ingroup los_arch_interrupt + * Hardware interrupt error code: Incorrect interrupt creation mode. + * + * Value: 0x02000906 + * + * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or OS_HWI_MODE_FAST of which the value can be 0 or 1. + */ +#define OS_ERRNO_HWI_MODE_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06) + +/* * + * @ingroup los_arch_interrupt + * Hardware interrupt error code: The interrupt has already been created as a fast interrupt. + * + * Value: 0x02000907 + * + * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created. + */ +#define OS_ERRNO_HWI_FASTMODE_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x07) + +#if (OS_HWI_WITH_ARG == 1) +/* * + * @ingroup los_hwi + * Set interrupt vector table. + */ +extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg); +#else +/* * + * @ingroup los_hwi + * Set interrupt vector table. + */ +extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector); +#endif + +/* * + * @ingroup los_arch_interrupt + * @brief: Hardware interrupt entry function. + * + * @par Description: + * This API is used as all hardware interrupt handling function entry. + * + * @attention: + * + * + * @param:None. + * + * @retval:None. + * @par Dependency: + * + * @see None. + */ +extern VOID HalInterrupt(VOID); + +/* * + * @ingroup los_arch_interrupt + * @brief: Get an interrupt number. + * + * @par Description: + * This API is used to get the current interrupt number. + * + * @attention: + * + * + * @param: None. + * + * @retval: Interrupt Indexes number. + * @par Dependency: + * + * @see None. + */ +extern UINT32 HalIntNumGet(VOID); + +/* * + * @ingroup los_arch_interrupt + * @brief: Default vector handling function. + * + * @par Description: + * This API is used to configure interrupt for null function. + * + * @attention: + * + * + * @param:None. + * + * @retval:None. + * @par Dependency: + * + * @see None. + */ +extern VOID HalHwiDefaultHandler(VOID); + +#define OS_EXC_IN_INIT 0 +#define OS_EXC_IN_TASK 1 +#define OS_EXC_IN_HWI 2 + +#define OS_EXC_FLAG_FAULTADDR_VALID 0x01 +#define OS_EXC_FLAG_IN_HWI 0x02 + +#define OS_EXC_IMPRECISE_ACCESS_ADDR 0xABABABAB + +/** + * @ingroup los_exc + * the struct of register files + * + * description: the register files that saved when exception triggered + * + * notes:the following register with prefix 'uw' correspond to the registers in the cpu data sheet. + */ +typedef struct TagExcContext { + UINT32 spsr; + UINT32 r0; + UINT32 r1; + UINT32 r2; + UINT32 r3; + UINT32 r4; + UINT32 r5; + UINT32 r6; + UINT32 r7; + UINT32 r8; + UINT32 r9; + UINT32 r10; + UINT32 r11; + UINT32 r12; + UINT32 sp; + UINT32 lr; + UINT32 pc; +} EXC_CONTEXT_S; + +typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *); +VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr); +VOID HalHwiInit(); + +/** + * @ingroup los_exc + * exception types: undefined instruction exception. + */ +#define OS_EXCEPT_UNDEF_INSTR 1 + +/** + * @ingroup los_exc + * exception types: software interrupt. + */ +#define OS_EXCEPT_SWI 2 + +/** + * @ingroup los_exc + * exception types: prefetch abort exception. + */ +#define OS_EXCEPT_PREFETCH_ABORT 3 + +/** + * @ingroup los_exc + * exception types: data abort exception. + */ +#define OS_EXCEPT_DATA_ABORT 4 + +/** + * @ingroup los_exc + * exception types: FIQ exception. + */ +#define OS_EXCEPT_FIQ 5 + +/** + * @ingroup los_exc + * Exception information structure + * + * Description: Exception information saved when an exception is triggered on the Cortex-M4 platform. + * + */ +typedef struct TagExcInfo { + /**< Exception occurrence phase: 0 means that an exception occurs in initialization, 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */ + UINT16 phase; + /**< Exception type. When exceptions occur, check the numbers 1 - 19 listed above */ + UINT16 type; + /**< If the exact address access error indicates the wrong access address when the exception occurred */ + UINT32 faultAddr; + /**< An exception occurs in an interrupt, indicating the interrupt number. An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */ + UINT32 thrdPid; + /**< Number of nested exceptions. Currently only registered hook functions are supported when an exception is entered for the first time */ + UINT16 nestCnt; + /**< reserve */ + UINT16 reserved; + /**< Hardware context at the time an exception to the automatic stack floating-point register occurs */ + EXC_CONTEXT_S *context; +} ExcInfo; + +extern UINT32 g_intCount; +extern ExcInfo g_excInfo; + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#endif /* _LOS_ARCH_INTERRUPT_H */ diff --git a/kernel/arch/arm/arm9/gcc/los_arch_timer.h b/kernel/arch/arm/arm9/gcc/los_arch_timer.h new file mode 100644 index 00000000..97ec28d1 --- /dev/null +++ b/kernel/arch/arm/arm9/gcc/los_arch_timer.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. + * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _LOS_ARCH_TIMER_H +#define _LOS_ARCH_TIMER_H + +#include "los_config.h" +#include "los_compiler.h" +#include "los_context.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +UINT32 HalTickStart(OS_TICK_HANDLER handler); + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#endif /* _LOS_ARCH_TIMER_H */ diff --git a/kernel/arch/arm/arm9/gcc/los_context.c b/kernel/arch/arm/arm9/gcc/los_context.c new file mode 100644 index 00000000..e332cbeb --- /dev/null +++ b/kernel/arch/arm/arm9/gcc/los_context.c @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. + * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "los_context.h" +#include "securec.h" +#include "los_arch_context.h" +#include "los_arch_interrupt.h" +#include "los_task.h" +#include "los_sched.h" +#include "los_interrupt.h" +#include "los_arch_timer.h" +#include "los_debug.h" + +UINT32 g_sysNeedSched = 0; + +/* **************************************************************************** + Function : HalArchInit + Description : arch init function + Input : None + Output : None + Return : None + **************************************************************************** */ +LITE_OS_SEC_TEXT_INIT VOID HalArchInit() +{ + HalHwiInit(); +} + +/* **************************************************************************** + Function : HalSysExit + Description : Task exit function + Input : None + Output : None + Return : None + **************************************************************************** */ +LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID) +{ + LOS_IntLock(); + while (1) { + } +} + +/* **************************************************************************** + Function : HalTskStackInit + Description : Task stack initialization function + Input : taskID --- TaskID + stackSize --- Total size of the stack + topStack --- Top of task's stack + Output : None + Return : Context pointer + **************************************************************************** */ +LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack) +{ + TaskContext *context = NULL; + LosTaskCB *taskCB = OS_TCB_FROM_TID(taskID); + errno_t result; + + /* initialize the task stack, write magic num to stack top */ + result = memset_s(topStack, stackSize, (INT32)(OS_TASK_STACK_INIT & 0xFF), stackSize); + if (result != EOK) { + PRINT_ERR("memset_s is failed:%s[%d]\r\n", __FUNCTION__, __LINE__); + } + *((UINT32 *)(topStack)) = OS_TASK_MAGIC_WORD; + + context = (TaskContext *)(((UINTPTR)topStack + stackSize) - sizeof(TaskContext)); + + context->r0 = taskID; + context->r1 = 0x01010101L; + context->r2 = 0x02020202L; + context->r3 = 0x03030303L; + context->r4 = 0x04040404L; + context->r5 = 0x05050505L; + context->r6 = 0x06060606L; + context->r7 = 0x07070707L; + context->r8 = 0x08080808L; + context->r9 = 0x09090909L; + context->r10 = 0x10101010L; + context->r11 = 0x11111111L; + context->r12 = 0x12121212L; + context->lr = (UINTPTR)HalSysExit; + + if ((UINTPTR)taskCB->taskEntry & 0x01) { + context->pc = (UINTPTR)OsTaskEntryThumb; + context->spsr = PSR_MODE_SVC_THUMB; /* thumb mode */ + } else { + context->pc = (UINTPTR)OsTaskEntryArm; + context->spsr = PSR_MODE_SVC_ARM; /* arm mode */ + } + + return (VOID *)context; +} + +LITE_OS_SEC_TEXT_INIT UINT32 HalStartSchedule(OS_TICK_HANDLER handler) +{ + (VOID)LOS_IntLock(); + UINT32 ret = HalTickStart(handler); + if (ret != LOS_OK) { + return ret; + } + + OsSchedStart(); + HalStartToRun(); + + return LOS_OK; /* never return */ +} + +LITE_OS_SEC_TEXT_INIT VOID dmb(VOID) +{ + __asm__ __volatile__("" : : : "memory"); +} + +LITE_OS_SEC_TEXT_INIT VOID dsb(VOID) +{ + __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" : : "r"(0) : "memory"); +} + +LITE_OS_SEC_TEXT_INIT VOID isb(VOID) +{ + __asm__ __volatile__("" : : : "memory"); +} + +LITE_OS_SEC_TEXT_INIT VOID wfi(VOID) +{ + __asm__ __volatile__("mcr p15, 0, %0, c7, c0, 4" : : "r"(0) : "memory"); +} + diff --git a/kernel/arch/arm/arm9/gcc/los_dispatch.S b/kernel/arch/arm/arm9/gcc/los_dispatch.S new file mode 100644 index 00000000..b83a730e --- /dev/null +++ b/kernel/arch/arm/arm9/gcc/los_dispatch.S @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. + * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + .equ OS_PSR_THUMB, 0x20U + .equ OS_PSR_INT_DIS, 0xC0U + .equ OS_PSR_FIQ_DIS, 0x40U + .equ OS_PSR_IRQ_DIS, 0x80U + .equ OS_PSR_MODE_MASK, 0x1FU + .equ OS_PSR_MODE_USR, 0x10U + .equ OS_PSR_MODE_FIQ, 0x11U + .equ OS_PSR_MODE_IRQ, 0x12U + .equ OS_PSR_MODE_SVC, 0x13U + .equ OS_PSR_MODE_ABT, 0x17U + .equ OS_PSR_MODE_UND, 0x1BU + .equ OS_PSR_MODE_SYS, 0x1FU + + .global HalExceptIrqHdl + .global HalTaskSchedule + .global HalStartToRun + .global OsTaskEntryArm + .global OsTaskEntryThumb + + .extern OsTaskEntry + .extern OsSchedTaskSwitch + .extern g_sysNeedSched + + .code 32 + .text + +HalStartToRun: + MSR CPSR_c, #(OS_PSR_INT_DIS | OS_PSR_FIQ_DIS | OS_PSR_MODE_SVC) + + LDR R1, =g_losTask + LDR R0, [R1, #4] + LDR SP, [R0] + + LDMFD SP!, {R0} + MSR SPSR_cxsf, R0 + + LDMFD SP!, {R0-R12, LR, PC}^ + +HalTaskSchedule: + STMFD SP!, {LR} + STMFD SP!, {LR} + STMFD SP!, {R0-R12} + + MRS R0, CPSR + MRS R1, CPSR + ORR R1, #OS_PSR_IRQ_DIS + MSR CPSR, R1 + + TST LR, #1 + ORRNE R0, R0, #OS_PSR_THUMB + STMFD SP!, {R0} + + LDR R1, =g_sysNeedSched + MOV R2, #1 + STR R2, [R1] + + LDR R0, =g_intCount + LDR R0, [R0] + CMP R0, #0 + BNE TaskContextLoad + STR R0, [R1] + + BLX OsSchedTaskSwitch + CMP R0, #0 + BNE NewTaskContextSwitch + B TaskContextLoad + +NewTaskContextSwitch: + LDR R0, =g_losTask + LDR R1, [R0] + STR SP, [R1] + + LDR R1, [R0, #4] + STR R1, [R0] + LDR SP, [R1] + +TaskContextLoad: + LDMFD SP!, {R0} + MSR SPSR_cxsf, R0 + LDMFD SP!, {R0-R12, LR, PC}^ + +OsTaskEntryArm: + STMFD SP!, {LR} + BL OsTaskEntry + LDMFD SP!, {LR} + BX LR + + .code 16 + .text +OsTaskEntryThumb: + PUSH {LR} + BL OsTaskEntry + POP {R0} + MOV LR, R0 + BX LR + diff --git a/kernel/arch/arm/arm9/gcc/los_exc.S b/kernel/arch/arm/arm9/gcc/los_exc.S new file mode 100644 index 00000000..54f32aa6 --- /dev/null +++ b/kernel/arch/arm/arm9/gcc/los_exc.S @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. + * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + .equ OS_PSR_INT_DIS, 0xC0U + .equ OS_PSR_FIQ_DIS, 0x40U + .equ OS_PSR_IRQ_DIS, 0x80U + .equ OS_PSR_MODE_MASK, 0x1FU + .equ OS_PSR_MODE_USR, 0x10U + .equ OS_PSR_MODE_FIQ, 0x11U + .equ OS_PSR_MODE_IRQ, 0x12U + .equ OS_PSR_MODE_SVC, 0x13U + .equ OS_PSR_MODE_ABT, 0x17U + .equ OS_PSR_MODE_UND, 0x1BU + .equ OS_PSR_MODE_SYS, 0x1FU + + .equ OS_EXCEPT_RESET, 0x00 + .equ OS_EXCEPT_UNDEF_INSTR, 0x01 + .equ OS_EXCEPT_SWI, 0x02 + .equ OS_EXCEPT_PREFETCH_ABORT, 0x03 + .equ OS_EXCEPT_DATA_ABORT, 0x04 + .equ OS_EXCEPT_FIQ, 0x05 + .equ OS_EXCEPT_ADDR_ABORT, 0x06 + .equ OS_EXCEPT_IRQ, 0x07 + + + .global HalExceptFiqHdl + .global HalExceptAddrAbortHdl + .global HalExceptDataAbortHdl + .global HalExceptPrefetchAbortHdl + .global HalExceptSwiHdl + .global HalExceptUndefInstrHdl + .global HalExceptIrqHdl + + .extern g_sysNeedSched + .extern g_losTaskLock + .extern HalExcHandleEntry + .extern HalInterrupt + .extern OsSchedTaskSwitch + .extern __svc_stack_top + .extern __exc_stack_top + .extern __irq_stack_top + + .code 32 + .text + +HalExceptUndefInstrHdl: + STMFD SP!, {R0-R5} + MOV R0, #OS_EXCEPT_UNDEF_INSTR + B _osExceptDispatch + +HalExceptSwiHdl: + STMFD SP!, {LR} + STMFD SP!, {LR} + STMFD SP!, {SP} + STMFD SP!, {R0-R12} + + MRS R1, SPSR + STMFD SP!, {R1} + + MOV R0, #OS_EXCEPT_SWI + + B _osExceptionSwi + +HalExceptPrefetchAbortHdl: + SUB LR, LR, #4 + STMFD SP!, {R0-R5} + + MOV R0, #OS_EXCEPT_PREFETCH_ABORT + + B _osExceptDispatch + +HalExceptDataAbortHdl: + SUB LR, LR, #4 + STMFD SP!, {R0-R5} + + MOV R0, #OS_EXCEPT_DATA_ABORT + + B _osExceptDispatch + +HalExceptAddrAbortHdl: + SUB LR, LR, #8 + STMFD SP!, {R0-R5} + + MOV R0, #OS_EXCEPT_ADDR_ABORT + + B _osExceptDispatch + +HalExceptFiqHdl: + SUB LR, LR, #4 + STMFD SP!, {R0-R5} + + MOV R0, #OS_EXCEPT_FIQ + + B _osExceptDispatch + +HalExceptIrqHdl: + SUB LR, LR, #4 + STMFD SP!, {R0-R2} + + MOV R0, SP + MRS R1, SPSR + MOV R2, LR + + MSR CPSR_c, #(OS_PSR_INT_DIS | OS_PSR_FIQ_DIS | OS_PSR_MODE_SVC) + STMFD SP!, {R2} + STMFD SP!, {LR} + STMFD SP!, {R3-R12} + LDMFD R0!, {R5-R7} + STMFD SP!, {R5-R7} + STMFD SP!, {R1} + + LDR R2, =g_losTask + LDR R3, [R2] + STR SP, [R3] + + LDR SP, =__svc_stack_top + + BLX HalInterrupt + + LDR R0, =g_losTaskLock + LDR R0, [R0] + CMP R0, #0 + BNE NoTaskContextSwitch + + LDR R0, =g_sysNeedSched + LDR R0, [R0] + CMP R0, #0 + BNE NeedTaskSwitch + B NoTaskContextSwitch + +NeedTaskSwitch: + LDR R0, =g_sysNeedSched + MOV R1, #0 + STR R1, [R0] + BLX OsSchedTaskSwitch + CMP R0, #0 + BEQ NoTaskContextSwitch + LDR R0, =g_losTask + LDR R1, [R0, #4] + STR R1, [R0] + LDR SP, [R1] + B TaskContextLoad + +NoTaskContextSwitch: + LDR R1, =g_losTask + LDR R1, [R1] + LDR SP, [R1] + +TaskContextLoad: + LDMFD SP!, {R0} + MSR SPSR_cxsf, R0 + LDMFD SP!, {R0-R12, LR, PC}^ + +_osExceptDispatch: + MRS R1, SPSR + MOV R2, LR + MOV R4, SP + ADD SP, SP, #(6 * 4) + + MSR CPSR_c, #(OS_PSR_INT_DIS | OS_PSR_MODE_SVC) + MOV R3, SP + LDR SP, =__exc_stack_top + + STMFD SP!, {R2} + STMFD SP!, {LR} + STMFD SP!, {R3} + STMFD SP!, {R6-R12} + LDMFD R4!, {R6-R12} + STMFD SP!, {R6-R11} + STMFD SP!, {R1} + +_osExceptionSwi: + MOV R3, SP + +_osExceptionGetSP: + STMFD SP!, {R1} + LDR R2, =HalExcHandleEntry + + MOV LR, PC + BX R2 + + LDMFD SP!, {R1} + MOV SP, R1 + + LDMFD SP!, {R1} + MSR CPSR, R1 + LDMFD SP!, {R0-R12} + ADD SP, SP, #(4 * 2) + LDMFD SP!, {LR} + SUB SP, SP, #(4 * 3) + LDMFD SP, {SP} + ADD LR, LR, #4 + MOV PC, LR + + .end diff --git a/kernel/arch/arm/arm9/gcc/los_interrupt.c b/kernel/arch/arm/arm9/gcc/los_interrupt.c new file mode 100644 index 00000000..06d7d929 --- /dev/null +++ b/kernel/arch/arm/arm9/gcc/los_interrupt.c @@ -0,0 +1,481 @@ +/* + * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. + * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "los_interrupt.h" +#include +#include "securec.h" +#include "los_context.h" +#include "los_arch_interrupt.h" +#include "los_debug.h" +#include "los_hook.h" +#include "los_task.h" +#include "los_sched.h" +#include "los_memory.h" +#include "los_membox.h" +#include "los_reg.h" + +#define OS_INT_IRQ_ENABLE (1U << 0) +#define OS_INT_FIQ_ENABLE (1U << 1) +#define OS_INT_REG_BASE 0x00802040UL +#define OS_INT_GLOBAL_ENABLE_ADDR (OS_INT_REG_BASE + 4) +#define OS_INT_ENABLE_ADDR (OS_INT_REG_BASE) +#define OS_INT_STATUS_ADDR (OS_INT_REG_BASE + 12) + +#define OS_INT_ENABLE(num) (*((volatile UINT32 *)OS_INT_ENABLE_ADDR) |= (1U << (num))) +#define OS_INT_DISABLE(num) (*((volatile UINT32 *)OS_INT_ENABLE_ADDR ) &= ~(1U << (num))) + +#define OS_INSTR_SET_MASK 0x01000020U +#define OS_ARM_INSTR_LEN 4 +#define OS_THUMB_INSTR_LEN 2 + +UINT32 g_intCount = 0; +ExcInfo g_excInfo = {0}; + +/* * + * @ingroup los_hwi + * hardware interrupt form mapping handling function array. + */ +STATIC HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT] = {0}; + +#if (OS_HWI_WITH_ARG == 1) + +typedef struct { + HWI_PROC_FUNC pfnHandler; + VOID *pParm; +} HWI_HANDLER_FUNC; + +/* * + * @ingroup los_hwi + * hardware interrupt handler form mapping handling function array. + */ +STATIC HWI_HANDLER_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {{ (HWI_PROC_FUNC)0, (HWI_ARG_T)0 }}; + +/* * + * @ingroup los_hwi + * Set interrupt vector table. + */ +VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg) +{ + if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) { + g_hwiForm[num + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalInterrupt; + g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pfnHandler = vector; + g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pParm = arg; + } +} + +#else +/* * + * @ingroup los_hwi + * hardware interrupt handler form mapping handling function array. + */ +STATIC HWI_PROC_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {0}; + +/* * + * @ingroup los_hwi + * Set interrupt vector table. + */ +VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector) +{ + if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) { + g_hwiForm[num + OS_SYS_VECTOR_CNT] = HalInterrupt; + g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT] = vector; + } +} +#endif + + +/* **************************************************************************** + Function : HalIntNumGet + Description : Get an interrupt number + Input : None + Output : None + Return : Interrupt Indexes number + **************************************************************************** */ +LITE_OS_SEC_TEXT_MINOR UINT32 HalIntNumGet(VOID) +{ + UINT32 status; + + READ_UINT32(status, OS_INT_STATUS_ADDR); + return (31 - CLZ(status)); +} + +inline UINT32 HalIsIntActive(VOID) +{ + return (g_intCount > 0); +} +/* **************************************************************************** + Function : HalHwiDefaultHandler + Description : default handler of the hardware interrupt + Input : None + Output : None + Return : None + **************************************************************************** */ +/*lint -e529*/ +LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID) +{ + UINT32 irqNum = HalIntNumGet(); + PRINT_ERR("%s irqnum:%d\n", __FUNCTION__, irqNum); + while (1) {} +} + +WEAK VOID HalPreInterruptHandler(UINT32 arg) +{ + return; +} + +WEAK VOID HalAftInterruptHandler(UINT32 arg) +{ + return; +} + +/* **************************************************************************** + Function : HalInterrupt + Description : Hardware interrupt entry function + Input : None + Output : None + Return : None + **************************************************************************** */ +LITE_OS_SEC_TEXT VOID HalInterrupt(VOID) +{ + UINT32 intSave; + UINT32 hwiIndex; + + intSave = LOS_IntLock(); + g_intCount++; + LOS_IntRestore(intSave); + +#if (LOSCFG_BASE_CORE_SCHED_SLEEP == 1) + OsSchedUpdateSleepTime(); +#endif + + hwiIndex = HalIntNumGet(); + + OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex); + + HalPreInterruptHandler(hwiIndex); + +#if (OS_HWI_WITH_ARG == 1) + if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) { + g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm); + } +#else + if (g_hwiHandlerForm[hwiIndex] != 0) { + g_hwiHandlerForm[hwiIndex](); + } +#endif + + HalAftInterruptHandler(hwiIndex); + + OsHookCall(LOS_HOOK_TYPE_ISR_EXIT, hwiIndex); + + intSave = LOS_IntLock(); + g_intCount--; + LOS_IntRestore(intSave); +} + +/* **************************************************************************** + Function : HalHwiCreate + Description : create hardware interrupt + Input : hwiNum --- hwi num to create + hwiPrio --- priority of the hwi + mode --- unused + handler --- hwi handler + arg --- param of the hwi handler + Output : None + Return : LOS_OK on success or error code on failure + **************************************************************************** */ +LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum, + HWI_PRIOR_T hwiPrio, + HWI_MODE_T mode, + HWI_PROC_FUNC handler, + HWI_ARG_T arg) +{ + UINT32 intSave; + + if (handler == NULL) { + return OS_ERRNO_HWI_PROC_FUNC_NULL; + } + + if (hwiNum >= OS_HWI_MAX_NUM) { + return OS_ERRNO_HWI_NUM_INVALID; + } + + if (g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] != (HWI_PROC_FUNC)HalHwiDefaultHandler) { + return OS_ERRNO_HWI_ALREADY_CREATED; + } + + intSave = LOS_IntLock(); +#if (OS_HWI_WITH_ARG == 1) + OsSetVector(hwiNum, handler, arg); +#else + OsSetVector(hwiNum, handler); +#endif + OS_INT_ENABLE(hwiNum); + LOS_IntRestore(intSave); + + return LOS_OK; +} + +/* **************************************************************************** + Function : HalHwiDelete + Description : Delete hardware interrupt + Input : hwiNum --- hwi num to delete + Output : None + Return : LOS_OK on success or error code on failure + **************************************************************************** */ +LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum) +{ + UINT32 intSave; + + if (hwiNum >= OS_HWI_MAX_NUM) { + return OS_ERRNO_HWI_NUM_INVALID; + } + + OS_INT_DISABLE(hwiNum); + + intSave = LOS_IntLock(); + g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalHwiDefaultHandler; + LOS_IntRestore(intSave); + + return LOS_OK; +} + +#if (LOSCFG_KERNEL_PRINTF != 0) +STATIC VOID OsExcTypeInfo(const ExcInfo *excInfo) +{ + CHAR *phaseStr[] = {"exc in init", "exc in task", "exc in hwi"}; + + PRINTK("Type = %d\n", excInfo->type); + PRINTK("ThrdPid = %d\n", excInfo->thrdPid); + PRINTK("Phase = %s\n", phaseStr[excInfo->phase]); + PRINTK("FaultAddr = 0x%x\n", excInfo->faultAddr); +} + +STATIC VOID OsExcCurTaskInfo(const ExcInfo *excInfo) +{ + PRINTK("Current task info:\n"); + if (excInfo->phase == OS_EXC_IN_TASK) { + LosTaskCB *taskCB = OS_TCB_FROM_TID(LOS_CurTaskIDGet()); + PRINTK("Task name = %s\n", taskCB->taskName); + PRINTK("Task ID = %d\n", taskCB->taskID); + PRINTK("Task SP = 0x%x\n", taskCB->stackPointer); + PRINTK("Task ST = 0x%x\n", taskCB->topOfStack); + PRINTK("Task SS = 0x%x\n", taskCB->stackSize); + } else if (excInfo->phase == OS_EXC_IN_HWI) { + PRINTK("Exception occur in interrupt phase!\n"); + } else { + PRINTK("Exception occur in system init phase!\n"); + } +} + +STATIC VOID OsExcRegInfo(const ExcInfo *excInfo) +{ + PRINTK("Exception reg dump:\n"); + PRINTK("PC = 0x%x\n", excInfo->context->pc); + PRINTK("LR = 0x%x\n", excInfo->context->lr); + PRINTK("R0 = 0x%x\n", excInfo->context->r0); + PRINTK("R1 = 0x%x\n", excInfo->context->r1); + PRINTK("R2 = 0x%x\n", excInfo->context->r2); + PRINTK("R3 = 0x%x\n", excInfo->context->r3); + PRINTK("R4 = 0x%x\n", excInfo->context->r4); + PRINTK("R5 = 0x%x\n", excInfo->context->r5); + PRINTK("R6 = 0x%x\n", excInfo->context->r6); + PRINTK("R7 = 0x%x\n", excInfo->context->r7); + PRINTK("R8 = 0x%x\n", excInfo->context->r8); + PRINTK("R9 = 0x%x\n", excInfo->context->r9); + PRINTK("R10 = 0x%x\n", excInfo->context->r10); + PRINTK("R11 = 0x%x\n", excInfo->context->r11); + PRINTK("R12 = 0x%x\n", excInfo->context->r12); + PRINTK("xPSR = 0x%x\n", excInfo->context->spsr); +} + +STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo) +{ + UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0}; + UINT32 index; + + OsBackTraceHookCall(LR, LOSCFG_BACKTRACE_DEPTH, 0, excInfo->context->sp); + + PRINTK("----- backtrace start -----\n"); + for (index = 0; index < LOSCFG_BACKTRACE_DEPTH; index++) { + if (LR[index] == 0) { + break; + } + PRINTK("backtrace %d -- lr = 0x%x\n", index, LR[index]); + } + PRINTK("----- backtrace end -----\n"); +} + +STATIC VOID OsExcMemPoolCheckInfo(VOID) +{ + PRINTK("\r\nmemory pools check:\n"); +#if (LOSCFG_PLATFORM_EXC == 1) + MemInfoCB memExcInfo[OS_SYS_MEM_NUM]; + UINT32 errCnt; + UINT32 i; + + (VOID)memset_s(memExcInfo, sizeof(memExcInfo), 0, sizeof(memExcInfo)); + + errCnt = OsMemExcInfoGet(OS_SYS_MEM_NUM, memExcInfo); + if (errCnt < OS_SYS_MEM_NUM) { + errCnt += OsMemboxExcInfoGet(OS_SYS_MEM_NUM - errCnt, memExcInfo + errCnt); + } + + if (errCnt == 0) { + PRINTK("all memory pool check passed!\n"); + return; + } + + for (i = 0; i < errCnt; i++) { + PRINTK("pool num = %d\n", i); + PRINTK("pool type = %d\n", memExcInfo[i].type); + PRINTK("pool addr = 0x%x\n", memExcInfo[i].startAddr); + PRINTK("pool size = 0x%x\n", memExcInfo[i].size); + PRINTK("pool free = 0x%x\n", memExcInfo[i].free); + PRINTK("pool blkNum = %d\n", memExcInfo[i].blockSize); + PRINTK("pool error node addr = 0x%x\n", memExcInfo[i].errorAddr); + PRINTK("pool error node len = 0x%x\n", memExcInfo[i].errorLen); + PRINTK("pool error node owner = %d\n", memExcInfo[i].errorOwner); + } +#endif + UINT32 ret = LOS_MemIntegrityCheck(LOSCFG_SYS_HEAP_ADDR); + if (ret == LOS_OK) { + PRINTK("system heap memcheck over, all passed!\n"); + } + + PRINTK("memory pool check end!\n"); +} +#endif + +STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo) +{ +#if (LOSCFG_KERNEL_PRINTF != 0) + PRINTK("*************Exception Information**************\n"); + OsExcTypeInfo(excInfo); + OsExcCurTaskInfo(excInfo); + OsExcRegInfo(excInfo); + OsExcBackTraceInfo(excInfo); + OsGetAllTskInfo(); + OsExcMemPoolCheckInfo(); +#endif +} + +LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr) +{ + g_intCount++; + g_excInfo.nestCnt++; + + g_excInfo.type = excType; + + if ((excType == OS_EXCEPT_UNDEF_INSTR) || (excType == OS_EXCEPT_SWI)) { + if ((excBufAddr->spsr & OS_INSTR_SET_MASK) == 0) { /* Work status: ARM */ + excBufAddr->pc -= OS_ARM_INSTR_LEN; + } else if ((excBufAddr->spsr & OS_INSTR_SET_MASK) == 0x20) { /* Work status: Thumb */ + excBufAddr->pc -= OS_THUMB_INSTR_LEN; + } + } + g_excInfo.faultAddr = OS_EXC_IMPRECISE_ACCESS_ADDR; + + if (g_losTask.runTask != NULL) { + g_excInfo.phase = OS_EXC_IN_TASK; + g_excInfo.thrdPid = g_losTask.runTask->taskID; + } else { + g_excInfo.phase = OS_EXC_IN_INIT; + g_excInfo.thrdPid = OS_NULL_INT; + } + g_excInfo.context = excBufAddr; + + OsDoExcHook(EXC_INTERRUPT); + OsExcInfoDisplay(&g_excInfo); + HalSysExit(); +} + +/* **************************************************************************** + Function : HalHwiInit + Description : initialization of the hardware interrupt + Input : None + Output : None + Return : None + **************************************************************************** */ +LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID) +{ +#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1) + UINT32 reg; + UINT32 val; + + for (val = OS_SYS_VECTOR_CNT; val < OS_VECTOR_CNT; val++) { +#if (OS_HWI_WITH_ARG == 1) + g_hwiForm[val].pfnHook = HalHwiDefaultHandler; + g_hwiForm[val].uwParam = 0; +#else + g_hwiForm[val] = (HWI_PROC_FUNC)HalHwiDefaultHandler; +#endif + } + + val = OS_INT_IRQ_ENABLE | OS_INT_FIQ_ENABLE; + READ_UINT32(reg, OS_INT_GLOBAL_ENABLE_ADDR); + reg |= val; + WRITE_UINT32(reg, OS_INT_GLOBAL_ENABLE_ADDR); +#endif + return; +} + +UINT32 HalIntLock(VOID) +{ + UINT32 ret; + UINT32 temp; + + __asm__ __volatile__("MRS %0, CPSR\n" + "ORR %1, %0, #0xC0\n" + "MSR CPSR_c, %1" + : "=r"(ret), "=r"(temp) + : + : "memory"); + return ret; +} + +VOID HalIntRestore(UINT32 intSave) +{ + __asm__ __volatile__("MSR CPSR_c, %0" : : "r"(intSave)); +} + +UINT32 HalIntUnLock(VOID) +{ + UINT32 intSave; + + __asm__ __volatile__("MRS %0, CPSR\n" + "BIC %0, %0, #0xC0\n" + "MSR CPSR_c, %0" + : "=r"(intSave) + : + : "memory"); + return intSave; +} + diff --git a/kernel/arch/arm/arm9/gcc/los_timer.c b/kernel/arch/arm/arm9/gcc/los_timer.c new file mode 100644 index 00000000..62f6990d --- /dev/null +++ b/kernel/arch/arm/arm9/gcc/los_timer.c @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. + * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "los_config.h" +#include "los_sched.h" +#include "los_arch_context.h" +#include "los_arch_interrupt.h" +#include "los_reg.h" + +#define OS_TIMER_CLKDIV_POS 3 +#define OS_TIMER_CLKDIV_MASK 7 +#define OS_TIMER_INT_POS 7 +#define OS_TIMER_INT_MASK 7 +#define OS_TIMER_IRQ_NUM 8 +#define OS_TIMER_ENABLE (1U << 0) +#define OS_TIMER_32K_CLK_BIT (1U << 21) +#define OS_TIMER_CNT_READ_BIT (1U << 0) + +#define OS_TIMER_REG_BASE 0x00802A40UL +#define OS_TIMER_CLK_PWD_ADDR 0x00802008UL +#define OS_TIMER_PERIOD_REG_ADDR (OS_TIMER_REG_BASE) +#define OS_TIMER_CTL_REG_ADDR (OS_TIMER_REG_BASE + 12) +#define OS_TIMER_READ_CTL_ADDR (OS_TIMER_REG_BASE + 16) +#define OS_TIMER_READ_VAL_ADDR (OS_TIMER_REG_BASE + 20) + +/* **************************************************************************** +Function : HalTickStart +Description : Configure Tick Interrupt Start +Input : none +output : none +return : LOS_OK - Success , or LOS_ERRNO_TICK_CFG_INVALID - failed +**************************************************************************** */ +WEAK UINT32 HalTickStart(OS_TICK_HANDLER *handler) +{ + UINT32 intSave = LOS_IntLock(); + UINT32 value; + + READ_UINT32(value, OS_TIMER_CLK_PWD_ADDR); + value &= ~(OS_TIMER_32K_CLK_BIT); + WRITE_UINT32(value, OS_TIMER_CLK_PWD_ADDR); + + value = OS_SYS_CLOCK / LOSCFG_BASE_CORE_TICK_PER_SECOND; + WRITE_UINT32(value, OS_TIMER_PERIOD_REG_ADDR); + + READ_UINT32(value, OS_TIMER_CTL_REG_ADDR); + value &= ~(OS_TIMER_CLKDIV_MASK << OS_TIMER_CLKDIV_POS); // The default is 1, and the clock does not divide. + value &= ~(OS_TIMER_INT_MASK << OS_TIMER_INT_POS); // Clearing interruption. + value |= 0x1 << OS_TIMER_INT_POS; + value |= OS_TIMER_ENABLE; // Enable timer. + WRITE_UINT32(value, OS_TIMER_CTL_REG_ADDR); + + (VOID)HalHwiCreate(OS_TIMER_IRQ_NUM, 0, 0, (HWI_PROC_FUNC)handler, 0); + LOS_IntRestore(intSave); + + return LOS_OK; +} + +STATIC VOID HalClockIrqClear(VOID) +{ + UINT32 mask = OS_TIMER_INT_MASK << OS_TIMER_INT_POS; + UINT32 status; + + do { + WRITE_UINT32(mask, OS_TIMER_CTL_REG_ADDR); + READ_UINT32(status, OS_TIMER_CTL_REG_ADDR); + } while (status & mask); +} + +WEAK VOID HalSysTickReload(UINT64 nextResponseTime) +{ + HalTickLock(); + WRITE_UINT32(nextResponseTime, OS_TIMER_PERIOD_REG_ADDR); + HalClockIrqClear(); + HalTickUnlock(); +} + +WEAK UINT64 HalGetTickCycle(UINT32 *period) +{ + UINT32 val; + + READ_UINT32(*period, OS_TIMER_PERIOD_REG_ADDR); + + WRITE_UINT32(OS_TIMER_CNT_READ_BIT, OS_TIMER_READ_CTL_ADDR); + do { + READ_UINT32(val, OS_TIMER_READ_CTL_ADDR); + } while (val & OS_TIMER_CNT_READ_BIT); // Wait for the setting to take effect. + + READ_UINT32(val, OS_TIMER_READ_VAL_ADDR); + + return (UINT64)val; +} + +WEAK VOID HalTickLock(VOID) +{ + UINT32 value; + + READ_UINT32(value, OS_TIMER_CTL_REG_ADDR); + value &= ~OS_TIMER_ENABLE; + value &= ~(OS_TIMER_INT_MASK << OS_TIMER_INT_POS); + value |= 0x1 << OS_TIMER_INT_POS; + WRITE_UINT32(value, OS_TIMER_CTL_REG_ADDR); +} + +WEAK VOID HalTickUnlock(VOID) +{ + UINT32 value; + + READ_UINT32(value, OS_TIMER_CTL_REG_ADDR); + value |= OS_TIMER_ENABLE; + value &= ~(OS_TIMER_INT_MASK << OS_TIMER_INT_POS); + value |= 0x1 << OS_TIMER_INT_POS; + WRITE_UINT32(value, OS_TIMER_CTL_REG_ADDR); +} + +VOID HalEnterSleep(LOS_SysSleepEnum sleep) +{ +#if (LOSCFG_BASE_CORE_SCHED_SLEEP == 1) + if (sleep == OS_SYS_DEEP_SLEEP) { + OsSchedToSleep(); + } +#endif + + dsb(); + wfi(); + isb(); +} diff --git a/kernel/arch/arm/arm9/gcc/reset_vector.S b/kernel/arch/arm/arm9/gcc/reset_vector.S new file mode 100644 index 00000000..27e40e43 --- /dev/null +++ b/kernel/arch/arm/arm9/gcc/reset_vector.S @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. + * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + .equ CPSR_IRQ_DISABLE, 0x80U + .equ CPSR_FIQ_DISABLE, 0x40U + .equ CPSR_THUMB_ENABLE, 0x20U + .equ CPSR_USER_MODE, 0x10U + .equ CPSR_FIQ_MODE, 0x11U + .equ CPSR_IRQ_MODE, 0x12U + .equ CPSR_SVC_MODE, 0x13U + .equ CPSR_ABT_MODE, 0x17U + .equ CPSR_UNDEF_MODE, 0x1BU + + .global __exc_stack_top + .global __irq_stack_top + .global __fiq_stack_top + .global __svc_stack_top + .global __abt_stack_top + .global __undef_stack_top + .global __exc_stack + .global __irq_stack + .global __fiq_stack + .global __svc_stack + .global __abt_stack + .global __undef_stack + .global main + + .extern HalExceptFiqHdl + .extern HalExceptAddrAbortHdl + .extern HalExceptDataAbortHdl + .extern HalExceptPrefetchAbortHdl + .extern HalExceptSwiHdl + .extern HalExceptUndefInstrHdl + .extern HalExceptIrqHdl + .extern _bss_start + .extern _bss_end + + .code 32 + .text + + .section ".vectors", "ax" + .global _vector_start + +_vector_start: + B HalResetVector + B HalExceptUndefInstrHdl + B HalExceptSwiHdl + B HalExceptPrefetchAbortHdl + B HalExceptDataAbortHdl + B HalExceptAddrAbortHdl + B HalExceptIrqHdl + B HalExceptFiqHdl + + + .globl HalResetVector + .section ".boot", "ax" + +HalResetVector: + MOV R0, #(CPSR_IRQ_DISABLE | CPSR_FIQ_DISABLE | CPSR_IRQ_MODE) + MSR CPSR, R0 + LDR SP, =__irq_stack_top + + MOV R0, #(CPSR_IRQ_DISABLE | CPSR_FIQ_DISABLE | CPSR_UNDEF_MODE) + MSR CPSR, R0 + LDR SP, =__undef_stack_top + + MOV R0, #(CPSR_IRQ_DISABLE | CPSR_FIQ_DISABLE | CPSR_ABT_MODE) + MSR CPSR, R0 + LDR SP, =__abt_stack_top + + MOV R0, #(CPSR_IRQ_DISABLE | CPSR_FIQ_DISABLE | CPSR_FIQ_MODE) + MSR CPSR, R0 + LDR SP, =__fiq_stack_top + + MOV R0, #(CPSR_IRQ_DISABLE | CPSR_FIQ_DISABLE | CPSR_SVC_MODE) + MSR CPSR, R0 + MSR SPSR, R0 + LDR SP, =__svc_stack_top + + BL OsBssInit + + B main + B . + +OsBssInit: + LDR R0, =_bss_start + LDR R1, =_bss_end + + MOV R3, R1 + MOV R4, R0 + MOV R2, #0 +1: CMP R4, R3 + STRLO R2, [R4], #4 + BLO 1b + BX LR + + .section ".bss", "wa", %nobits + .align 3 +__undef_stack: + .space 32 +__undef_stack_top: + +__abt_stack: + .space 32 +__abt_stack_top: + +__irq_stack: + .space 64 +__irq_stack_top: + +__fiq_stack: + .space 64 +__fiq_stack_top: + +__svc_stack: + .space 4096 +__svc_stack_top: + +__exc_stack: + .space 512 +__exc_stack_top: diff --git a/kernel/arch/include/los_context.h b/kernel/arch/include/los_context.h index 8038e90f..9fc30c62 100755 --- a/kernel/arch/include/los_context.h +++ b/kernel/arch/include/los_context.h @@ -107,15 +107,6 @@ extern VOID HalTaskSchedule(VOID); typedef VOID (*OS_TICK_HANDLER)(VOID); UINT32 HalStartSchedule(OS_TICK_HANDLER handler); -UINT32 HalIntLock(VOID); -#define LOS_IntLock HalIntLock - -VOID HalIntRestore(UINT32 intSave); -#define LOS_IntRestore HalIntRestore - -UINT32 HalIntUnLock(VOID); -#define LOS_IntUnLock HalIntUnLock - #ifdef __cplusplus #if __cplusplus } diff --git a/kernel/arch/include/los_interrupt.h b/kernel/arch/include/los_interrupt.h index 3fa2fe33..d600ae4b 100644 --- a/kernel/arch/include/los_interrupt.h +++ b/kernel/arch/include/los_interrupt.h @@ -71,6 +71,15 @@ UINT32 HalIsIntActive(VOID); #define OS_INT_ACTIVE (HalIsIntActive()) #define OS_INT_INACTIVE (!(OS_INT_ACTIVE)) +UINT32 HalIntLock(VOID); +#define LOS_IntLock HalIntLock + +VOID HalIntRestore(UINT32 intSave); +#define LOS_IntRestore HalIntRestore + +UINT32 HalIntUnLock(VOID); +#define LOS_IntUnLock HalIntUnLock + /** * @ingroup los_interrupt * @brief Delete hardware interrupt. diff --git a/kernel/src/los_task.c b/kernel/src/los_task.c index 76657dff..3164218b 100644 --- a/kernel/src/los_task.c +++ b/kernel/src/los_task.c @@ -647,7 +647,6 @@ LITE_OS_SEC_TEXT_INIT STATIC_INLINE UINT32 OsTaskInitParamCheck(TSK_INIT_PARAM_S LITE_OS_SEC_TEXT_INIT UINT32 OsNewTaskInit(LosTaskCB *taskCB, TSK_INIT_PARAM_S *taskInitParam, VOID *topOfStack) { - taskCB->stackPointer = HalTskStackInit(taskCB->taskID, taskInitParam->uwStackSize, topOfStack); taskCB->arg = taskInitParam->uwArg; taskCB->topOfStack = (UINT32)(UINTPTR)topOfStack; taskCB->stackSize = taskInitParam->uwStackSize; @@ -662,6 +661,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 OsNewTaskInit(LosTaskCB *taskCB, TSK_INIT_PARAM_S * taskCB->eventMask = 0; taskCB->taskName = taskInitParam->pcName; taskCB->msg = NULL; + taskCB->stackPointer = HalTskStackInit(taskCB->taskID, taskInitParam->uwStackSize, topOfStack); SET_SORTLIST_VALUE(&taskCB->sortList, OS_SORT_LINK_INVALID_TIME); return LOS_OK; } @@ -920,7 +920,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 LOS_TaskDelete(UINT32 taskID) // Ignore the return code when matching CSEC rule 6.6(4). (VOID)memset_s((VOID *)&g_cpup[taskCB->taskID], sizeof(OsCpupCB), 0, sizeof(OsCpupCB)); #endif - if (taskCB->taskStatus & OS_TASK_STATUS_RUNNING) { + if (taskCB->taskStatus & OS_TASK_STATUS_RUNNING) { taskCB->taskStatus = OS_TASK_STATUS_UNUSED; OsRunningTaskDelete(taskID, taskCB); LOS_IntRestore(intSave); diff --git a/utils/los_debug.c b/utils/los_debug.c index fbd78865..faac3e21 100644 --- a/utils/los_debug.c +++ b/utils/los_debug.c @@ -31,7 +31,7 @@ #include "los_debug.h" #include "stdarg.h" -#include "los_context.h" +#include "los_interrupt.h" #if (LOSCFG_KERNEL_PRINTF == 1)