From 3e8aea224e481322efef9397e4aafc3450a09d28 Mon Sep 17 00:00:00 2001
From: zff <zhangfanfan2@huawei.com>
Date: Mon, 18 Oct 2021 11:16:19 +0800
Subject: [PATCH] =?UTF-8?q?fix:=20m4=E6=A0=B8=E5=9C=A8=E4=BB=BB=E5=8A=A1?=
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m4核开启浮点运算时，异常处理流程未将浮点压栈，导致异常上下文信息错位，
进而导致backtrace时使用的SP值错误，从而出现backtrace时使用的栈信息不对。

close: #I4D7GE

Signed-off-by: zff <zhangfanfan2@huawei.com>
Change-Id: If7d5198d1f808de4f1cd9c2bc5c6f68185a4ffac
---
 kernel/arch/arm/cortex-m4/gcc/los_dispatch.S |  2 +-
 kernel/arch/arm/cortex-m4/gcc/los_exc.S      | 16 +++++++++-------
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/kernel/arch/arm/cortex-m4/gcc/los_dispatch.S b/kernel/arch/arm/cortex-m4/gcc/los_dispatch.S
index 409b3040..9fb66127 100644
--- a/kernel/arch/arm/cortex-m4/gcc/los_dispatch.S
+++ b/kernel/arch/arm/cortex-m4/gcc/los_dispatch.S
@@ -30,7 +30,7 @@
  */
 .syntax unified
 .arch armv7e-m
-.fpu fpv5-d16
+.fpu fpv4-sp-d16
 .thumb
 
 .equ    OS_FPU_CPACR,                0xE000ED88
diff --git a/kernel/arch/arm/cortex-m4/gcc/los_exc.S b/kernel/arch/arm/cortex-m4/gcc/los_exc.S
index 6b0e0973..d7991ebc 100644
--- a/kernel/arch/arm/cortex-m4/gcc/los_exc.S
+++ b/kernel/arch/arm/cortex-m4/gcc/los_exc.S
@@ -29,9 +29,10 @@
  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
- .syntax unified
- .arch armv7e-m
- .thumb
+.syntax unified
+.arch armv7e-m
+.fpu fpv4-sp-d16
+.thumb
 .section .text
 
 
@@ -281,7 +282,7 @@ _ExcInMSP:
     PUSH  {R3}
     MRS   R12, PRIMASK                  // store message-->exc: disable int?
     PUSH {R4-R12}                       // store message-->exc: {R4-R12}
-    #VPUSH {D8-D15}                     // FPU
+    VPUSH {D8-D15}                      // FPU
     B     _handleEntry
   .fnend
 
@@ -337,12 +338,13 @@ _hwiActiveCheckNext:
 
     MRS   R12, PRIMASK
     PUSH {R4-R12}
+    VPUSH {D8-D15}                      // FPU
 
     // copy auto saved task register
 
-    LDMFD R3!, {R4-R11}                  // R4-R11 store PSP reg(auto push when exc in task)
-    #VLDMIA  R3!, {D8-D15}               // FPU
-    #VSTMDB  R2!, {D8-D15}               // FPU
+    LDMFD R3!, {R4-R11}                 // R4-R11 store PSP reg(auto push when exc in task)
+    VLDMIA  R3!, {D8-D15}               // FPU
+    VSTMDB  R2!, {D8-D15}               // FPU
     STMFD R2!, {R4-R11}
     B     _handleEntry
   .fnend