From 02ac3ade30c574b4216e4ddb636b6286be34d305 Mon Sep 17 00:00:00 2001 From: rtos-lover Date: Sat, 8 May 2021 10:00:57 +0800 Subject: [PATCH] fix:correct spelling corrent those typos in log_debug.h los_exc.S close https://gitee.com/openharmony/kernel_liteos_m/issues/I3PVZV --- kernel/arch/arm/cortex-m3/keil/los_exc.S | 4 +-- kernel/arch/arm/cortex-m33/gcc/los_exc.S | 4 +-- kernel/arch/arm/cortex-m4/gcc/los_exc.S | 4 +-- kernel/arch/arm/cortex-m4/iar/los_exc.S | 4 +-- kernel/arch/arm/cortex-m7/gcc/los_exc.S | 4 +-- kernel/arch/arm/cortex-m7/iar/los_exc.S | 4 +-- .../Common/Source/GCC/startup_demosoc.S | 4 +-- .../Common/Source/GCC/startup_gd32vf103.S | 4 +-- utils/los_debug.h | 32 +++++++++---------- 9 files changed, 32 insertions(+), 32 deletions(-) diff --git a/kernel/arch/arm/cortex-m3/keil/los_exc.S b/kernel/arch/arm/cortex-m3/keil/los_exc.S index 2da36fb4..96f338db 100644 --- a/kernel/arch/arm/cortex-m3/keil/los_exc.S +++ b/kernel/arch/arm/cortex-m3/keil/los_exc.S @@ -56,8 +56,8 @@ FLAG_ADDR_VALID EQU 0x10000 FLAG_HWI_ACTIVE EQU 0x20000 FLAG_NO_FLOAT EQU 0x10000000 -OS_NVIC_FSR EQU 0xE000ED28 ;include BusFault/MemFault/UsageFault State Regeister -OS_NVIC_HFSR EQU 0xE000ED2C ;HardFault State Regeister +OS_NVIC_FSR EQU 0xE000ED28 ;include BusFault/MemFault/UsageFault State Register +OS_NVIC_HFSR EQU 0xE000ED2C ;HardFault State Register OS_NVIC_BFAR EQU 0xE000ED38 OS_NVIC_MMAR EQU 0xE000ED34 OS_NVIC_ACT_BASE EQU 0xE000E300 diff --git a/kernel/arch/arm/cortex-m33/gcc/los_exc.S b/kernel/arch/arm/cortex-m33/gcc/los_exc.S index 16116b09..af0753ab 100644 --- a/kernel/arch/arm/cortex-m33/gcc/los_exc.S +++ b/kernel/arch/arm/cortex-m33/gcc/los_exc.S @@ -59,8 +59,8 @@ .equ FLAG_HWI_ACTIVE, 0x20000 .equ FLAG_NO_FLOAT, 0x10000000 -.equ OS_NVIC_FSR , 0xE000ED28 //include BusFault/MemFault/UsageFault State Regeister -.equ OS_NVIC_HFSR , 0xE000ED2C //HardFault State Regeister +.equ OS_NVIC_FSR , 0xE000ED28 //include BusFault/MemFault/UsageFault State Register +.equ OS_NVIC_HFSR , 0xE000ED2C //HardFault State Register .equ OS_NVIC_BFAR , 0xE000ED38 .equ OS_NVIC_MMAR , 0xE000ED34 .equ OS_NVIC_ACT_BASE , 0xE000E300 diff --git a/kernel/arch/arm/cortex-m4/gcc/los_exc.S b/kernel/arch/arm/cortex-m4/gcc/los_exc.S index 5de06ad5..cfdf0fac 100644 --- a/kernel/arch/arm/cortex-m4/gcc/los_exc.S +++ b/kernel/arch/arm/cortex-m4/gcc/los_exc.S @@ -58,8 +58,8 @@ .equ FLAG_HWI_ACTIVE, 0x20000 .equ FLAG_NO_FLOAT, 0x10000000 -.equ OS_NVIC_FSR , 0xE000ED28 //include BusFault/MemFault/UsageFault State Regeister -.equ OS_NVIC_HFSR , 0xE000ED2C //HardFault State Regeister +.equ OS_NVIC_FSR , 0xE000ED28 //include BusFault/MemFault/UsageFault State Register +.equ OS_NVIC_HFSR , 0xE000ED2C //HardFault State Register .equ OS_NVIC_BFAR , 0xE000ED38 .equ OS_NVIC_MMAR , 0xE000ED34 .equ OS_NVIC_ACT_BASE , 0xE000E300 diff --git a/kernel/arch/arm/cortex-m4/iar/los_exc.S b/kernel/arch/arm/cortex-m4/iar/los_exc.S index b28b112a..7c26aba9 100644 --- a/kernel/arch/arm/cortex-m4/iar/los_exc.S +++ b/kernel/arch/arm/cortex-m4/iar/los_exc.S @@ -56,8 +56,8 @@ FLAG_ADDR_VALID EQU 0x10000 FLAG_HWI_ACTIVE EQU 0x20000 FLAG_NO_FLOAT EQU 0x10000000 -OS_NVIC_FSR EQU 0xE000ED28 ;include BusFault/MemFault/UsageFault State Regeister -OS_NVIC_HFSR EQU 0xE000ED2C ;HardFault State Regeister +OS_NVIC_FSR EQU 0xE000ED28 ;include BusFault/MemFault/UsageFault State Register +OS_NVIC_HFSR EQU 0xE000ED2C ;HardFault State Register OS_NVIC_BFAR EQU 0xE000ED38 OS_NVIC_MMAR EQU 0xE000ED34 OS_NVIC_ACT_BASE EQU 0xE000E300 diff --git a/kernel/arch/arm/cortex-m7/gcc/los_exc.S b/kernel/arch/arm/cortex-m7/gcc/los_exc.S index 927ed35e..bef3bc89 100644 --- a/kernel/arch/arm/cortex-m7/gcc/los_exc.S +++ b/kernel/arch/arm/cortex-m7/gcc/los_exc.S @@ -59,8 +59,8 @@ .equ FLAG_HWI_ACTIVE, 0x20000 .equ FLAG_NO_FLOAT, 0x10000000 -.equ OS_NVIC_FSR , 0xE000ED28 //include BusFault/MemFault/UsageFault State Regeister -.equ OS_NVIC_HFSR , 0xE000ED2C //HardFault State Regeister +.equ OS_NVIC_FSR , 0xE000ED28 //include BusFault/MemFault/UsageFault State Register +.equ OS_NVIC_HFSR , 0xE000ED2C //HardFault State Register .equ OS_NVIC_BFAR , 0xE000ED38 .equ OS_NVIC_MMAR , 0xE000ED34 .equ OS_NVIC_ACT_BASE , 0xE000E300 diff --git a/kernel/arch/arm/cortex-m7/iar/los_exc.S b/kernel/arch/arm/cortex-m7/iar/los_exc.S index 59d7dd57..f1efbf3c 100644 --- a/kernel/arch/arm/cortex-m7/iar/los_exc.S +++ b/kernel/arch/arm/cortex-m7/iar/los_exc.S @@ -56,8 +56,8 @@ FLAG_ADDR_VALID EQU 0x10000 FLAG_HWI_ACTIVE EQU 0x20000 FLAG_NO_FLOAT EQU 0x10000000 -OS_NVIC_FSR EQU 0xE000ED28 ;include BusFault/MemFault/UsageFault State Regeister -OS_NVIC_HFSR EQU 0xE000ED2C ;HardFault State Regeister +OS_NVIC_FSR EQU 0xE000ED28 ;include BusFault/MemFault/UsageFault State Register +OS_NVIC_HFSR EQU 0xE000ED2C ;HardFault State Register OS_NVIC_BFAR EQU 0xE000ED38 OS_NVIC_MMAR EQU 0xE000ED34 OS_NVIC_ACT_BASE EQU 0xE000E300 diff --git a/targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/GCC/startup_demosoc.S b/targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/GCC/startup_demosoc.S index d508a408..d3240b11 100644 --- a/targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/GCC/startup_demosoc.S +++ b/targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/GCC/startup_demosoc.S @@ -191,7 +191,7 @@ _start: csrs CSR_MMISC_CTL, t0 /* - * Intialize ECLIC vector interrupt + * Initialize ECLIC vector interrupt * base address mtvt to vector_base */ la t0, vector_base @@ -200,7 +200,7 @@ _start: /* * Set ECLIC non-vector entry to be controlled * by mtvt2 CSR register. - * Intialize ECLIC non-vector interrupt + * Initialize ECLIC non-vector interrupt * base address mtvt2 to irq_entry. */ la t0, irq_entry diff --git a/targets/riscv_nuclei_gd32vf103_soc_gcc/SoC/gd32vf103/Common/Source/GCC/startup_gd32vf103.S b/targets/riscv_nuclei_gd32vf103_soc_gcc/SoC/gd32vf103/Common/Source/GCC/startup_gd32vf103.S index eab20897..823ba687 100644 --- a/targets/riscv_nuclei_gd32vf103_soc_gcc/SoC/gd32vf103/Common/Source/GCC/startup_gd32vf103.S +++ b/targets/riscv_nuclei_gd32vf103_soc_gcc/SoC/gd32vf103/Common/Source/GCC/startup_gd32vf103.S @@ -255,7 +255,7 @@ _start0800: csrs CSR_MMISC_CTL, t0 /* - * Intialize ECLIC vector interrupt + * Initialize ECLIC vector interrupt * base address mtvt to vector_base */ la t0, vector_base @@ -264,7 +264,7 @@ _start0800: /* * Set ECLIC non-vector entry to be controlled * by mtvt2 CSR register. - * Intialize ECLIC non-vector interrupt + * Initialize ECLIC non-vector interrupt * base address mtvt2 to irq_entry. */ la t0, irq_entry diff --git a/utils/los_debug.h b/utils/los_debug.h index 55287633..cd061554 100644 --- a/utils/los_debug.h +++ b/utils/los_debug.h @@ -185,7 +185,7 @@ extern VOID OsBackTraceHookCall(UINTPTR *LR, UINT32 LRSize, UINT32 jumpCount, UI * * Value: 0x02001401 * - * Solution: Use valid type to regeister the new trace. + * Solution: Use valid type to register the new trace. */ #define LOS_ERRNO_TRACE_TYPE_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_TRACE, 0x01) @@ -196,7 +196,7 @@ extern VOID OsBackTraceHookCall(UINTPTR *LR, UINT32 LRSize, UINT32 jumpCount, UI * * Value: 0x02001402 * - * Solution: Use valid callback function to regeister the new trace. + * Solution: Use valid callback function to register the new trace. */ #define LOS_ERRNO_TRACE_FUNCTION_NULL LOS_ERRNO_OS_ERROR(LOS_MOD_TRACE, 0x02) @@ -206,7 +206,7 @@ extern VOID OsBackTraceHookCall(UINTPTR *LR, UINT32 LRSize, UINT32 jumpCount, UI * * Value: 0x02001403 * - * Solution: Use valid filled size to regeister the new trace. + * Solution: Use valid filled size to register the new trace. */ #define LOS_ERRNO_TRACE_MAX_SIZE_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_TRACE, 0x03) @@ -218,7 +218,7 @@ extern VOID OsBackTraceHookCall(UINTPTR *LR, UINT32 LRSize, UINT32 jumpCount, UI /** * @ingroup los_trace - * It's the legth of tag, filled by los_trace system + * It's the length of tag, filled by los_trace system */ #define LOS_TRACE_TAG_LENGTH sizeof(UINT32) @@ -228,7 +228,7 @@ extern VOID OsBackTraceHookCall(UINTPTR *LR, UINT32 LRSize, UINT32 jumpCount, UI */ typedef enum enTraceType { LOS_TRACE_SWITCH = 0, /**< trace for task switch, 0 is reserved for taskswitch */ - LOS_TRACE_INTERRUPT = 1, /**< trace for Interrrupt, 1 is reserved for interrupt */ + LOS_TRACE_INTERRUPT = 1, /**< trace for Interrupt, 1 is reserved for interrupt */ LOS_TRACE_TYPE_NUM = 10, /**< num for the register type, user can use 2~ LOS_TRACE_TYPE_NUM-1 */ } TRACE_TYPE_E; @@ -238,8 +238,8 @@ typedef enum enTraceType { * struct to store the task switch infomation */ typedef struct tagTraceTaskSwitch { - UINT8 ucSrcTaskId; /**< source taskid */ - UINT8 ucDestTaskId; /**< destination taskid */ + UINT8 ucSrcTaskId; /**< source taskId */ + UINT8 ucDestTaskId; /**< destination taskId */ UINT32 uwSwitchTick; /**< Time at which the task switch happens */ } TRACE_TASKSWITCH_S; @@ -261,13 +261,13 @@ typedef struct tagTraceInterrupt { typedef struct tagTrace { union { TRACE_TASKSWITCH_S stTraceTask; /**< It used for trace the task */ - TRACE_INTERRUPT_S stTraceInterrupt; /**< It used for trace the interrrupt */ + TRACE_INTERRUPT_S stTraceInterrupt; /**< It used for trace the interrupt */ }; } TRACE_S; /** * @ingroup los_trace - * Main struct to store the interrupt and task swithc infomation + * Main struct to store the interrupt and task switch infomation */ typedef struct tagTraceBuffer { UINT16 usTracePos; @@ -278,7 +278,7 @@ typedef struct tagTraceBuffer { /** * @ingroup los_trace - * Struct to store the trace infomaion for each trace type + * Struct to store the trace information for each trace type */ typedef struct tagTraceInfo { TRACE_TYPE_E eType; /**< trace type, selected from TRACE_TYPE_E */ @@ -289,10 +289,10 @@ typedef struct tagTraceInfo { /** * @ingroup los_trace - * @brief Intialize the trace when the system startup. + * @brief Initialize the trace when the system startup. * * @par Description: - * This API is used to intilize the trace for system level. + * This API is used to initialize the trace for system level. * @attention *