Caoruihong
102 lines
3.7 KiB
C
102 lines
3.7 KiB
C
/*
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* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
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* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this list of
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* conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice, this list
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* of conditions and the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARCH_CONFIG_H
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#define _ARCH_CONFIG_H
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#define CPSR_INT_DISABLE 0xC0 /* Disable both FIQ and IRQ */
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#define CPSR_IRQ_DISABLE 0x80 /* IRQ disabled when =1 */
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#define CPSR_FIQ_DISABLE 0x40 /* FIQ disabled when =1 */
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#define CPSR_THUMB_ENABLE 0x20 /* Thumb mode when =1 */
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#define CPSR_USER_MODE 0x10
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#define CPSR_FIQ_MODE 0x11
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#define CPSR_IRQ_MODE 0x12
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#define CPSR_SVC_MODE 0x13
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#define CPSR_ABT_MODE 0x17
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#define CPSR_UNDEF_MODE 0x1B
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#define CPSR_MASK_MODE 0x1F
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/* Define exception type ID */
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#define OS_EXCEPT_RESET 0x00
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#define OS_EXCEPT_UNDEF_INSTR 0x01
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#define OS_EXCEPT_SWI 0x02
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#define OS_EXCEPT_PREFETCH_ABORT 0x03
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#define OS_EXCEPT_DATA_ABORT 0x04
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#define OS_EXCEPT_FIQ 0x05
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#define OS_EXCEPT_ADDR_ABORT 0x06
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#define OS_EXCEPT_IRQ 0x07
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/* Define core num */
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#ifdef LOSCFG_KERNEL_SMP
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#define CORE_NUM LOSCFG_KERNEL_SMP_CORE_NUM
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#else
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#define CORE_NUM 1
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#endif
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/* Initial bit32 stack value. */
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#define OS_STACK_INIT 0xCACACACA
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/* Bit32 stack top magic number. */
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#define OS_STACK_MAGIC_WORD 0xCCCCCCCC
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#ifdef LOSCFG_GDB
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#define OS_EXC_UNDEF_STACK_SIZE 512
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#define OS_EXC_ABT_STACK_SIZE 512
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#else
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#define OS_EXC_UNDEF_STACK_SIZE 40
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#define OS_EXC_ABT_STACK_SIZE 40
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#endif
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#define OS_EXC_FIQ_STACK_SIZE 64
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#define OS_EXC_IRQ_STACK_SIZE 64
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#define OS_EXC_SVC_STACK_SIZE 0x2000
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#define OS_EXC_STACK_SIZE 0x1000
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#define REG_R0 0
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#define REG_R1 1
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#define REG_R2 2
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#define REG_R3 3
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#define REG_R4 4
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#define REG_R5 5
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#define REG_R6 6
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#define REG_R7 7
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#define REG_R8 8
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#define REG_R9 9
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#define REG_R10 10
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#define REG_R11 11
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#define REG_R12 12
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#define REG_R13 13
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#define REG_R14 14
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#define REG_R15 15
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#define REG_CPSR 16
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#define REG_SP REG_R13
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#define REG_LR REG_R14
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#define REG_PC REG_R15
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#endif |