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add OpenHarmony 1.0 baseline

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This commit is contained in:
wenjun
2020-09-08 10:21:39 +08:00
parent 94f5f466b4
commit 6df931fc98
736 changed files with 111817 additions and 0 deletions
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49
platform/Kconfig Executable file
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config PLATFORM
string
default "hi3516dv300" if PLATFORM_HI3516DV300
default "hi3518ev300" if PLATFORM_HI3518EV300
choice
prompt "Board"
default PLATFORM_HI3516DV300
help
IPC has several chips:
hi3516dv300
hi3518ev300
config PLATFORM_HI3516DV300
bool "hi3516dv300"
select ARCH_CORTEX_A7
config PLATFORM_HI3518EV300
bool "hi3518ev300"
select ARCH_CORTEX_A7
endchoice
config TEE_ENABLE
bool "ENABLE TEE"
default n
depends on PLATFORM_HI3516DV300
help
ENABLE teeos in platform
choice
prompt "IRQCHIP"
default PLATFORM_BSP_GIC_V2
help
Interrupt Controller.
config PLATFORM_BSP_GIC_V2
bool "GIC Version 2"
help
This GIC(General Interrupt Controller) version 2 driver is compatatble with
GIC version 1 and version 2.
config PLATFORM_BSP_GIC_V3
bool "GIC Version 3"
depends on ARCH_ARM_V8A || ARCH_ARM_V8R
help
General Interrupt Controller version 3.
endchoice

81
platform/Makefile Executable file
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# Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
# Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without modification,
# are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice, this list of
# conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice, this list
# of conditions and the following disclaimer in the documentation and/or other materials
# provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its contributors may be used
# to endorse or promote products derived from this software without specific prior written
# permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
include $(LITEOSTOPDIR)/config.mk
MODULE_NAME := bsp
LOCAL_SRCS = $(wildcard $(HWI_SRC)/*.c) \
$(wildcard $(TIMER_SRC)/*.c) \
$(wildcard $(HRTIMER_SRC)/*.c) \
$(wildcard $(UART_SRC)/*.c) \
$(wildcard ./main.c)
LOCAL_INCLUDE += -I $(LITEOSTOPDIR)/compat/posix/src \
-I $(LITEOSTOPDIR)/bsd/dev/random
ifeq ($(findstring y, $(LOSCFG_PLATFORM_HI3518EV300)$(LOSCFG_PLATFORM_HI3516DV300)), y)
LOCAL_SRCS += $(wildcard ../kernel/common/*.c)
LOCAL_SRCS := $(filter-out ../kernel/common/los_rootfs.c, $(LOCAL_SRCS))
ifneq ($(LOSCFG_FS_VFS), y)
LOCAL_SRCS := $(filter-out ../kernel/common/console.c ../kernel/common/virtual_serial.c, $(LOCAL_SRCS))
endif
else
LOCAL_SRCS += $(wildcard ../kernel/common/los_config.c)
LOCAL_SRCS += $(wildcard ../kernel/common/los_printf.c)
endif
ifeq ($(LOSCFG_DRIVERS_USB), y)
LOCAL_SRCS += $(wildcard $(USB_SRC)/*.c)
endif
ifeq ($(LOSCFG_KERNEL_TICKLESS), y)
LOCAL_INCLUDE += -I $(LITEOSTOPDIR)/kernel/extended/include
endif
ifeq ($(LOSCFG_KERNEL_TRACE), y)
LOCAL_INCLUDE += -I $(LITEOSTOPDIR)/kernel/extended/include
endif
ifeq ($(LOSCFG_KERNEL_CPUP), y)
LOCAL_INCLUDE += -I $(LITEOSTOPDIR)/kernel/extended/include
endif
ifeq ($(LOSCFG_KERNEL_VDSO), y)
LOCAL_INCLUDE += -I $(LITEOSTOPDIR)/kernel/extended/vdso/include
endif
ALL_ASSRCS := $(wildcard *.S)
ASSRCS := $(subst board.ld.S,,$(ALL_ASSRCS))
LOCAL_SRCS += $(ASSRCS)
LOCAL_FLAGS := $(LOCAL_INCLUDE) $(LITEOS_GCOV_OPTS)
include $(MODULE)

56
platform/board.ld.S Executable file
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/*
* Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "include/board.h"
#define TEXT_BASE KERNEL_VADDR_BASE
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
MEMORY
{
ram : ORIGIN = KERNEL_VADDR_BASE, LENGTH = KERNEL_VADDR_SIZE
sram : ORIGIN = 0x40000000, LENGTH = 0x1000
user_ram : ORIGIN = 0x1000000, LENGTH = 0x100000
}
SECTIONS
{
/DISCARD/ : { *(.comment .note) }
.ram_vectors TEXT_BASE : {
__ram_vectors_vma = .;
KEEP (*(.vectors))
} > ram
__ram_vectors_lma = LOADADDR(.ram_vectors);
}
USER_INIT_VM_START = 0x1000000;

90
platform/bsp.mk Executable file
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# Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
# Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without modification,
# are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice, this list of
# conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice, this list
# of conditions and the following disclaimer in the documentation and/or other materials
# provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its contributors may be used
# to endorse or promote products derived from this software without specific prior written
# permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
############################# SRCs #################################
HWI_SRC :=
MMU_SRC :=
NET_SRC :=
TIMER_SRC :=
HRTIMER_SRC :=
UART_SRC :=
USB_SRC :=
############################# HI3516DV300 Options#################################
ifeq ($(LOSCFG_PLATFORM_HI3516DV300), y)
HWI_TYPE := arm/interrupt/gic
TIMER_TYPE := arm/timer/arm_generic
HRTIMER_TYPE := hisoc/hrtimer
NET_TYPE := hieth
UART_TYPE := amba_pl011
USB_TYPE := usb3.0_hi3516dv300
LITEOS_CMACRO_TEST += -DTEST3516DV300
########################## HI3518EV300 Options##############################
else ifeq ($(LOSCFG_PLATFORM_HI3518EV300), y)
HWI_TYPE := arm/interrupt/gic
TIMER_TYPE := hisoc/timer
HRTIMER_TYPE := hisoc/hrtimer
NET_TYPE := hieth
UART_TYPE := amba_pl011
USB_TYPE := usb3.0_hi3518ev300
LITEOS_CMACRO_TEST += -DTEST3518EV300
endif
HWI_SRC := hw/$(HWI_TYPE)
TIMER_SRC := hw/$(TIMER_TYPE)
HRTIMER_SRC := hw/$(HRTIMER_TYPE)
NET_SRC := net/$(NET_TYPE)
UART_SRC := uart/$(UART_TYPE)
USB_SRC := usb/$(USB_TYPE)
LITEOS_BASELIB += -lbsp
LITEOS_PLATFORM := $(subst $\",,$(LOSCFG_PLATFORM))
PLATFORM_BSP_HISI_BASE := $(LITEOSTOPDIR)/platform
PLATFORM_INCLUDE := -I $(LITEOSTOPDIR)/../../vendor/hisi/hi35xx/$(LITEOS_PLATFORM)/config/board/include \
-I $(PLATFORM_BSP_HISI_BASE)/../kernel/common \
-I $(PLATFORM_BSP_HISI_BASE)/../../../drivers/liteos/platform/pm \
-I $(PLATFORM_BSP_HISI_BASE)/hw/include \
-I $(PLATFORM_BSP_HISI_BASE)/include \
-I $(PLATFORM_BSP_HISI_BASE)/$(UART_SRC)
ifeq ($(findstring y, $(LOSCFG_PLATFORM_HI3518EV300)$(LOSCFG_PLATFORM_HI3516DV300)), y)
PLATFORM_INCLUDE += -I $(LITEOSTOPDIR)/../../vendor/hisi/hi35xx/$(LITEOS_PLATFORM)/config/board/include/hisoc
endif
#
#-include $(LITEOSTOPDIR)/platform/bsp/board/$(LITEOS_PLATFORM)/board.mk
#
LIB_SUBDIRS += $(PLATFORM_BSP_HISI_BASE)
LITEOS_PLATFORM_INCLUDE += $(PLATFORM_INCLUDE)
LITEOS_CXXINCLUDE += $(PLATFORM_INCLUDE)

193
platform/hw/arm/interrupt/gic/gic_v2.c Executable file
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/*
* Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "gic_common.h"
#include "los_hwi_pri.h"
#include "los_mp.h"
STATIC_ASSERT(OS_USER_HWI_MAX <= 1020, "hwi max is too large!");
#ifdef LOSCFG_PLATFORM_BSP_GIC_V2
STATIC UINT32 g_curIrqNum = 0;
#if (LOSCFG_KERNEL_SMP == YES)
/*
* filter description
* 0b00: forward to the cpu interfaces specified in cpu_mask
* 0b01: forward to all cpu interfaces
* 0b10: forward only to the cpu interface that request the irq
*/
STATIC VOID GicWriteSgi(UINT32 vector, UINT32 cpuMask, UINT32 filter)
{
UINT32 val = ((filter & 0x3) << 24) | ((cpuMask & 0xFF) << 16) |
(vector & 0xF);
GIC_REG_32(GICD_SGIR) = val;
}
VOID HalIrqSendIpi(UINT32 target, UINT32 ipi)
{
GicWriteSgi(ipi, target, 0);
}
VOID HalIrqSetAffinity(UINT32 vector, UINT32 cpuMask)
{
UINT32 offset = vector / 4;
UINT32 index = vector & 0x3;
GIC_REG_8(GICD_ITARGETSR(offset) + index) = cpuMask;
}
#endif
UINT32 HalCurIrqGet(VOID)
{
return g_curIrqNum;
}
VOID HalIrqMask(UINT32 vector)
{
if ((vector > OS_USER_HWI_MAX) || (vector < OS_USER_HWI_MIN)) {
return;
}
GIC_REG_32(GICD_ICENABLER(vector / 32)) = 1U << (vector % 32);
}
VOID HalIrqUnmask(UINT32 vector)
{
if ((vector > OS_USER_HWI_MAX) || (vector < OS_USER_HWI_MIN)) {
return;
}
GIC_REG_32(GICD_ISENABLER(vector >> 5)) = 1U << (vector % 32);
}
VOID HalIrqPending(UINT32 vector)
{
if ((vector > OS_USER_HWI_MAX) || (vector < OS_USER_HWI_MIN)) {
return;
}
GIC_REG_32(GICD_ISPENDR(vector >> 5)) = 1U << (vector % 32);
}
VOID HalIrqClear(UINT32 vector)
{
GIC_REG_32(GICC_EOIR) = vector;
}
VOID HalIrqInitPercpu(VOID)
{
/* unmask interrupts */
GIC_REG_32(GICC_PMR) = 0xFF;
/* enable gic cpu interface */
GIC_REG_32(GICC_CTLR) = 1;
}
VOID HalIrqInit(VOID)
{
UINT32 i;
/* set externel interrupts to be level triggered, active low. */
for (i = 32; i < OS_HWI_MAX_NUM; i += 16) {
GIC_REG_32(GICD_ICFGR(i / 16)) = 0;
}
/* set externel interrupts to CPU 0 */
for (i = 32; i < OS_HWI_MAX_NUM; i += 4) {
GIC_REG_32(GICD_ITARGETSR(i / 4)) = 0x01010101;
}
/* set priority on all interrupts */
for (i = 0; i < OS_HWI_MAX_NUM; i += 4) {
GIC_REG_32(GICD_IPRIORITYR(i / 4)) = GICD_INT_DEF_PRI_X4;
}
/* disable all interrupts. */
for (i = 0; i < OS_HWI_MAX_NUM; i += 32) {
GIC_REG_32(GICD_ICENABLER(i / 32)) = ~0;
}
HalIrqInitPercpu();
/* enable gic distributor control */
GIC_REG_32(GICD_CTLR) = 1;
#if (LOSCFG_KERNEL_SMP == YES)
/* register inter-processor interrupt */
(VOID)LOS_HwiCreate(LOS_MP_IPI_WAKEUP, 0xa0, 0, OsMpWakeHandler, 0);
(VOID)LOS_HwiCreate(LOS_MP_IPI_SCHEDULE, 0xa0, 0, OsMpScheduleHandler, 0);
(VOID)LOS_HwiCreate(LOS_MP_IPI_HALT, 0xa0, 0, OsMpHaltHandler, 0);
#endif
}
VOID HalIrqHandler(VOID)
{
UINT32 iar = GIC_REG_32(GICC_IAR);
UINT32 vector = iar & 0x3FFU;
/*
* invalid irq number, mainly the spurious interrupts 0x3ff,
* gicv2 valid irq ranges from 0~1019, we use OS_HWI_MAX_NUM
* to do the checking.
*/
if (vector >= OS_HWI_MAX_NUM) {
return;
}
g_curIrqNum = vector;
OsInterrupt(vector);
/* use orignal iar to do the EOI */
GIC_REG_32(GICC_EOIR) = iar;
}
CHAR *HalIrqVersion(VOID)
{
UINT32 pidr = GIC_REG_32(GICD_PIDR2V2);
CHAR *irqVerString = NULL;
switch (pidr >> GIC_REV_OFFSET) {
case GICV1:
irqVerString = "GICv1";
break;
case GICV2:
irqVerString = "GICv2";
break;
default:
irqVerString = "unknown";
}
return irqVerString;
}
#endif

446
platform/hw/arm/interrupt/gic/gic_v3.c Executable file
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/*
* Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "gic_common.h"
#include "gic_v3.h"
#include "los_typedef.h"
#include "los_hwi_pri.h"
#include "los_mp.h"
#ifdef LOSCFG_PLATFORM_BSP_GIC_V3
STATIC UINT32 g_curIrqNum = 0;
STATIC INLINE UINT64 MpidrToAffinity(UINT64 mpidr)
{
return ((MPIDR_AFF_LEVEL(mpidr, 3) << 32) |
(MPIDR_AFF_LEVEL(mpidr, 2) << 16) |
(MPIDR_AFF_LEVEL(mpidr, 1) << 8) |
(MPIDR_AFF_LEVEL(mpidr, 0)));
}
#if (LOSCFG_KERNEL_SMP == YES)
STATIC UINT32 NextCpu(UINT32 cpu, UINT32 cpuMask)
{
UINT32 next = cpu + 1;
while (next < LOSCFG_KERNEL_CORE_NUM) {
if (cpuMask & (1U << next)) {
goto OUT;
}
next++;
}
OUT:
return next;
}
STATIC UINT16 GicTargetList(UINT32 *base, UINT32 cpuMask, UINT64 cluster)
{
UINT32 nextCpu;
UINT16 tList = 0;
UINT32 cpu = *base;
UINT64 mpidr = CPU_MAP_GET(cpu);
while (cpu < LOSCFG_KERNEL_CORE_NUM) {
tList |= 1U << (mpidr & 0xf);
nextCpu = NextCpu(cpu, cpuMask);
if (nextCpu >= LOSCFG_KERNEL_CORE_NUM) {
goto out;
}
cpu = nextCpu;
mpidr = CPU_MAP_GET(cpu);
if (cluster != (mpidr & ~0xffUL)) {
cpu--;
goto out;
}
}
out:
*base = cpu;
return tList;
}
STATIC VOID GicSgi(UINT32 irq, UINT32 cpuMask)
{
UINT16 tList;
UINT32 cpu = 0;
UINT64 val, cluster;
while (cpuMask && (cpu < LOSCFG_KERNEL_CORE_NUM)) {
if (cpuMask & (1U << cpu)) {
cluster = CPU_MAP_GET(cpu) & ~0xffUL;
tList = GicTargetList(&cpu, cpuMask, cluster);
/* Generates a Group 1 interrupt for the current security state */
val = ((MPIDR_AFF_LEVEL(cluster, 3) << 48) |
(MPIDR_AFF_LEVEL(cluster, 2) << 32) |
(MPIDR_AFF_LEVEL(cluster, 1) << 16) |
(irq << 24) | tList);
GiccSetSgi1r(val);
}
cpu++;
}
}
VOID HalIrqSendIpi(UINT32 target, UINT32 ipi)
{
GicSgi(ipi, target);
}
VOID HalIrqSetAffinity(UINT32 irq, UINT32 cpuMask)
{
UINT64 affinity = MpidrToAffinity(NextCpu(0, cpuMask));
/* When ARE is on, use router */
GIC_REG_64(GICD_IROUTER(irq)) = affinity;
}
#endif
STATIC VOID GicWaitForRwp(UINT64 reg)
{
INT32 count = 1000000; /* 1s */
while (GIC_REG_32(reg) & GICD_CTLR_RWP) {
count -= 1;
if (!count) {
PRINTK("gic_v3: rwp timeout 0x%x\n", GIC_REG_32(reg));
return;
}
}
}
STATIC INLINE VOID GicdSetGroup(UINT32 irq)
{
/* configure spi as group 0 on secure mode and group 1 on unsecure mode */
#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
GIC_REG_32(GICD_IGROUPR(irq / 32)) = 0;
#else
GIC_REG_32(GICD_IGROUPR(irq / 32)) = 0xffffffff;
#endif
}
STATIC INLINE VOID GicrSetWaker(UINT32 cpu)
{
GIC_REG_32(GICR_WAKER(cpu)) &= ~GICR_WAKER_PROCESSORSLEEP;
DSB;
ISB;
while ((GIC_REG_32(GICR_WAKER(cpu)) & 0x4) == GICR_WAKER_CHILDRENASLEEP);
}
STATIC INLINE VOID GicrSetGroup(UINT32 cpu)
{
/* configure sgi/ppi as group 0 on secure mode and group 1 on unsecure mode */
#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
GIC_REG_32(GICR_IGROUPR0(cpu)) = 0;
GIC_REG_32(GICR_IGRPMOD0(cpu)) = 0;
#else
GIC_REG_32(GICR_IGROUPR0(cpu)) = 0xffffffff;
#endif
}
STATIC VOID GicdSetPmr(UINT32 irq, UINT8 priority)
{
UINT32 pos = irq >> 2; /* one irq have the 8-bit interrupt priority field */
UINT32 newPri = GIC_REG_32(GICD_IPRIORITYR(pos));
/* Shift and mask the correct bits for the priority */
newPri &= ~(GIC_PRIORITY_MASK << ((irq % 4) * GIC_PRIORITY_OFFSET));
newPri |= priority << ((irq % 4) * GIC_PRIORITY_OFFSET);
GIC_REG_32(GICD_IPRIORITYR(pos)) = newPri;
}
STATIC VOID GicrSetPmr(UINT32 irq, UINT8 priority)
{
UINT32 cpu = ArchCurrCpuid();
UINT32 pos = irq >> 2; /* one irq have the 8-bit interrupt priority field */
UINT32 newPri = GIC_REG_32(GICR_IPRIORITYR0(cpu) + pos * 4);
/* Clear priority offset bits and set new priority */
newPri &= ~(GIC_PRIORITY_MASK << ((irq % 4) * GIC_PRIORITY_OFFSET));
newPri |= priority << ((irq % 4) * GIC_PRIORITY_OFFSET);
GIC_REG_32(GICR_IPRIORITYR0(cpu) + pos * 4) = newPri;
}
STATIC VOID GiccInitPercpu(VOID)
{
/* enable system register interface */
UINT32 sre = GiccGetSre();
if (!(sre & 0x1)) {
GiccSetSre(sre | 0x1);
/*
* Need to check that the SRE bit has actually been set. If
* not, it means that SRE is disabled at up EL level. We're going to
* die painfully, and there is nothing we can do about it.
*/
sre = GiccGetSre();
LOS_ASSERT(sre & 0x1);
}
#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
/* Enable group 0 and disable grp1ns grp1s interrupts */
GiccSetIgrpen0(1);
GiccSetIgrpen1(0);
/*
* For priority grouping.
* The value of this field control show the 8-bit interrupt priority field
* is split into a group priority field, that determines interrupt preemption,
* and a subpriority field.
*/
GiccSetBpr0(MAX_BINARY_POINT_VALUE);
#else
/* enable group 1 interrupts */
GiccSetIgrpen1(1);
#endif
/* set priority threshold to max */
GiccSetPmr(0xff);
/* EOI deactivates interrupt too (mode 0) */
GiccSetCtlr(0);
}
UINT32 HalCurIrqGet(VOID)
{
return g_curIrqNum;
}
VOID HalIrqMask(UINT32 vector)
{
INT32 i;
const UINT32 mask = 1U << (vector % 32);
if ((vector > OS_USER_HWI_MAX) || (vector < OS_USER_HWI_MIN)) {
return;
}
if (vector < 32) {
for (i = 0; i < LOSCFG_KERNEL_CORE_NUM; i++) {
GIC_REG_32(GICR_ICENABLER0(i)) = mask;
GicWaitForRwp(GICR_CTLR(i));
}
} else {
GIC_REG_32(GICD_ICENABLER(vector >> 5)) = mask;
GicWaitForRwp(GICD_CTLR);
}
}
VOID HalIrqUnmask(UINT32 vector)
{
INT32 i;
const UINT32 mask = 1U << (vector % 32);
if ((vector > OS_USER_HWI_MAX) || (vector < OS_USER_HWI_MIN)) {
return;
}
if (vector < 32) {
for (i = 0; i < LOSCFG_KERNEL_CORE_NUM; i++) {
GIC_REG_32(GICR_ISENABLER0(i)) = mask;
GicWaitForRwp(GICR_CTLR(i));
}
} else {
GIC_REG_32(GICD_ISENABLER(vector >> 5)) = mask;
GicWaitForRwp(GICD_CTLR);
}
}
VOID HalIrqPending(UINT32 vector)
{
if ((vector > OS_USER_HWI_MAX) || (vector < OS_USER_HWI_MIN)) {
return;
}
GIC_REG_32(GICD_ISPENDR(vector >> 5)) = 1U << (vector % 32);
}
VOID HalIrqClear(UINT32 vector)
{
GiccSetEoir(vector);
ISB;
}
UINT32 HalIrqSetPrio(UINT32 vector, UINT8 priority)
{
UINT8 prio = priority;
if (vector > OS_HWI_MAX_NUM) {
PRINT_ERR("Invalid irq value %u, max irq is %u\n", vector, OS_HWI_MAX_NUM);
return LOS_NOK;
}
prio = prio & (UINT8)GIC_INTR_PRIO_MASK;
if (vector >= GIC_MIN_SPI_NUM) {
GicdSetPmr(vector, prio);
} else {
GicrSetPmr(vector, prio);
}
return LOS_OK;
}
VOID HalIrqInitPercpu(VOID)
{
INT32 idx;
UINT32 cpu = ArchCurrCpuid();
/* GICR init */
GicrSetWaker(cpu);
GicrSetGroup(cpu);
GicWaitForRwp(GICR_CTLR(cpu));
/* GICR: clear and mask sgi/ppi */
GIC_REG_32(GICR_ICENABLER0(cpu)) = 0xffffffff;
GIC_REG_32(GICR_ICPENDR0(cpu)) = 0xffffffff;
GIC_REG_32(GICR_ISENABLER0(cpu)) = 0xffffffff;
for (idx = 0; idx < GIC_MIN_SPI_NUM; idx += 1) {
GicrSetPmr(idx, MIN_INTERRUPT_PRIORITY);
}
GicWaitForRwp(GICR_CTLR(cpu));
/* GICC init */
GiccInitPercpu();
#ifdef LOSCFG_KERNEL_SMP
/* unmask ipi interrupts */
HalIrqUnmask(LOS_MP_IPI_WAKEUP);
HalIrqUnmask(LOS_MP_IPI_HALT);
#endif
}
VOID HalIrqInit(VOID)
{
UINT32 i;
UINT64 affinity;
/* disable distributor */
GIC_REG_32(GICD_CTLR) = 0;
GicWaitForRwp(GICD_CTLR);
ISB;
/* set externel interrupts to be level triggered, active low. */
for (i = 32; i < OS_HWI_MAX_NUM; i += 16) {
GIC_REG_32(GICD_ICFGR(i / 16)) = 0;
}
/* config distributer, mask and clear all spis, set group x */
for (i = 32; i < OS_HWI_MAX_NUM; i += 32) {
GIC_REG_32(GICD_ICENABLER(i / 32)) = 0xffffffff;
GIC_REG_32(GICD_ICPENDR(i / 32)) = 0xffffffff;
GIC_REG_32(GICD_IGRPMODR(i / 32)) = 0;
GicdSetGroup(i);
}
/* set spi priority as default */
for (i = 32; i < OS_HWI_MAX_NUM; i++) {
GicdSetPmr(i, MIN_INTERRUPT_PRIORITY);
}
GicWaitForRwp(GICD_CTLR);
/* disable all interrupts. */
for (i = 0; i < OS_HWI_MAX_NUM; i += 32) {
GIC_REG_32(GICD_ICENABLER(i / 32)) = 0xffffffff;
}
/* enable distributor with ARE, group 1 enabled */
GIC_REG_32(GICD_CTLR) = CTLR_ENALBE_G0 | CTLR_ENABLE_G1NS | CTLR_ARE_S;
/* set spi to boot cpu only. ARE must be enabled */
affinity = MpidrToAffinity(AARCH64_SYSREG_READ(mpidr_el1));
for (i = 32; i < OS_HWI_MAX_NUM; i++) {
GIC_REG_64(GICD_IROUTER(i)) = affinity;
}
HalIrqInitPercpu();
#if (LOSCFG_KERNEL_SMP == YES)
/* register inter-processor interrupt */
LOS_HwiCreate(LOS_MP_IPI_WAKEUP, 0xa0, 0, OsMpWakeHandler, 0);
LOS_HwiCreate(LOS_MP_IPI_SCHEDULE, 0xa0, 0, OsMpScheduleHandler, 0);
LOS_HwiCreate(LOS_MP_IPI_HALT, 0xa0, 0, OsMpScheduleHandler, 0);
#endif
}
VOID HalIrqHandler(VOID)
{
UINT32 iar = GiccGetIar();
UINT32 vector = iar & 0x3FFU;
/*
* invalid irq number, mainly the spurious interrupts 0x3ff,
* valid irq ranges from 0~1019, we use OS_HWI_MAX_NUM to do
* the checking.
*/
if (vector >= OS_HWI_MAX_NUM) {
return;
}
g_curIrqNum = vector;
OsInterrupt(vector);
GiccSetEoir(vector);
}
CHAR *HalIrqVersion(VOID)
{
UINT32 pidr = GIC_REG_32(GICD_PIDR2V3);
CHAR *irqVerString = NULL;
switch (pidr >> GIC_REV_OFFSET) {
case GICV3:
irqVerString = "GICv3";
break;
case GICV4:
irqVerString = "GICv4";
break;
default:
irqVerString = "unknown";
}
return irqVerString;
}
#endif

199
platform/hw/arm/timer/arm_generic/arm_generic_timer.c Executable file
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/*
* Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_hw_pri.h"
#include "los_tick_pri.h"
#include "los_sys_pri.h"
#include "gic_common.h"
#define STRING_COMB(x, y, z) x ## y ## z
#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
#define TIMER_REG(reg) STRING_COMB(TIMER_REG_, CNTPS, reg)
#else
#define TIMER_REG(reg) STRING_COMB(TIMER_REG_, CNTP, reg)
#endif
#define TIMER_REG_CTL TIMER_REG(_CTL) /* 32 bits */
#define TIMER_REG_TVAL TIMER_REG(_TVAL) /* 32 bits */
#define TIMER_REG_CVAL TIMER_REG(_CVAL) /* 64 bits */
#define TIMER_REG_CT TIMER_REG(CT) /* 64 bits */
#ifdef __LP64__
#define TIMER_REG_CNTFRQ cntfrq_el0
/* CNTP AArch64 registers */
#define TIMER_REG_CNTP_CTL cntp_ctl_el0
#define TIMER_REG_CNTP_TVAL cntp_tval_el0
#define TIMER_REG_CNTP_CVAL cntp_cval_el0
#define TIMER_REG_CNTPCT cntpct_el0
/* CNTPS AArch64 registers */
#define TIMER_REG_CNTPS_CTL cntps_ctl_el1
#define TIMER_REG_CNTPS_TVAL cntps_tval_el1
#define TIMER_REG_CNTPS_CVAL cntps_cval_el1
#define TIMER_REG_CNTPSCT cntpct_el0
#define READ_TIMER_REG32(reg) AARCH64_SYSREG_READ(reg)
#define READ_TIMER_REG64(reg) AARCH64_SYSREG_READ(reg)
#define WRITE_TIMER_REG32(reg, val) AARCH64_SYSREG_WRITE(reg, (UINT64)(val))
#define WRITE_TIMER_REG64(reg, val) AARCH64_SYSREG_WRITE(reg, val)
#else /* Aarch32 */
#define TIMER_REG_CNTFRQ CP15_REG(c14, 0, c0, 0)
/* CNTP AArch32 registers */
#define TIMER_REG_CNTP_CTL CP15_REG(c14, 0, c2, 1)
#define TIMER_REG_CNTP_TVAL CP15_REG(c14, 0, c2, 0)
#define TIMER_REG_CNTP_CVAL CP15_REG64(c14, 2)
#define TIMER_REG_CNTPCT CP15_REG64(c14, 0)
/* CNTPS AArch32 registers are banked and accessed though CNTP */
#define CNTPS CNTP
#define READ_TIMER_REG32(reg) ARM_SYSREG_READ(reg)
#define READ_TIMER_REG64(reg) ARM_SYSREG64_READ(reg)
#define WRITE_TIMER_REG32(reg, val) ARM_SYSREG_WRITE(reg, val)
#define WRITE_TIMER_REG64(reg, val) ARM_SYSREG64_WRITE(reg, val)
#endif
#define OS_CYCLE_PER_TICK (g_sysClock / LOSCFG_BASE_CORE_TICK_PER_SECOND)
UINT32 HalClockFreqRead(VOID)
{
return READ_TIMER_REG32(TIMER_REG_CNTFRQ);
}
VOID HalClockFreqWrite(UINT32 freq)
{
WRITE_TIMER_REG32(TIMER_REG_CNTFRQ, freq);
}
STATIC_INLINE VOID TimerCtlWrite(UINT32 cntpCtl)
{
WRITE_TIMER_REG32(TIMER_REG_CTL, cntpCtl);
}
STATIC_INLINE UINT64 TimerCvalRead(VOID)
{
return READ_TIMER_REG64(TIMER_REG_CVAL);
}
STATIC_INLINE VOID TimerCvalWrite(UINT64 cval)
{
WRITE_TIMER_REG64(TIMER_REG_CVAL, cval);
}
STATIC_INLINE VOID TimerTvalWrite(UINT32 tval)
{
WRITE_TIMER_REG32(TIMER_REG_TVAL, tval);
}
UINT64 HalClockGetCycles(VOID)
{
UINT64 cntpct;
cntpct = READ_TIMER_REG64(TIMER_REG_CT);
return cntpct;
}
LITE_OS_SEC_TEXT VOID OsTickEntry(VOID)
{
TimerCtlWrite(0);
OsTickHandler();
/*
* use last cval to generate the next tick's timing is
* absolute and accurate. DO NOT use tval to drive the
* generic time in which case tick will be slower.
*/
TimerCvalWrite(TimerCvalRead() + OS_CYCLE_PER_TICK);
TimerCtlWrite(1);
}
LITE_OS_SEC_TEXT_INIT VOID HalClockInit(VOID)
{
UINT32 ret;
g_sysClock = HalClockFreqRead();
ret = LOS_HwiCreate(OS_TICK_INT_NUM, MIN_INTERRUPT_PRIORITY, 0, OsTickEntry, 0);
if (ret != LOS_OK) {
PRINT_ERR("%s, %d create tick irq failed, ret:0x%x\n", __FUNCTION__, __LINE__, ret);
}
}
LITE_OS_SEC_TEXT_INIT VOID HalClockStart(VOID)
{
HalIrqUnmask(OS_TICK_INT_NUM);
/* triggle the first tick */
TimerCtlWrite(0);
TimerTvalWrite(OS_CYCLE_PER_TICK);
TimerCtlWrite(1);
}
VOID HalDelayUs(UINT32 usecs)
{
UINT64 cycles = (UINT64)usecs * HalClockFreqRead() / OS_SYS_US_PER_SECOND;
UINT64 deadline = HalClockGetCycles() + cycles;
while (HalClockGetCycles() < deadline) {
__asm__ volatile ("nop");
}
}
UINT64 hi_sched_clock(VOID)
{
return LOS_CurrNanosec();
}
UINT32 HalClockGetTickTimerCycles(VOID)
{
UINT64 cval = TimerCvalRead();
UINT64 cycles = HalClockGetCycles();
return (UINT32)((cval > cycles) ? (cval - cycles) : 0);
}
VOID HalClockTickTimerReload(UINT32 cycles)
{
HalIrqMask(OS_TICK_INT_NUM);
HalIrqClear(OS_TICK_INT_NUM);
TimerCtlWrite(0);
TimerCvalWrite(HalClockGetCycles() + cycles);
TimerCtlWrite(1);
HalIrqUnmask(OS_TICK_INT_NUM);
}

135
platform/hw/arm/timer/arm_private/arm_private_timer.c Executable file
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/*
* Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "asm/platform.h"
#include "los_hwi.h"
#include "los_tick_pri.h"
#define OS_CYCLE_PER_TICK (TIMER_FREQ / LOSCFG_BASE_CORE_TICK_PER_SECOND)
typedef struct {
UINT32 load; /* Private Timer Load Register */
UINT32 count; /* Private Timer Counter Register */
UINT32 control; /* Private Timer Control Register */
UINT32 intStatus; /* Private Timer Interrupt Status Register */
} PrivateTimer;
typedef struct {
UINT32 low; /* Global Timer Counter Registers, low bits */
UINT32 high; /* Global Timer Counter Registers, high bits */
UINT32 control; /* Global Timer Control Register */
UINT32 intStatus; /* Global Timer Interrupt Status Register */
UINT32 compareLow; /* Comparator Value Registers, low bits */
UINT32 compareHigh; /* Comparator Value Registers, high bits */
UINT32 increment; /* Auto-increment Register */
} GlobalTimer;
PrivateTimer *g_privateTimer = (PrivateTimer *)PRVTIMER_BASE_ADDR;
GlobalTimer *g_globalTimer = (GlobalTimer *)GTIMER_BASE_ADDR;
UINT32 HalClockFreqRead(VOID)
{
return TIMER_FREQ;
}
VOID HalClockFreqWrite(UINT32 freq)
{
PRINT_WARN("private timer does not support setting frequency\n");
}
VOID HalClockStart(VOID)
{
HalIrqUnmask(PRVTIMER_INT_NUM);
g_privateTimer->load = OS_CYCLE_PER_TICK;
g_privateTimer->control = 0x06; /* IAE bits = 110, not eanbled yet */
g_privateTimer->control |= 0x01; /* enable private timer */
}
VOID OsTickEntry(VOID)
{
OsTickHandler();
/* clear private timer */
g_privateTimer->intStatus = 0x01;
}
VOID HalClockInit(VOID)
{
UINT32 ret;
ret = LOS_HwiCreate(PRVTIMER_INT_NUM, 0xa0, 0, OsTickEntry, NULL);
if (ret != LOS_OK) {
PRINT_ERR("%s, %d create tick irq failed, ret:0x%x\n", __FUNCTION__, __LINE__, ret);
}
}
UINT64 HalClockGetCycles(VOID)
{
UINT32 low, high;
do {
high = g_globalTimer->high;
low = g_globalTimer->low;
} while (g_globalTimer->high != high);
/* combine high and low into 8 bytes cycles */
return (((UINT64)high << 32) | low);
}
VOID HalDelayUs(UINT32 usecs)
{
UINT64 tmo = LOS_CurrNanosec() + usecs * 1000;
while (LOS_CurrNanosec() < tmo) {
__asm__ volatile ("nop");
}
}
UINT64 hi_sched_clock(VOID)
{
return LOS_CurrNanosec();
}
UINT32 HalClockGetTickTimerCycles(VOID)
{
return g_privateTimer->count;
}
VOID HalClockTickTimerReload(UINT32 period)
{
HalIrqUnmask(PRVTIMER_INT_NUM);
/* set control counter regs to defaults */
g_privateTimer->load = period;
g_privateTimer->control = 0x06; /* IAE bits = 110, not eanbled yet */
g_privateTimer->control |= 0x01; /* reenable private timer */
}

112
platform/hw/hisoc/hrtimer/hrtimer.c Executable file
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/*
* Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_hwi.h"
#include "hisoc/sys_ctrl.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
#define TIMER_ENABLE_BIT 7
#define TIMER_COUNTING_MODE_BIT 6
#define TIMER_INTERRUPT_ENABLE_BIT 5
#define TIMER_SIZE_SELECT_BIT 1
#define TIMER_ONESHOT_BIT 0
VOID HrtimerClockIrqClear(VOID)
{
WRITE_UINT32(0x1, HRTIMER_TIMER_REG_BASE + TIMER_INT_CLR);
}
VOID HrtimerClockInit(VOID)
{
UINT32 temp;
/* enable timer here */
READ_UINT32(temp, SYS_CTRL_REG_BASE + REG_SC_CTRL);
temp |= HRTIMER_TIMER_ENABLE;
WRITE_UINT32(temp, SYS_CTRL_REG_BASE + REG_SC_CTRL);
/* disable timer */
WRITE_UINT32(0x0, HRTIMER_TIMER_REG_BASE + TIMER_CONTROL);
/*
* Timing mode:oneshot [bit 0 set as 1]
* timersize:32bits [bit 1 set as 1]
* ticking with 1/1 clock frequency [bit 3 set as 0, bit 2 set as 0]
* interrupt enabled [bit 5 set as 1]
* timing circulary [bit 6 set as 1]
*/
temp = (1U << TIMER_COUNTING_MODE_BIT) | (1U << TIMER_INTERRUPT_ENABLE_BIT) |
(1U << TIMER_SIZE_SELECT_BIT) | (1U << TIMER_ONESHOT_BIT);
WRITE_UINT32(temp, HRTIMER_TIMER_REG_BASE + TIMER_CONTROL);
}
VOID HrtimerClockStart(UINT32 period)
{
UINT32 temp;
/* set init value as period */
WRITE_UINT32(period, HRTIMER_TIMER_REG_BASE + TIMER_LOAD);
READ_UINT32(temp, HRTIMER_TIMER_REG_BASE + TIMER_CONTROL);
/* timer enabled [bit 7 set as 1] */
temp |= 1U << TIMER_ENABLE_BIT;
WRITE_UINT32(temp, HRTIMER_TIMER_REG_BASE + TIMER_CONTROL);
}
VOID HrtimerClockStop(VOID)
{
UINT32 temp;
READ_UINT32(temp, HRTIMER_TIMER_REG_BASE + TIMER_CONTROL);
/* timer disabled [bit 7 set as 0] */
temp &= ~(1U << TIMER_ENABLE_BIT);
WRITE_UINT32(temp, HRTIMER_TIMER_REG_BASE + TIMER_CONTROL);
}
UINT32 HrtimerClockValueGet(VOID)
{
UINT32 temp;
/* Read the current value of the timer3 */
READ_UINT32(temp, HRTIMER_TIMER_REG_BASE + TIMER_VALUE);
return temp;
}
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */

408
platform/hw/hisoc/timer/timer.c Executable file
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/*
* Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_timer_pri.h"
#include "los_tick_pri.h"
#include "los_sys_pri.h"
#include "los_hwi.h"
#include "hisoc/sys_ctrl.h"
#include "los_swtmr.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
STATIC_ASSERT(LOSCFG_KERNEL_SMP != YES, "hisoc timer does not suppot on SMP mode!");
STATIC_ASSERT(LOSCFG_BASE_CORE_TICK_HW_TIME == YES, "hisoc timer needs to turn on hw time!");
#define TIMER_ENABLE_BIT 7
#define TIMER_COUNTING_MODE_BIT 6
#define TIMER_INTERRUPT_ENABLE_BIT 5
#define TIMER_FREQUENCY_DIV_BIT 3
#define TIMER_SIZE_SELECT_BIT 1
#define TIMER_ONESHOT_BIT 0
#define READ_TIMER (*(volatile UINT32 *)(TIMER_TICK_REG_BASE + TIMER_VALUE))
#define US_PER_MS 1000
#define MS_PER_S 1000
STATIC UINT32 g_timeStamp __attribute__((section(".data.init")));
STATIC UINT32 g_lastDec __attribute__((section(".data.init")));
STATIC volatile UINT64 g_schedClockNanosec = 0;
STATIC volatile UINT64 g_schedClockCycle = 0;
STATIC volatile UINT32 g_timeClkLast = 0;
STATIC UINT16 g_swtmrID;
#ifdef LOSCFG_KERNEL_TICKLESS
VOID HalClockTickTimerReload(UINT32 period)
{
UINT32 cyclesPerTick;
cyclesPerTick = g_sysClock / LOSCFG_BASE_CORE_TICK_PER_SECOND;
WRITE_UINT32(period, TIMER_TICK_REG_BASE + TIMER_LOAD);
WRITE_UINT32(cyclesPerTick, TIMER_TICK_REG_BASE + TIMER_BGLOAD);
HalClockIrqClear();
HalIrqClear(NUM_HAL_INTERRUPT_TIMER);
}
#endif
VOID ResetTimerMasked(VOID)
{
g_lastDec = READ_TIMER;
g_timeStamp = 0;
}
UINT32 GetTimerMasked(VOID)
{
UINT32 now = READ_TIMER;
if (g_lastDec >= now) {
/* not roll back */
g_timeStamp += g_lastDec - now;
} else {
/* rollback */
g_timeStamp += g_lastDec + (g_sysClock / LOSCFG_BASE_CORE_TICK_PER_SECOND) - now;
}
g_lastDec = now;
return g_timeStamp;
}
UINT32 TimeClockRead(VOID)
{
UINT32 value;
READ_UINT32(value, TIMER_TIME_REG_BASE + TIMER_VALUE);
value = TIMER_MAXLOAD - value;
return value;
}
UINT32 ArchTimerRollback(VOID)
{
UINT32 flag;
READ_UINT32(flag, TIMER_TICK_REG_BASE + TIMER_RIS);
return flag;
}
/* this func is start timer2 for start time */
VOID HalClockInitStart(VOID)
{
UINT32 temp;
/*
* enable timer2 here,
* but only time0 is used for system clock.
*/
READ_UINT32(temp, SYS_CTRL_REG_BASE + REG_SC_CTRL);
temp |= TIMER2_ENABLE;
WRITE_UINT32(temp, SYS_CTRL_REG_BASE + REG_SC_CTRL);
/* init the timestamp and lastdec value */
ResetTimerMasked();
/* disable timer2 */
WRITE_UINT32(0x0, TIMER2_REG_BASE + TIMER_CONTROL);
/* set init value as period */
WRITE_UINT32(TIMER_MAXLOAD, TIMER2_REG_BASE + TIMER_LOAD);
/*
* Timing mode: 32bits [bit 1 set as 1]
* ticking with 1/256 clock frequency [bit 3 set as 1, bit 2 set as 0]
* timing circulary [bit 6 set as 1]
* timer enabled [bit 7 set as 1]
*/
temp = (1U << TIMER_ENABLE_BIT) | (1U << TIMER_COUNTING_MODE_BIT) |
(1U << TIMER_FREQUENCY_DIV_BIT) | (1U << TIMER_SIZE_SELECT_BIT);
WRITE_UINT32(temp, TIMER2_REG_BASE + TIMER_CONTROL);
}
UINT32 GetTimer2Value(VOID)
{
UINT32 temp;
READ_UINT32(temp, TIMER2_REG_BASE + TIMER_VALUE);
return temp;
}
UINT32 HalClockGetTickTimerCycles(VOID)
{
UINT32 temp;
READ_UINT32(temp, TIMER_TICK_REG_BASE + TIMER_VALUE);
return temp;
}
/* get the system ms clock since the system start */
UINT32 HiGetMsClock(VOID)
{
const UINT32 t32 = TIMER_MAXLOAD - GetTimer2Value();
UINT64 t64 = (UINT64)t32 << 0x8; /* Timer2 is divided by 256, left shift 8 to recover sys clock */
UINT64 temp = OS_TIME_TIMER_CLOCK / MS_PER_S;
return (UINT32)(t64 / temp);
}
VOID HalClockInit(VOID)
{
UINT32 temp;
UINT32 period = g_sysClock / LOSCFG_BASE_CORE_TICK_PER_SECOND;
/*
* enable time0, timer1 here,
* but only time0 is used for system clock.
*/
READ_UINT32(temp, SYS_CTRL_REG_BASE + REG_SC_CTRL);
temp |= TIMER_TICK_ENABLE | TIMER_TIME_ENABLE;
WRITE_UINT32(temp, SYS_CTRL_REG_BASE + REG_SC_CTRL);
/* disable first */
WRITE_UINT32(0x0, TIMER_TICK_REG_BASE + TIMER_CONTROL);
/* set init value as period */
WRITE_UINT32(period, TIMER_TICK_REG_BASE + TIMER_LOAD);
/*
* Timing mode: 32bits [bit 1 set as 1]
* ticking with 1/1 clock frequency [bit 3 set as 0, bit 2 set as 0]
* interrupt enabled [bit 5 set as 1]
* timing circulary [bit 6 set as 1]
*/
temp = (1U << 6) | (1U << 5) | (1U << 1);
WRITE_UINT32(temp, TIMER_TICK_REG_BASE + TIMER_CONTROL);
/* init the timestamp and lastdec value */
ResetTimerMasked();
/* disable timer1 */
WRITE_UINT32(0x0, TIMER_TIME_REG_BASE + TIMER_CONTROL);
/* set init value as period */
WRITE_UINT32(0xffffffff, TIMER_TIME_REG_BASE + TIMER_LOAD);
/*
* Timing mode: 32bits [bit 1 set as 1]
* ticking with 1/1 clock frequency [bit 3 set as 0, bit 2 set as 0]
* timing circulary [bit 6 set as 1]
* timer enabled [bit 7 set as 1]
*/
temp = (1U << 7) | (1U << 6) | (1U << 1);
WRITE_UINT32(temp, TIMER_TIME_REG_BASE + TIMER_CONTROL);
(void)LOS_HwiCreate(NUM_HAL_INTERRUPT_TIMER, 0xa0, 0, OsTickHandler, 0);
}
VOID HalClockIrqClear(VOID)
{
WRITE_UINT32(1, TIMER_TICK_REG_BASE + TIMER_INT_CLR);
}
VOID HalClockEnable(VOID)
{
UINT32 val;
val = GET_UINT32(TIMER_TICK_REG_BASE + TIMER_CONTROL);
/* timer enabled [bit 7 set as 1] */
val |= 1U << TIMER_ENABLE_BIT;
WRITE_UINT32(val, TIMER_TICK_REG_BASE + TIMER_CONTROL);
}
/* Delay for some number of micro-seconds */
UINT32 GetTimer(UINT32 base)
{
return GetTimerMasked() - base;
}
VOID HalClockDelayUs(UINT32 usecs)
{
UINT32 tmo = 0;
UINT32 tmp;
UINT32 intSave = LOS_IntLock();
/* part of usecs >= 1ms */
if (usecs >= US_PER_MS) {
tmo = usecs / US_PER_MS; /* start to normalize for usec to cycles per sec */
tmo *= (g_sysClock / MS_PER_S); /* largest msecond 1374389 */
usecs -= (usecs / US_PER_MS * US_PER_MS); /* get value of usecs < 1ms */
}
/* part of usecs < 1ms */
if (usecs) {
tmo += (usecs * (g_sysClock / MS_PER_S)) / US_PER_MS; /* translate us into sys_clock, prevent u32 overflow */
}
/* reset "advancing" timestamp to 0, set lastdec value */
ResetTimerMasked();
tmp = GetTimer(0); /* get current timestamp */
/* set advancing stamp wake up time */
tmo += tmp;
while (GetTimerMasked() < tmo) {}
LOS_IntRestore(intSave);
}
VOID HalClockFreqWrite(UINT32 freq)
{
PRINT_WARN("hisoc timer does not support setting frequency\n");
}
STATIC UINT32 UpdateTimeClk(UINT32 *timeClk)
{
UINT32 timeClkNow;
timeClkNow = TimeClockRead();
if (timeClkNow >= g_timeClkLast) {
*timeClk = timeClkNow - g_timeClkLast;
} else {
*timeClk = timeClkNow + (TIMER_MAXLOAD - g_timeClkLast);
}
return timeClkNow;
}
VOID UpdateSchedClock(VOID)
{
UINT32 timeClk;
UINT32 intSave;
intSave = LOS_IntLock();
g_timeClkLast = UpdateTimeClk(&timeClk);
g_schedClockCycle += (UINT64)timeClk;
g_schedClockNanosec += (UINT64)CYCLE_TO_NS(timeClk);
OsAdjTime();
LOS_IntRestore(intSave);
}
STATIC UINT64 GetSchedClock(VOID)
{
UINT32 timeClk;
(VOID)UpdateTimeClk(&timeClk);
return (g_schedClockNanosec + (UINT64)CYCLE_TO_NS(timeClk));
}
STATIC UINT64 SchedClock(VOID)
{
UINT32 intSave;
UINT64 timeClk64;
intSave = LOS_IntLock();
timeClk64 = GetSchedClock();
LOS_IntRestore(intSave);
return timeClk64;
}
UINT64 hi_sched_clock(VOID)
{
return SchedClock();
}
VOID SchedClockSwtmr(VOID)
{
UINT32 ret;
ret = LOS_SwtmrCreate(SCHED_CLOCK_INTETRVAL_TICKS, LOS_SWTMR_MODE_PERIOD,
(SWTMR_PROC_FUNC)UpdateSchedClock, &g_swtmrID, 0);
if (ret != LOS_OK) {
PRINT_ERR("LOS_SwtmrCreate error %u\n", ret);
return;
}
ret = LOS_SwtmrStart(g_swtmrID);
if (ret != LOS_OK) {
PRINT_ERR("LOS_SwtmrStart error %u\n", ret);
return;
}
}
LITE_OS_SEC_TEXT_INIT VOID HalClockStart(VOID)
{
HalIrqUnmask(NUM_HAL_INTERRUPT_TIMER);
HalClockEnable();
/* start adjusting swtmer */
SchedClockSwtmr();
g_cycle2NsScale = ((double)OS_SYS_NS_PER_SECOND / ((long)OS_TIME_TIMER_CLOCK));
}
UINT64 HalClockGetCycles(VOID)
{
UINT32 timeClk;
UINT32 intSave;
UINT64 cycle;
intSave = LOS_IntLock();
(VOID)UpdateTimeClk(&timeClk);
cycle = g_schedClockCycle + (UINT64)timeClk;
LOS_IntRestore(intSave);
return cycle;
}
VOID HalDelayUs(UINT32 usecs)
{
UINT32 tmo = 0;
UINT32 tmp;
UINT32 intSave = LOS_IntLock();
/* part of usecs >= 1ms */
if (usecs >= US_PER_MS) {
tmo = usecs / US_PER_MS; /* start to normalize for usec to cycles per sec */
tmo *= (g_sysClock / MS_PER_S); /* largest msecond 1374389 */
usecs -= (usecs / US_PER_MS * US_PER_MS); /* get value of usecs < 1ms */
}
/* part of usecs < 1ms */
if (usecs) {
tmo += (usecs * (g_sysClock / MS_PER_S)) / US_PER_MS; /* translate us into sys_clock, prevent u32 overflow */
}
/* reset "advancing" timestamp to 0, set lastdec value */
ResetTimerMasked();
tmp = GetTimer(0); /* get current timestamp */
/* set advancing stamp wake up time */
tmo += tmp;
while (GetTimerMasked() < tmo) {}
LOS_IntRestore(intSave);
}
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */

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/*
* Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _GIC_COMMON_H
#define _GIC_COMMON_H
#include "stdint.h"
#include "asm/platform.h"
#include "los_config.h"
/* gic arch revision */
enum {
GICV1 = 1,
GICV2,
GICV3,
GICV4
};
#define GIC_REV_MASK 0xF0
#define GIC_REV_OFFSET 0x4
#ifdef LOSCFG_PLATFORM_BSP_GIC_V2
#define GICC_CTLR (GICC_OFFSET + 0x00) /* CPU Interface Control Register */
#define GICC_PMR (GICC_OFFSET + 0x04) /* Interrupt Priority Mask Register */
#define GICC_BPR (GICC_OFFSET + 0x08) /* Binary Point Register */
#define GICC_IAR (GICC_OFFSET + 0x0c) /* Interrupt Acknowledge Register */
#define GICC_EOIR (GICC_OFFSET + 0x10) /* End of Interrupt Register */
#define GICC_RPR (GICC_OFFSET + 0x14) /* Running Priority Register */
#define GICC_HPPIR (GICC_OFFSET + 0x18) /* Highest Priority Pending Interrupt Register */
#endif
#define GICD_CTLR (GICD_OFFSET + 0x000) /* Distributor Control Register */
#define GICD_TYPER (GICD_OFFSET + 0x004) /* Interrupt Controller Type Register */
#define GICD_IIDR (GICD_OFFSET + 0x008) /* Distributor Implementer Identification Register */
#define GICD_IGROUPR(n) (GICD_OFFSET + 0x080 + (n) * 4) /* Interrupt Group Registers */
#define GICD_ISENABLER(n) (GICD_OFFSET + 0x100 + (n) * 4) /* Interrupt Set-Enable Registers */
#define GICD_ICENABLER(n) (GICD_OFFSET + 0x180 + (n) * 4) /* Interrupt Clear-Enable Registers */
#define GICD_ISPENDR(n) (GICD_OFFSET + 0x200 + (n) * 4) /* Interrupt Set-Pending Registers */
#define GICD_ICPENDR(n) (GICD_OFFSET + 0x280 + (n) * 4) /* Interrupt Clear-Pending Registers */
#define GICD_ISACTIVER(n) (GICD_OFFSET + 0x300 + (n) * 4) /* GICv2 Interrupt Set-Active Registers */
#define GICD_ICACTIVER(n) (GICD_OFFSET + 0x380 + (n) * 4) /* Interrupt Clear-Active Registers */
#define GICD_IPRIORITYR(n) (GICD_OFFSET + 0x400 + (n) * 4) /* Interrupt Priority Registers */
#define GICD_ITARGETSR(n) (GICD_OFFSET + 0x800 + (n) * 4) /* Interrupt Processor Targets Registers */
#define GICD_ICFGR(n) (GICD_OFFSET + 0xc00 + (n) * 4) /* Interrupt Configuration Registers */
#define GICD_SGIR (GICD_OFFSET + 0xf00) /* Software Generated Interrupt Register */
#define GICD_CPENDSGIR(n) (GICD_OFFSET + 0xf10 + (n) * 4) /* SGI Clear-Pending Registers; NOT available on cortex-a9 */
#define GICD_SPENDSGIR(n) (GICD_OFFSET + 0xf20 + (n) * 4) /* SGI Set-Pending Registers; NOT available on cortex-a9 */
#define GICD_PIDR2V2 (GICD_OFFSET + 0xfe8)
#define GICD_PIDR2V3 (GICD_OFFSET + 0xffe8)
#ifdef LOSCFG_PLATFORM_BSP_GIC_V3
#define GICD_IGRPMODR(n) (GICD_OFFSET + 0x0d00 + (n) * 4) /* Interrupt Group Mode Reisters */
#define GICD_IROUTER(n) (GICD_OFFSET + 0x6000 + (n) * 8) /* Interrupt Rounter Reisters */
#endif
#define GIC_REG_8(reg) (*(volatile UINT8 *)((UINTPTR)(GIC_BASE_ADDR + (reg))))
#define GIC_REG_32(reg) (*(volatile UINT32 *)((UINTPTR)(GIC_BASE_ADDR + (reg))))
#define GIC_REG_64(reg) (*(volatile UINT64 *)((UINTPTR)(GIC_BASE_ADDR + (reg))))
#define GICD_INT_DEF_PRI 0xa0U
#define GICD_INT_DEF_PRI_X4 (((UINT32)GICD_INT_DEF_PRI << 24) | \
((UINT32)GICD_INT_DEF_PRI << 16) | \
((UINT32)GICD_INT_DEF_PRI << 8) | \
(UINT32)GICD_INT_DEF_PRI)
#define GIC_MIN_SPI_NUM 32
/* Interrupt preemption config */
#define GIC_PRIORITY_MASK 0xFFU
#define GIC_PRIORITY_OFFSET 8
/*
* The number of bits to shift for an interrupt priority is dependent
* on the number of bits implemented by the interrupt controller.
* If the MAX_BINARY_POINT_VALUE is 7,
* it means that interrupt preemption is not supported.
*/
#ifndef LOSCFG_ARCH_INTERRUPT_PREEMPTION
#define MAX_BINARY_POINT_VALUE 7
#define PRIORITY_SHIFT 0
#define GIC_MAX_INTERRUPT_PREEMPTION_LEVEL 0U
#else
#define PRIORITY_SHIFT ((MAX_BINARY_POINT_VALUE + 1) % GIC_PRIORITY_OFFSET)
#define GIC_MAX_INTERRUPT_PREEMPTION_LEVEL ((UINT8)((GIC_PRIORITY_MASK + 1) >> PRIORITY_SHIFT))
#endif
#define GIC_INTR_PRIO_MASK ((UINT8)(0xFFFFFFFFU << PRIORITY_SHIFT))
/*
* The preemption level is up to 128, and the maximum value corresponding to the interrupt priority is 254 [7:1].
* If the GIC_MAX_INTERRUPT_PREEMPTION_LEVEL is 0, the minimum priority is 0xff.
*/
#define MIN_INTERRUPT_PRIORITY ((UINT8)((GIC_MAX_INTERRUPT_PREEMPTION_LEVEL - 1) << PRIORITY_SHIFT))
#endif

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platform/hw/include/gic_v3.h Executable file
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/*
* Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _GIC_V3_H_
#define _GIC_V3_H_
#include "stdint.h"
#include "asm/platform.h"
#include "los_hw_cpu.h"
#define BIT_32(bit) (1u << bit)
#define BIT_64(bit) (1ul << bit)
#define ICC_CTLR_EL1 "S3_0_C12_C12_4"
#define ICC_PMR_EL1 "S3_0_C4_C6_0"
#define ICC_IAR1_EL1 "S3_0_C12_C12_0"
#define ICC_SRE_EL1 "S3_0_C12_C12_5"
#define ICC_BPR0_EL1 "S3_0_C12_C8_3"
#define ICC_BPR1_EL1 "S3_0_C12_C12_3"
#define ICC_IGRPEN0_EL1 "S3_0_C12_C12_6"
#define ICC_IGRPEN1_EL1 "S3_0_C12_C12_7"
#define ICC_EOIR1_EL1 "S3_0_C12_C12_1"
#define ICC_SGI1R_EL1 "S3_0_C12_C11_5"
#define ICC_EOIR0_EL1 "S3_0_c12_c8_1"
#define ICC_IAR0_EL1 "S3_0_C12_C8_0"
#define ICC_CTLR_EL3 "S3_6_C12_C12_4"
#define ICC_SRE_EL3 "S3_6_C12_C12_5"
#define ICC_IGRPEN1_EL3 "S3_6_C12_C12_7"
/* GICD_CTLR bit definitions */
#define CTLR_ENALBE_G0 BIT_32(0)
#define CTLR_ENABLE_G1NS BIT_32(1)
#define CTLR_ENABLE_G1S BIT_32(2)
#define CTLR_RES0 BIT_32(3)
#define CTLR_ARE_S BIT_32(4)
#define CTLR_ARE_NS BIT_32(5)
#define CTLR_DS BIT_32(6)
#define CTLR_E1NWF BIT_32(7)
#define GICD_CTLR_RWP BIT_32(31)
/* peripheral identification registers */
#define GICD_CIDR0 (GICD_OFFSET + 0xfff0)
#define GICD_CIDR1 (GICD_OFFSET + 0xfff4)
#define GICD_CIDR2 (GICD_OFFSET + 0xfff8)
#define GICD_CIDR3 (GICD_OFFSET + 0xfffc)
#define GICD_PIDR0 (GICD_OFFSET + 0xffe0)
#define GICD_PIDR1 (GICD_OFFSET + 0xffe4)
#define GICD_PIDR2 (GICD_OFFSET + 0xffe8)
#define GICD_PIDR3 (GICD_OFFSET + 0xffec)
/* GICD_PIDR bit definitions and masks */
#define GICD_PIDR2_ARCHREV_SHIFT 4
#define GICD_PIDR2_ARCHREV_MASK 0xf
/* redistributor registers */
#define GICR_SGI_OFFSET (GICR_OFFSET + 0x10000)
#define GICR_CTLR(i) (GICR_OFFSET + GICR_STRIDE * (i) + 0x0000)
#define GICR_IIDR(i) (GICR_OFFSET + GICR_STRIDE * (i) + 0x0004)
#define GICR_TYPER(i, n) (GICR_OFFSET + GICR_STRIDE * (i) + 0x0008 + (n)*4)
#define GICR_STATUSR(i) (GICR_OFFSET + GICR_STRIDE * (i) + 0x0010)
#define GICR_WAKER(i) (GICR_OFFSET + GICR_STRIDE * (i) + 0x0014)
#define GICR_IGROUPR0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0080)
#define GICR_IGRPMOD0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0d00)
#define GICR_ISENABLER0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0100)
#define GICR_ICENABLER0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0180)
#define GICR_ISPENDR0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0200)
#define GICR_ICPENDR0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0280)
#define GICR_ISACTIVER0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0300)
#define GICR_ICACTIVER0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0380)
#define GICR_IPRIORITYR0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0400)
#define GICR_ICFGR0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0c00)
#define GICR_ICFGR1(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0c04)
#define GICR_NSACR(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0e00)
#define GICR_WAKER_PROCESSORSLEEP_LEN 1U
#define GICR_WAKER_PROCESSORSLEEP_OFFSET 1
#define GICR_WAKER_CHILDRENASLEEP_LEN 1U
#define GICR_WAKER_CHILDRENASLEEP_OFFSET 2
#define GICR_WAKER_PROCESSORSLEEP (GICR_WAKER_PROCESSORSLEEP_LEN << GICR_WAKER_PROCESSORSLEEP_OFFSET)
#define GICR_WAKER_CHILDRENASLEEP (GICR_WAKER_CHILDRENASLEEP_LEN << GICR_WAKER_CHILDRENASLEEP_OFFSET)
STATIC INLINE VOID GiccSetCtlr(UINT32 val)
{
#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
__asm__ volatile("msr " ICC_CTLR_EL3 ", %0" ::"r"(val));
#else
__asm__ volatile("msr " ICC_CTLR_EL1 ", %0" ::"r"(val));
#endif
ISB;
}
STATIC INLINE VOID GiccSetPmr(UINT32 val)
{
__asm__ volatile("msr " ICC_PMR_EL1 ", %0" ::"r"(val));
ISB;
DSB;
}
STATIC INLINE VOID GiccSetIgrpen0(UINT32 val)
{
__asm__ volatile("msr " ICC_IGRPEN0_EL1 ", %0" ::"r"(val));
ISB;
}
STATIC INLINE VOID GiccSetIgrpen1(UINT32 val)
{
#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
__asm__ volatile("msr " ICC_IGRPEN1_EL3 ", %0" ::"r"(val));
#else
__asm__ volatile("msr " ICC_IGRPEN1_EL1 ", %0" ::"r"(val));
#endif
ISB;
}
STATIC INLINE UINT32 GiccGetSre(VOID)
{
UINT32 temp;
#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
__asm__ volatile("mrs %0, " ICC_SRE_EL3 : "=r"(temp));
#else
__asm__ volatile("mrs %0, " ICC_SRE_EL1 : "=r"(temp));
#endif
return temp;
}
STATIC INLINE VOID GiccSetSre(UINT32 val)
{
#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
__asm__ volatile("msr " ICC_SRE_EL3 ", %0" ::"r"(val));
#else
__asm__ volatile("msr " ICC_SRE_EL1 ", %0" ::"r"(val));
#endif
ISB;
}
STATIC INLINE VOID GiccSetEoir(UINT32 val)
{
#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
__asm__ volatile("msr " ICC_EOIR0_EL1 ", %0" ::"r"(val));
#else
__asm__ volatile("msr " ICC_EOIR1_EL1 ", %0" ::"r"(val));
#endif
ISB;
}
STATIC INLINE UINT32 GiccGetIar(VOID)
{
UINT32 temp;
#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
__asm__ volatile("mrs %0, " ICC_IAR0_EL1 : "=r"(temp));
#else
__asm__ volatile("mrs %0, " ICC_IAR1_EL1 : "=r"(temp));
#endif
DSB;
return temp;
}
STATIC INLINE VOID GiccSetSgi1r(UINT64 val)
{
__asm__ volatile("msr " ICC_SGI1R_EL1 ", %0" ::"r"(val));
ISB;
DSB;
}
STATIC INLINE VOID GiccSetBpr0(UINT32 val)
{
__asm__ volatile("msr " ICC_BPR0_EL1 ", %0" ::"r"(val));
ISB;
DSB;
}
#endif

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/*
* Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _HWI_H
#define _HWI_H
#include "los_typedef.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
extern VOID HalIrqInit(VOID);
extern VOID HalIrqInitPercpu(VOID);
extern VOID HalIrqMask(UINT32 vector);
extern VOID HalIrqUnmask(UINT32 vector);
extern VOID HalIrqPending(UINT32 vector);
extern VOID HalIrqClear(UINT32 vector);
extern CHAR *HalIrqVersion(VOID);
extern UINT32 HalCurIrqGet(VOID);
extern UINT32 HalIrqSetPrio(UINT32 vector, UINT8 priority);
#if (LOSCFG_KERNEL_SMP == YES)
extern VOID HalIrqSendIpi(UINT32 target, UINT32 ipi);
extern VOID HalIrqSetAffinity(UINT32 vector, UINT32 cpuMask);
#endif
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _HWI_H */

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platform/include/hal_timer.h Executable file
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/*
* Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_TIMER_H
#define _LOS_TIMER_H
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
extern UINT32 HalClockFreqRead(VOID);
extern VOID HalClockFreqWrite(UINT32 freq);
extern VOID HalClockStart(VOID);
extern VOID HalClockIrqClear(VOID);
extern VOID HalClockInit(VOID);
extern UINT64 HalClockGetCycles(VOID);
extern VOID HalDelayUs(UINT32 usecs);
extern UINT64 hi_sched_clock(VOID);
extern UINT32 HalClockGetTickTimerCycles(VOID);
extern VOID HalClockTickTimerReload(UINT32 cycles);
extern UINT32 HrtimersInit(VOID);
extern VOID HrtimerClockIrqClear(VOID);
extern VOID HrtimerClockStart(UINT32 period);
extern VOID HrtimerClockStop(VOID);
extern UINT32 HrtimerClockValueGet(VOID);
extern VOID HrtimerClockInit(VOID);
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_TIMER_H */

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platform/main.c Executable file
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/*
* Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_config.h"
#include "los_task_pri.h"
#include "los_swtmr_pri.h"
#include "los_printf.h"
#include "los_atomic.h"
#include "gic_common.h"
#include "uart.h"
#include "los_process_pri.h"
#include "los_arch_mmu.h"
#if (LOSCFG_KERNEL_SMP == YES)
STATIC Atomic g_ncpu = 1;
#endif
LITE_OS_SEC_TEXT_INIT VOID OsSystemInfo(VOID)
{
#ifdef LOSCFG_DEBUG_VERSION
const CHAR *buildType = "debug";
#else
const CHAR *buildType = "release";
#endif /* LOSCFG_DEBUG_VERSION */
PRINT_RELEASE("\n******************Welcome******************\n\n"
"Processor : %s"
#if (LOSCFG_KERNEL_SMP == YES)
" * %d\n"
"Run Mode : SMP\n"
#else
"\n"
"Run Mode : UP\n"
#endif
"GIC Rev : %s\n"
"build time : %s %s\n"
"Kernel : %s %d.%d.%d.%d/%s\n"
"\n*******************************************\n",
LOS_CpuInfo(),
#if (LOSCFG_KERNEL_SMP == YES)
LOSCFG_KERNEL_SMP_CORE_NUM,
#endif
HalIrqVersion(), __DATE__, __TIME__,\
KERNEL_NAME, KERNEL_MAJOR, KERNEL_MINOR, KERNEL_PATCH, KERNEL_ITRE, buildType);
}
LITE_OS_SEC_TEXT_INIT VOID secondary_cpu_start(VOID)
{
#if (LOSCFG_KERNEL_SMP == YES)
UINT32 cpuid = ArchCurrCpuid();
OsArchMmuInitPerCPU();
OsCurrTaskSet(OsGetMainTask());
/* increase cpu counter */
LOS_AtomicInc(&g_ncpu);
/* store each core's hwid */
CPU_MAP_SET(cpuid, OsHwIDGet());
HalIrqInitPercpu();
OsCurrProcessSet(OS_PCB_FROM_PID(OsGetKernelInitProcessID()));
OsSwtmrInit();
OsIdleTaskCreate();
OsStart();
while (1) {
__asm volatile("wfi");
}
#endif
}
#if (LOSCFG_KERNEL_SMP == YES)
#ifdef LOSCFG_TEE_ENABLE
#define TSP_CPU_ON 0xb2000011UL
STATIC INT32 raw_smc_send(UINT32 cmd)
{
register UINT32 smc_id asm("r0") = cmd;
do {
asm volatile (
"mov r0, %[a0]\n"
"smc #0\n"
: [a0] "+r"(smc_id)
);
} while (0);
return (INT32)smc_id;
}
STATIC VOID trigger_secondary_cpu(VOID)
{
(VOID)raw_smc_send(TSP_CPU_ON);
}
LITE_OS_SEC_TEXT_INIT VOID release_secondary_cores(VOID)
{
trigger_secondary_cpu();
/* wait until all APs are ready */
while (LOS_AtomicRead(&g_ncpu) < LOSCFG_KERNEL_CORE_NUM) {
asm volatile("wfe");
}
}
#else
#define CLEAR_RESET_REG_STATUS(regval) (regval) &= ~(1U << 2)
LITE_OS_SEC_TEXT_INIT VOID release_secondary_cores(VOID)
{
UINT32 regval;
/* clear the slave cpu reset */
READ_UINT32(regval, PERI_CRG30_BASE);
CLEAR_RESET_REG_STATUS(regval);
WRITE_UINT32(regval, PERI_CRG30_BASE);
/* wait until all APs are ready */
while (LOS_AtomicRead(&g_ncpu) < LOSCFG_KERNEL_CORE_NUM) {
asm volatile("wfe");
}
}
#endif /* LOSCFG_TEE_ENABLE */
#endif /* LOSCFG_KERNEL_SMP */
LITE_OS_SEC_TEXT_INIT INT32 main(VOID)
{
UINT32 uwRet = LOS_OK;
OsSetMainTask();
OsCurrTaskSet(OsGetMainTask());
/* set smp system counter freq */
#if (LOSCFG_KERNEL_SMP == YES)
#ifndef LOSCFG_TEE_ENABLE
HalClockFreqWrite(OS_SYS_CLOCK);
#endif
#endif
/* system and chip info */
OsSystemInfo();
PRINT_RELEASE("\nmain core booting up...\n");
uwRet = OsMain();
if (uwRet != LOS_OK) {
return LOS_NOK;
}
#if (LOSCFG_KERNEL_SMP == YES)
PRINT_RELEASE("releasing %u secondary cores\n", LOSCFG_KERNEL_SMP_CORE_NUM - 1);
release_secondary_cores();
#endif
CPU_MAP_SET(0, OsHwIDGet());
OsStart();
while (1) {
__asm volatile("wfi");
}
}

304
platform/uart/amba-pl011-lagacy/uart.c Executable file
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/*
* Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_event.h"
#include "los_task.h"
#include "hisoc/uart.h"
#include "los_printf.h"
EVENT_CB_S g_uartEvent;
#ifdef LOSCFG_PLATFORM_UART_WITHOUT_VFS
#ifdef LOSCFG_SHELL
#define UART_BUF 128
static UINT8 g_uart_buf[UART_BUF];
extern void shellCmdLineParse(CHAR c, pf_OUTPUT pf_put);
static channel_data_t smdk_ser_channels[2] = {
{(UINT32)UART0_REG_BASE, 1000, NUM_HAL_INTERRUPT_UART0},
{(UINT32)UART1_REG_BASE, 1000, NUM_HAL_INTERRUPT_UART1}
};
#endif
#endif
#ifdef LOSCFG_GDB
extern int gdb_is_enter(void);
#endif
UINT8 uart_getc(void)
{
UINT8 ch = 0;
UINT32 base = UART_REG_BASE;
#ifdef LOSCFG_GDB
if (gdb_is_enter()) {
// nothing to do when using gdb, you can't read from serial.
} else {
#endif
UINT32 status;
READ_UINT32(status, base + UART_FR);
/* Wait until there is data in the FIFO */
while (status & 0x10) {
READ_UINT32(status, base + UART_FR);
(VOID)LOS_TaskDelay(1);
}
READ_UINT8(ch, UART_REG_BASE + UART_DR);
#ifdef LOSCFG_GDB
}
#endif
return ch; /*lint !e438*/
} /*lint !e550*/
#if defined(LOSCFG_COREDUMP) || defined(LOSCFG_LLTSER)
UINT8 uart_getc_interrupt(void)
{
UINT8 ch = 0;
UINT32 status;
UINT32 base = UART_REG_BASE;
READ_UINT32(status, base + UART_FR);
while (status & 0x10) { /*lint !e40*/
READ_UINT32(status, base + UART_FR);
}
/* receive one char */
READ_UINT8(ch, UART_REG_BASE + UART_DR);
return ch;
}
#endif
#ifdef LOSCFG_GDB
static char gdb_log_buf[1024 * 8];
static int gdb_log_buf_write_pos = 0;
static int gdb_log_buf_read_pos = 0;
const static int gdb_log_buf_size = sizeof(gdb_log_buf);
#endif
char uart_putc(char c)
{
#ifdef LOSCFG_GDB
if (gdb_is_enter()) {
// if buf full
if (((gdb_log_buf_write_pos + 1) % gdb_log_buf_size) == gdb_log_buf_read_pos) {
// buffer is full, u can do others
} else {
// when using gdb, we should save log data temporarily.
gdb_log_buf[gdb_log_buf_write_pos] = c;
gdb_log_buf_write_pos = (gdb_log_buf_write_pos + 1) % gdb_log_buf_size;
}
} else {
#endif
UINT32 status = 0;
/* Wait for Tx FIFO not full */
do {
READ_UINT32(status, UART_REG_BASE + UART_FR);
} while (status & 0x20);
WRITE_UINT8(c, UART_REG_BASE + UART_DR);
#ifdef LOSCFG_GDB
}
#endif
return c;
}
unsigned int g_uart_fputc_en __attribute__ ((section(".data"))) = 1;
char uart_fputc(char c, void *f)
{
if (g_uart_fputc_en == 1) {
if (c == '\n') {
uart_putc('\r'); /*lint !e534*/
}
return (uart_putc(c));
} else {
return 0;
}
}
#ifdef LOSCFG_PLATFORM_UART_WITHOUT_VFS
#ifdef LOSCFG_SHELL
static void uart_notice_adapt(void)
{
LOS_EventWrite(&g_uartEvent, 0x112);
}
void uart_get_raw(void)
{
UINT8 ch;
static int cnt_ii = 0;
if (cnt_ii == 0) {
(VOID)memset_s(g_uart_buf, UART_BUF, 0, UART_BUF);
}
ch = uart_getc();
g_uart_buf[cnt_ii] = ch;
cnt_ii++;
switch (cnt_ii) {
case 1: // only one char
if (ch != 27) { // un special
uart_notice_adapt();
cnt_ii = 0;
}
break;
case 2:
if (ch != 91) {
uart_notice_adapt();
cnt_ii = 0;
}
break;
case 3:
switch (ch) {
default:
case 'A':
case 'B':
case 'C':
case 'D':
uart_notice_adapt();
cnt_ii = 0;
break;
case 51:
case 49:
case 52:
break;
}
break;
case 4:
uart_notice_adapt();
cnt_ii = 0;
break;
default:
uart_notice_adapt();
cnt_ii = 0;
break;
}
}
extern void dprintf(const char *fmt, ...);
static void uart_irqhandle(void)
{
shellCmdLineParse(0, dprintf);
WRITE_UINT32((1 << 4) | (1 << 6), UART_REG_BASE + UART_CLR);
}
int uart_hwiCreate(void)
{
UINT32 uwRet = 0;
if (uwRet != LOS_HwiCreate(NUM_HAL_INTERRUPT_UART, 0xa0, 0, uart_irqhandle, 0)) {
return uwRet;
}
uart_interrupt_unmask();
return 0;
}
#endif /* LOSCFG_SHELL */
#endif /* LOSCFG_PLATFORM_UART_WITHOUT_VFS */
void uart_init(void)
{
UINT32 uwBaudRate;
UINT32 divider;
UINT32 remainder;
UINT32 fraction;
#if defined LOSCFG_PLATFORM_HI3519 || defined LOSCFG_PLATFORM_HI3519V101 || defined LOSCFG_PLATFORM_HI3559
uart_pin_mux_cfg(CONSOLE_UART); /*lint !e506*/
uart_clk_cfg(CONSOLE_UART, true); /*lint !e506*/
#endif
/* First, disable everything */
WRITE_UINT32(0x0, UART_REG_BASE + UART_CR);
/* set baud rate */
uwBaudRate = 16 * CONSOLE_UART_BAUDRATE;
divider = CONFIG_UART_CLK_INPUT / uwBaudRate;
remainder = CONFIG_UART_CLK_INPUT % uwBaudRate;
uwBaudRate = (8 * remainder) / CONSOLE_UART_BAUDRATE;
fraction = (uwBaudRate >> 1) + (uwBaudRate & 1);
WRITE_UINT32(divider, UART_REG_BASE + UART_IBRD);
WRITE_UINT32(fraction, UART_REG_BASE + UART_FBRD);
/* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled. */
WRITE_UINT32((3 << 5) | (1 << 4), UART_REG_BASE + UART_LCR_H);
/* set the fifo threshold of recv interrupt >= 1/8 full */
WRITE_UINT32((2 << 3) | (4 << 0), UART_REG_BASE + UART_IFLS);
/* set nonblock of recv interrupt and recv timeout interrupt */
WRITE_UINT32((1 << 4) | (1 << 6), UART_REG_BASE + UART_IMSC);
/* enable the UART */
WRITE_UINT32((1 << 0) | (1 << 8) | (1 << 9), UART_REG_BASE + UART_CR);
(VOID)LOS_EventInit(&g_uartEvent);
}
#ifdef LOSCFG_GDB
UINT8 gdb_uart_getc(void)
{
UINT8 ch = 0;
UINT32 status;
UINT32 base = UART_REG_BASE;
READ_UINT32(status, base + UART_FR);
/* Wait until there is data in the FIFO */
while (status & 0x10) { /*lint !e40*/
READ_UINT32(status, base + UART_FR);
}
READ_UINT8(ch, UART_REG_BASE + UART_DR);
return ch; /*lint !e438*/
}
char gdb_uart_putc(char c)
{
UINT32 status = 0;
/* Wait for Tx FIFO not full */
do {
READ_UINT32(status, UART_REG_BASE + UART_FR);
} while (status & 0x20);
WRITE_UINT8(c, UART_REG_BASE + UART_DR);
return c;
}
void gdb_log_flush(void)
{
while (gdb_log_buf_read_pos != gdb_log_buf_write_pos) {
gdb_uart_putc(gdb_log_buf[gdb_log_buf_read_pos]);
gdb_log_buf_read_pos = (gdb_log_buf_read_pos + 1) % gdb_log_buf_size;
}
}
#endif
void uart_interrupt_unmask(void)
{
HalIrqUnmask(NUM_HAL_INTERRUPT_UART);
}

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platform/uart/amba_pl011/amba_pl011.c Executable file
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/*
* Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "amba_pl011.h"
#include "asm/platform.h"
#include "uart.h"
#include "los_hwi.h"
#include "los_spinlock.h"
#include "los_event.h"
#include "los_task_pri.h"
EVENT_CB_S g_stShellEvent;
CHAR g_inputCmd[CMD_LENGTH];
INT32 g_inputIdx = 0;
__attribute__ ((section(".data"))) UINT32 g_uart_fputc_en = 1;
#define REG32(addr) ((volatile UINT32 *)(UINTPTR)(addr))
#define UARTREG(base, reg) (*REG32((base) + (reg)))
#define UART_FR_TXFF (0x1U << 5)
STATIC VOID UartPutcReg(UINTPTR base, CHAR c)
{
/* Spin while fifo is full */
while (UARTREG(base, UART_FR) & UART_FR_TXFF) {}
UARTREG(base, UART_DR) = c;
}
STATIC INLINE UINTPTR uart_to_ptr(UINTPTR n)
{
(VOID)n;
return UART_REG_BASE;
}
INT32 uart_putc(INT32 port, CHAR c)
{
UINTPTR base = uart_to_ptr((UINT32)port);
UartPutcReg(base, c);
return 1;
}
CHAR uart_fputc(CHAR c, VOID *f)
{
(VOID)f;
if (g_uart_fputc_en == 1) {
if (c == '\n') {
(VOID)uart_putc(0, '\r');
}
return (uart_putc(0, (c)));
} else {
return 0;
}
}
LITE_OS_SEC_BSS STATIC SPIN_LOCK_INIT(g_uartOutputSpin);
STATIC VOID UartPutStr(UINTPTR base, const CHAR *s, UINT32 len)
{
UINT32 i;
for (i = 0; i < len; i++) {
if (*(s + i) == '\n') {
UartPutcReg(base, '\r');
}
UartPutcReg(base, *(s + i));
}
}
UINT32 UartPutsReg(UINTPTR base, const CHAR *s, UINT32 len, BOOL isLock)
{
UINT32 intSave;
if (g_uart_fputc_en == 0) {
return 0;
}
if (isLock) {
LOS_SpinLockSave(&g_uartOutputSpin, &intSave);
UartPutStr(base, s, len);
LOS_SpinUnlockRestore(&g_uartOutputSpin, intSave);
} else {
UartPutStr(base, s, len);
}
return len;
}
VOID UartPuts(const CHAR *s, UINT32 len, BOOL isLock)
{
UINTPTR base = uart_to_ptr(0);
(VOID)UartPutsReg(base, s, len, isLock);
}
INT32 uart_puts(const CHAR *s, UINTPTR len, VOID *state)
{
(VOID)state;
UINTPTR i;
for (i = 0; i < len; i++) {
if (*(s + i) != '\0') {
if (*(s + i) == '\n') {
(VOID)uart_fputc('\r', NULL);
}
(VOID)uart_fputc(*(s + i), NULL);
}
}
return (INT32)len;
}
VOID uart_handler(VOID)
{
CHAR c;
UINTPTR base = uart_to_ptr(0);
c = UARTREG(base, UART_DR);
switch (c) {
case '\r':
case '\n':
if (g_inputIdx < CMD_LENGTH - 1) {
g_inputCmd[g_inputIdx++] = '\0';
LOS_EventWrite(&g_stShellEvent, 0x1);
(VOID)uart_putc(0, '\r');
(VOID)uart_putc(0, '\n');
}
break;
case 0x8: /* backspace */
case 0x7f: /* delete */
if (g_inputIdx > 0) {
g_inputIdx--;
(VOID)uart_putc(0, '\b');
(VOID)uart_putc(0, ' ');
(VOID)uart_putc(0, '\b');
}
break;
default:
if (g_inputIdx < CMD_LENGTH - 1) {
(VOID)uart_putc(0, c);
g_inputCmd[g_inputIdx++] = c;
}
}
}
VOID uart_early_init(VOID)
{
/* enable uart transmit */
UARTREG(UART_REG_BASE, UART_CR) = (1 << 8) | (1 << 0);
}
VOID uart_init(VOID)
{
UINT32 ret;
/* uart interrupt priority should be the highest in interrupt preemption mode */
ret = LOS_HwiCreate(NUM_HAL_INTERRUPT_UART, 0, 0, (HWI_PROC_FUNC)uart_handler, NULL);
if (ret != LOS_OK) {
PRINT_ERR("%s,%d, uart interrupt created error:%x\n", __FUNCTION__, __LINE__, ret);
} else {
/* clear all irqs */
UARTREG(UART_REG_BASE, UART_ICR) = 0x3ff;
/* set fifo trigger level */
UARTREG(UART_REG_BASE, UART_IFLS) = 0;
/* enable rx interrupt */
UARTREG(UART_REG_BASE, UART_IMSC) = (1 << 4 | 1 << 6);
/* enable receive */
UARTREG(UART_REG_BASE, UART_CR) |= (1 << 9);
HalIrqUnmask(NUM_HAL_INTERRUPT_UART);
}
}

68
platform/uart/amba_pl011/amba_pl011.h Executable file
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/*
* Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _AMBA_PL011_UART_H
#define _AMBA_PL011_UART_H
#include "los_typedef.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
#define UART_DR 0x0 /* data register */
#define UART_RSR 0x04
#define UART_FR 0x18 /* flag register */
#define UART_CLR 0x44 /* interrupt clear register */
#define UART_CR 0x30 /* control register */
#define UART_IBRD 0x24 /* interge baudrate register */
#define UART_FBRD 0x28 /* decimal baudrate register */
#define UART_LCR_H 0x2C
#define UART_IFLS 0x34 /* fifo register */
#define UART_IMSC 0x38 /* interrupt mask register */
#define UART_RIS 0x3C /* base interrupt state register */
#define UART_MIS 0x40 /* mask interrupt state register */
#define UART_ICR 0x44
#define UART_DMACR 0x48 /* DMA control register */
#define CMD_LENGTH 128
extern CHAR g_inputCmd[CMD_LENGTH];
extern INT32 g_inputIdx;
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif

215
platform/uart/dw-3.0.8a/uart.c Executable file
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/*
* Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_event.h"
#include "hisoc/uart.h"
EVENT_CB_S g_uartEvent;
#ifdef LOSCFG_PLATFORM_UART_WITHOUT_VFS
#ifdef LOSCFG_SHELL
#define UART_BUF 128
static UINT8 g_uart_buf[UART_BUF];
extern void shellCmdLineParse(CHAR c, pf_OUTPUT pf_put);
#endif
#endif
UINT8 uart_getc(void)
{
UINT8 ch = 0;
while (!(GET_UINT32(UART_REG_BASE + UART_USR) & 0x08)) { /*lint !e40*/
LOS_Msleep(100);
}
/* receive one char */
READ_UINT8(ch, UART_REG_BASE + UART_DR);
return ch;
}
#if defined(LOSCFG_COREDUMP) || defined(LOSCFG_LLTSER)
UINT8 uart_getc_interrupt(void)
{
UINT8 ch = 0;
while (!(GET_UINT32(UART_REG_BASE + UART_USR) & 0x08)) { /*lint !e40*/
}
/* receive one char */
READ_UINT8(ch, UART_REG_BASE + UART_DR);
return ch;
}
#endif
/* send */
char uart_putc (char c)
{
/* Wait until THRE is empyt */
while (!(GET_UINT32(UART_REG_BASE + UART_USR) & 0x02)); /*lint !e40*/
/* send one char */
WRITE_UINT8(c, UART_REG_BASE + UART_DR);
return c;
}
unsigned int g_uart_fputc_en __attribute__ ((section(".data"))) = 1;
char uart_fputc(char c, void *f)
{
if (g_uart_fputc_en == 1) {
if (c == '\n') {
uart_putc('\r'); /*lint !e534*/
}
return (uart_putc(c));
} else {
return 0;
}
}
#ifdef LOSCFG_PLATFORM_UART_WITHOUT_VFS
#ifdef LOSCFG_SHELL
static void uart_notice_adapt(void)
{
LOS_EventWrite(&g_uartEvent, 0x112);
}
void uart_get_raw(void)
{
UINT8 ch;
static int cnt_ii = 0;
if (cnt_ii == 0) {
(VOID)memset_s(g_uart_buf, UART_BUF, 0, UART_BUF);
}
ch = uart_getc();
g_uart_buf[cnt_ii] = ch;
cnt_ii++;
switch (cnt_ii) {
case 1: // only one char
if (ch != 27) { // un special
uart_notice_adapt();
cnt_ii = 0;
}
break;
case 2:
if (ch != 91) {
uart_notice_adapt();
cnt_ii = 0;
}
break;
case 3:
switch (ch) {
default:
case 'A':
case 'B':
case 'C':
case 'D':
{
uart_notice_adapt();
cnt_ii = 0;
}
break;
case 51:
case 49:
case 52:
break;
}
break;
case 4:
{
uart_notice_adapt();
cnt_ii = 0;
}
break;
default:
{
uart_notice_adapt();
cnt_ii = 0;
}
break;
}
}
extern void dprintf(const char *fmt, ...);
static void uart_irqhandle(void)
{
UINT8 ch;
shellCmdLineParse(0, dprintf);
}
int uart_hwiCreate(void)
{
UINT32 uwRet = 0;
if (uwRet != LOS_HwiCreate(NUM_HAL_INTERRUPT_UART, 0xa0, 0, uart_irqhandle, 0)) {
return uwRet;
}
uart_interrupt_unmask();
return 0;
}
#endif
#endif
void uart_init()
{
unsigned int temp;
unsigned int divider;
unsigned char dividerH, dividerL;
/* disable UART1 FIFO */
WRITE_UINT32(0, UART_REG_BASE + UART_FCR); /*lint !e40*/
/* reset and enable UART1 FIFO */
WRITE_UINT32(0x7, UART_REG_BASE + UART_FCR); /*lint !e40*/
/* disable UART1 interrupt */
WRITE_UINT32(0, UART_REG_BASE + UART_IER); /*lint !e40*/
/* enable DLL and DLH */
WRITE_UINT32(0x80, UART_REG_BASE + UART_LCR); /*lint !e40*/
/* Caculate devide */
temp = 16 * CONSOLE_UART_BAUDRATE;
divider = CONFIG_UART_CLK_INPUT / temp;
dividerH = ((divider) & 0xff00) >> 8;
dividerL = ((divider) & 0x00ff);
/* configure DLL and DLH */
WRITE_UINT32(dividerL, UART_REG_BASE + UART_DLL); /*lint !e40*/
WRITE_UINT32(dividerH, UART_REG_BASE + UART_DLH); /*lint !e40*/
/* disable DLL and DLH */
WRITE_UINT32(0x0, UART_REG_BASE + UART_LCR); /*lint !e40*/
/* 8bit data, 1bit stop,even parity */
WRITE_UINT32(0x1b, UART_REG_BASE + UART_LCR); /*lint !e40*/
/* enable UART1 */
WRITE_UINT32(0x1, UART_REG_BASE + UART_IER); /*lint !e40*/
(VOID)LOS_EventInit(&g_uartEvent);
}
void uart_interrupt_unmask(void)
{
HalIrqUnmask(NUM_HAL_INTERRUPT_UART);
}

325
platform/usb/usb3.0_hi3516dv300/usb_board.c Executable file
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/*
* Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "hisoc/usb3.h"
#include "los_atomic.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
#define USB3_CTRL_REG_BASE IO_DEVICE_ADDR(CONFIG_HIUSB_XHCI_IOBASE)
#define REG_USB2_CTRL 0x0140
/* offset 0x140 */
#define USB2_UTMI_PCTRL (0x1U << 15)
#define USB2_PHY_TEST_SRST_REQ (0x1U << 14)
#define USB2_UTMI_CKSEL (0x1U << 13)
#define USB2_UTMI_CKEN (0x1U << 12)
#define USB2_REF_CKEN (0x1U << 9)
#define USB2_BUS_CKEN (0x1U << 8)
#define USB2_VCC_SRST_REQ (0x1U << 3)
#define USB2_PHY_CKEN (0x1U << 2)
#define USB2_PHY_PORT_TREQ (0x1U << 1)
#define USB2_PHY_REQ (0x1U << 0)
#define REG_GUSB3PIPECTL0 0xC2C0
#define PCS_SSP_SOFT_RESET (0x1U << 31)
#define PORT_DISABLE_SUSPEND (0x1U << 17)
#define REG_GCTL 0xC110
#define PORT_CAP_DIR (0x3U << 12)
#define PORT_SET_HOST (0x1U << 12)
#define PORT_SET_DEVICE (0x1U << 13)
#define GTXTHRCFG 0xC108
#define USB2_G_TXTHRCFG IO_DEVICE_ADDR(0x23100000)
#define GRXTHRCFG 0xC10C
#define USB2_G_RXTHRCFG IO_DEVICE_ADDR(0x23100000)
#define USB2_INNO_PHY_BASE_REG IO_DEVICE_ADDR(0x10110000)
#define USB2_PHY_CLK_OUTPUT_REG 0x18
#define USB2_PHY_CLK_OUTPUT_VAL 0x0C
#define USB2_VBUS_IO_BASE_REG IO_DEVICE_ADDR(0x10FF0000)
#define USB2_VBUS_IO_OFFSET 0x40
#define USB2_VBUS_IO_VAL 0x431
#define HS_HIGH_HEIGHT_TUNING_OFFSET 0x8
#define HS_HIGH_HEIGHT_TUNING_MASK (0x7U << 4)
#define HS_HIGH_HEIGHT_TUNING_VAL (0x5U << 4)
#define PRE_EMPHASIS_TUNING_OFFSET 0x0
#define PRE_EMPHASIS_TUNING_MASK (0x7U << 0)
#define PRE_EMPHASIS_TUNING_VAL (0x7U << 0)
#define PRE_EMPHASIS_STRENGTH_OFFSET 0x14
#define PRE_EMPHASIS_STRENGTH_MASK (0x7U << 2)
#define PRE_EMPHASIS_STRENGTH_VAL (0x3U << 2)
#define HS_SLEW_RATE_TUNING_OFFSET 0x74
#define HS_SLEW_RATE_TUNING_MASK (0x7U << 1)
#define HS_SLEW_RATE_TUNING_VAL (0x7U << 1)
#define DISCONNECT_TRIGGER_OFFSET 0x10
#define DISCONNECT_TRIGGER_MASK (0xfU << 4)
#define DISCONNECT_TRIGGER_VAL (0xdU << 4)
STATIC BOOL g_otgUsbdevStat = FALSE;
STATIC Atomic g_devOpenCnt = 0;
STATIC VOID OpenUtmi(VOID)
{
UINT32 reg;
/* open utmi pctrl */
reg = GET_UINT32(CRG_REG_BASE + REG_USB2_CTRL);
reg &= ~USB2_UTMI_PCTRL;
WRITE_UINT32(reg, CRG_REG_BASE + REG_USB2_CTRL);
LOS_Udelay(10); /* Delay 10us */
/* open utmi cksel */
reg = GET_UINT32(CRG_REG_BASE + REG_USB2_CTRL);
reg &= ~USB2_UTMI_CKSEL;
WRITE_UINT32(reg, CRG_REG_BASE + REG_USB2_CTRL);
LOS_Udelay(10); /* Delay 10us */
/* open utmi cken */
reg = GET_UINT32(CRG_REG_BASE + REG_USB2_CTRL);
reg |= USB2_UTMI_CKEN;
WRITE_UINT32(reg, CRG_REG_BASE + REG_USB2_CTRL);
LOS_Udelay(10); /* Delay 10us */
}
STATIC VOID CancelReset(VOID)
{
UINT32 reg;
/* cancel POR reset */
reg = GET_UINT32(CRG_REG_BASE + REG_USB2_CTRL);
reg &= ~USB2_PHY_REQ;
WRITE_UINT32(reg, CRG_REG_BASE + REG_USB2_CTRL);
LOS_Udelay(200); /* Delay 200us */
/* cancel TPOR reset */
reg = GET_UINT32(CRG_REG_BASE + REG_USB2_CTRL);
reg &= ~USB2_PHY_PORT_TREQ;
WRITE_UINT32(reg, CRG_REG_BASE + REG_USB2_CTRL);
LOS_Udelay(200); /* Delay 200us */
/* cancel vcc reset */
reg = GET_UINT32(CRG_REG_BASE + REG_USB2_CTRL);
reg &= ~USB2_VCC_SRST_REQ;
WRITE_UINT32(reg, CRG_REG_BASE + REG_USB2_CTRL);
LOS_Udelay(200); /* Delay 200us */
}
STATIC VOID Usb2ControllerConfig(VOID)
{
UINT32 reg;
reg = GET_UINT32(USB3_CTRL_REG_BASE + REG_GUSB3PIPECTL0);
reg |= PCS_SSP_SOFT_RESET;
WRITE_UINT32(reg, USB3_CTRL_REG_BASE + REG_GUSB3PIPECTL0);
LOS_Udelay(20); /* Delay 20us */
reg = GET_UINT32(USB3_CTRL_REG_BASE + REG_GCTL);
reg &= ~PORT_CAP_DIR;
reg |= PORT_SET_HOST; /* [13:12] 01: Host; 10: Device; 11: OTG */
WRITE_UINT32(reg, USB3_CTRL_REG_BASE + REG_GCTL);
LOS_Udelay(20); /* Delay 20us */
reg = GET_UINT32(USB3_CTRL_REG_BASE + REG_GUSB3PIPECTL0);
reg &= ~PCS_SSP_SOFT_RESET;
reg &= ~PORT_DISABLE_SUSPEND; /* disable suspend */
WRITE_UINT32(reg, USB3_CTRL_REG_BASE + REG_GUSB3PIPECTL0);
LOS_Udelay(20); /* Delay 20us */
WRITE_UINT32(USB2_G_TXTHRCFG, USB3_CTRL_REG_BASE + GTXTHRCFG);
WRITE_UINT32(USB2_G_RXTHRCFG, USB3_CTRL_REG_BASE + GRXTHRCFG);
LOS_Udelay(20); /* Delay 20us */
}
VOID Usb2EyeConfig(VOID)
{
UINT32 reg;
/* HS eye height tuning */
reg = GET_UINT32(USB2_INNO_PHY_BASE_REG + HS_HIGH_HEIGHT_TUNING_OFFSET);
reg &= ~HS_HIGH_HEIGHT_TUNING_MASK;
reg |= HS_HIGH_HEIGHT_TUNING_VAL;
WRITE_UINT32(reg, USB2_INNO_PHY_BASE_REG + HS_HIGH_HEIGHT_TUNING_OFFSET);
/* Pre-emphasis tuning */
reg = GET_UINT32(USB2_INNO_PHY_BASE_REG + PRE_EMPHASIS_TUNING_OFFSET);
reg &= ~PRE_EMPHASIS_TUNING_MASK;
reg |= PRE_EMPHASIS_TUNING_VAL;
WRITE_UINT32(reg, USB2_INNO_PHY_BASE_REG + PRE_EMPHASIS_TUNING_OFFSET);
/* Pre-emphasis strength */
reg = GET_UINT32(USB2_INNO_PHY_BASE_REG + PRE_EMPHASIS_STRENGTH_OFFSET);
reg &= ~PRE_EMPHASIS_STRENGTH_MASK;
reg |= PRE_EMPHASIS_STRENGTH_VAL;
WRITE_UINT32(reg, USB2_INNO_PHY_BASE_REG + PRE_EMPHASIS_STRENGTH_OFFSET);
/* HS driver slew rate tunning */
reg = GET_UINT32(USB2_INNO_PHY_BASE_REG + HS_SLEW_RATE_TUNING_OFFSET);
reg &= ~HS_SLEW_RATE_TUNING_MASK;
reg |= HS_SLEW_RATE_TUNING_VAL;
WRITE_UINT32(reg, USB2_INNO_PHY_BASE_REG + HS_SLEW_RATE_TUNING_OFFSET);
/* HOST disconnects detection trigger point */
reg = GET_UINT32(USB2_INNO_PHY_BASE_REG + DISCONNECT_TRIGGER_OFFSET);
reg &= ~DISCONNECT_TRIGGER_MASK;
reg |= DISCONNECT_TRIGGER_VAL;
WRITE_UINT32(reg, USB2_INNO_PHY_BASE_REG + DISCONNECT_TRIGGER_OFFSET);
}
STATIC VOID HisiUsb3PhyPowerOn(VOID)
{
UINT32 reg;
if (LOS_AtomicIncRet(&g_devOpenCnt) == 1) {
/* usb phy reset */
reg = GET_UINT32(CRG_REG_BASE + REG_USB2_CTRL);
reg |= USB2_PHY_TEST_SRST_REQ;
WRITE_UINT32(reg, CRG_REG_BASE + REG_USB2_CTRL);
LOS_Udelay(100); /* Delay 100us */
/* cancel usb phy srst */
reg = GET_UINT32(CRG_REG_BASE + REG_USB2_CTRL);
reg &= ~USB2_PHY_TEST_SRST_REQ;
WRITE_UINT32(reg, CRG_REG_BASE + REG_USB2_CTRL);
LOS_Udelay(20); /* Delay 20us */
/* usb2 vcc reset */
reg = GET_UINT32(CRG_REG_BASE + REG_USB2_CTRL);
reg |= USB2_VCC_SRST_REQ;
WRITE_UINT32(reg, CRG_REG_BASE + REG_USB2_CTRL);
LOS_Udelay(200); /* Delay 200us */
/* set inno phy output clock */
WRITE_UINT32(USB2_PHY_CLK_OUTPUT_VAL, USB2_INNO_PHY_BASE_REG +
USB2_PHY_CLK_OUTPUT_REG);
LOS_Udelay(10); /* Delay 10us */
/* open phy ref cken */
reg = GET_UINT32(CRG_REG_BASE + REG_USB2_CTRL);
reg |= USB2_PHY_CKEN;
WRITE_UINT32(reg, CRG_REG_BASE + REG_USB2_CTRL);
LOS_Udelay(10); /* Delay 10us */
/* open utmi */
OpenUtmi();
/* open controller ref cken */
reg = GET_UINT32(CRG_REG_BASE + REG_USB2_CTRL);
reg |= USB2_REF_CKEN;
WRITE_UINT32(reg, CRG_REG_BASE + REG_USB2_CTRL);
LOS_Udelay(10); /* Delay 10us */
/* open bus cken */
reg = GET_UINT32(CRG_REG_BASE + REG_USB2_CTRL);
reg |= USB2_BUS_CKEN;
WRITE_UINT32(reg, CRG_REG_BASE + REG_USB2_CTRL);
LOS_Udelay(200); /* Delay 200us */
/* cancel reset */
CancelReset();
/* usb2 test vbus using gpio */
WRITE_UINT32(USB2_VBUS_IO_VAL, USB2_VBUS_IO_BASE_REG + USB2_VBUS_IO_OFFSET);
LOS_Udelay(20); /* Delay 20us */
/* USB2 Controller configs */
Usb2ControllerConfig();
/* USB2 eye config */
Usb2EyeConfig();
}
}
STATIC VOID HisiUsb3PhyPowerOff(VOID)
{
UINT32 reg;
if (LOS_AtomicDecRet(&g_devOpenCnt) == 0) {
/* usb2 vcc reset */
reg = GET_UINT32(CRG_REG_BASE + REG_USB2_CTRL);
reg |= USB2_VCC_SRST_REQ;
WRITE_UINT32(reg, CRG_REG_BASE + REG_USB2_CTRL);
LOS_Udelay(200); /* Delay 200us */
}
}
VOID HiUsb3StartHcd(VOID)
{
HisiUsb3PhyPowerOn();
}
VOID HiUsb3StopHcd(VOID)
{
HisiUsb3PhyPowerOff();
}
VOID HiUsb3Host2Device(VOID)
{
UINT32 reg;
reg = GET_UINT32(USB3_CTRL_REG_BASE + REG_GCTL);
reg &= ~PORT_CAP_DIR;
reg |= PORT_SET_DEVICE; /* [13:12] 01: Host; 10: Device; 11: OTG */
WRITE_UINT32(reg, USB3_CTRL_REG_BASE + REG_GCTL);
LOS_Udelay(20); /* Delay 20us */
}
BOOL HiUsbIsDeviceMode(VOID)
{
return g_otgUsbdevStat;
}
VOID UsbOtgSwSetDeviceState(VOID)
{
g_otgUsbdevStat = TRUE;
}
VOID UsbOtgSwClearDeviceState(VOID)
{
g_otgUsbdevStat = FALSE;
}
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif

391
platform/usb/usb3.0_hi3518ev300/usb_board.c Executable file
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/*
* Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "hisoc/usb3.h"
#include "linux/delay.h"
#include "board.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
/* offset 0x140 */
#define USB2_CTRL IO_ADDRESS(CRG_REG_BASE + 0x140)
#define USB2_CRG_DEFAULT_VAL 0x3B2F
#define USB2_UTMI_CKEN (0x1U << 12)
#define USB2_PHY_APB_CKEN (0x1U << 11)
#define USB2_REF_CKEN (0x1U << 9)
#define USB2_BUS_CKEN (0x1U << 8)
#define USB2_PHY_PLL_CKEN (0x1U << 4)
#define USB2_PHY_XTAL_CKEN (0x1U << 2)
#define USB2_FREECLK_CKSEL (0x1U << 13)
#define USB2_PHY_APB_RST (0x1U << 10)
#define USB2_VCC_SRST_REQ (0x1U << 3)
#define USB2_PHY_REQ (0x1U << 0)
#define USB2_PHY_PORT_TREQ (0x1U << 1)
#define CTRL_BASE_REG IO_DEVICE_ADDR(0x10030000)
#define GTXTHRCFG IO_ADDRESS(CTRL_BASE_REG + 0xC108)
#define GRXTHRCFG IO_ADDRESS(CTRL_BASE_REG + 0xC10C)
#define REG_GCTL IO_ADDRESS(CTRL_BASE_REG + 0xC110)
#define REG_GUSB3PIPECTL0 IO_ADDRESS(CTRL_BASE_REG + 0xC2C0)
#define PCS_SSP_SOFT_RESET (0x1U << 31)
#define PORT_CAP_DIR (0x3U << 12)
#define PORT_SET_HOST (0x1U << 12)
#define PORT_SET_DEVICE (0x1U << 13)
#define PORT_DISABLE_SUSPEND (0x1U << 17)
#define USB2_G_TXTHRCFG 0x23100000
#define USB2_G_RXTHRCFG 0x23100000
/* PHY base register */
#define USB2_PHY_BASE_REG IO_DEVICE_ADDR(0x100D0000)
#define RG_PLL_EN_MASK 0x0003U
#define RG_PLL_EN_VAL 0x0003U
#define RG_PLL_OFFSET 0x0014
#define USB2_VBUS_IO_BASE_REG IO_DEVICE_ADDR(0x100C0000)
#define USB2_VBUS_IO_OFFSET 0x7C
#define USB_VBUS_IO_CONFIG_VAL 0x0531
#define USB_PWREN_CONFIG_REG IO_DEVICE_ADDR(0x100C0080)
#define USB_PWREN_CONFIG_VAL 0x1
/* PHY eye config */
#define HIXVP_PHY_ANA_CFG_0_OFFSET 0x00
#define HIXVP_PHY_PRE_DRIVE_MASK (0xFU << 24)
#define HIXVP_PHY_PRE_DRIVE_VAL (0x4U << 24)
#define HIXVP_PHY_ANA_CFG_2_OFFSET 0x08
#define HIXVP_PHY_TX_TEST_BIT (0x1U << 20)
#define HIXVP_PHY_DISCONNECT_REFERENCE_MASK (0x7U << 16)
#define HIXVP_PHY_DISCONNECT_REFERENCE_VAL (0x2U << 16)
#define HIXVP_PHY_ANA_CFG_4_OFFSET 0x10
#define HIXVP_PHY_TX_REFERENCE_MASK (0x7U << 4)
#define HIXVP_PHY_TX_REFERENCE_VAL (0x5U << 4)
#define HIXVP_PHY_SQUELCH_MASK (0x7U << 0)
#define HIXVP_PHY_SQUELCH_VAL (0x5U << 0)
/* PHY trim config */
#define USB_TRIM_BASE_REG IO_DEVICE_ADDR(0x12028004)
#define USB_TRIM_VAL_MASK 0x001FU
#define USB_TRIM_VAL_MIN 0x0009
#define USB_TRIM_VAL_MAX 0x001D
#define USB2_TRIM_OFFSET 0x0008
#define USB2_TRIM_MASK 0x1F00U
#define USB2_TRIM_VAL(a) (((a) << 8) & USB2_TRIM_MASK)
#define USB2_TRIM_DEFAULT_VAL 0x000EU
/* PHY svb config */
#define USB_SVB_BASE_REG IO_DEVICE_ADDR(0x12020158)
#define USB_SVB_OFFSET 0x00
#define USB_SVB_MASK (0x0FU << 24)
#define USB_SVB_PREDEV_5_MIN 0x2BC
#define USB_SVB_PREDEV_5_MAX_4_MIN 0x32A
#define USB_SVB_PREDEV_4_MAX_3_MIN 0x398
#define USB_SVB_PREDEV_3_MAX_2_MIN 0x3CA
#define USB_SVB_PREDEV_2_MAX 0x44C
#define USB_SVB_PREDEV_5_PHY_VAL (0x05U << 24)
#define USB_SVB_PREDEV_4_PHY_VAL (0x04U << 24)
#define USB_SVB_PREDEV_3_PHY_VAL (0x03U << 24)
#define USB_SVB_PREDEV_2_PHY_VAL (0x02U << 24)
#define VBUS_CONFIG_WAIT_TIME 20
#define CTRL_CONFIG_WAIT_TIME 20
#define MODE_SWITCH_WAIT_TIME 20
#define USB_PHY_OFF_WAIT_TIME 2000
#define PLL_CONFIG_WAIT_TIME 2000
#define USB2_CTRL_CONFIG_WAIT_TIME 200
STATIC BOOL g_otgUsbdevStat = FALSE;
STATIC VOID UsbEyeConfig(VOID)
{
UINT32 reg;
/* HSTX pre-drive strength */
reg = GET_UINT32(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_0_OFFSET);
reg &= ~HIXVP_PHY_PRE_DRIVE_MASK;
reg |= HIXVP_PHY_PRE_DRIVE_VAL;
WRITE_UINT32(reg, USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_0_OFFSET);
/* TX test bit */
reg = GET_UINT32(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_2_OFFSET);
reg |= HIXVP_PHY_TX_TEST_BIT;
WRITE_UINT32(reg, USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_2_OFFSET);
/* Disconnect reference voltage sel */
reg = GET_UINT32(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_2_OFFSET);
reg &= ~HIXVP_PHY_DISCONNECT_REFERENCE_MASK;
reg |= HIXVP_PHY_DISCONNECT_REFERENCE_VAL;
WRITE_UINT32(reg, USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_2_OFFSET);
/* TX reference voltage sel */
reg = GET_UINT32(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_4_OFFSET);
reg &= ~HIXVP_PHY_TX_REFERENCE_MASK;
reg |= HIXVP_PHY_TX_REFERENCE_VAL;
WRITE_UINT32(reg, USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_4_OFFSET);
/* Squelch voltage config */
reg = GET_UINT32(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_4_OFFSET);
reg &= ~HIXVP_PHY_SQUELCH_MASK;
reg |= HIXVP_PHY_SQUELCH_VAL;
WRITE_UINT32(reg, USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_4_OFFSET);
}
VOID UsbTrimConfig(VOID)
{
UINT32 ret, reg, trimVal;
ret = GET_UINT32(USB_TRIM_BASE_REG);
trimVal = ret & USB_TRIM_VAL_MASK; /* get usb trim value */
reg = GET_UINT32(USB2_PHY_BASE_REG + USB2_TRIM_OFFSET);
reg &= ~USB2_TRIM_MASK;
/* set trim value to HiXVPV100 phy */
if ((trimVal >= USB_TRIM_VAL_MIN) && (trimVal <= USB_TRIM_VAL_MAX)) {
reg |= USB2_TRIM_VAL(trimVal);
} else {
reg |= USB2_TRIM_VAL(USB2_TRIM_DEFAULT_VAL);
}
WRITE_UINT32(reg, USB2_PHY_BASE_REG + USB2_TRIM_OFFSET);
}
VOID UsbSvbConfig(VOID)
{
UINT32 ret, reg;
ret = GET_UINT32(USB_SVB_BASE_REG);
reg = GET_UINT32(USB2_PHY_BASE_REG + USB_SVB_OFFSET);
reg &= ~USB_SVB_MASK;
/* set svb value to HiXVPV100 phy */
if ((ret >= USB_SVB_PREDEV_5_MIN) && (ret < USB_SVB_PREDEV_5_MAX_4_MIN)) {
reg |= USB_SVB_PREDEV_5_PHY_VAL;
} else if ((ret >= USB_SVB_PREDEV_5_MAX_4_MIN) && (ret < USB_SVB_PREDEV_4_MAX_3_MIN)) {
reg |= USB_SVB_PREDEV_4_PHY_VAL;
} else if ((ret >= USB_SVB_PREDEV_4_MAX_3_MIN) && (ret <= USB_SVB_PREDEV_3_MAX_2_MIN)) {
reg |= USB_SVB_PREDEV_3_PHY_VAL;
} else if ((ret > USB_SVB_PREDEV_3_MAX_2_MIN) && (ret <= USB_SVB_PREDEV_2_MAX)) {
reg |= USB_SVB_PREDEV_2_PHY_VAL;
} else {
reg |= USB_SVB_PREDEV_4_PHY_VAL;
}
WRITE_UINT32(reg, USB2_PHY_BASE_REG + USB_SVB_OFFSET);
}
STATIC VOID UsbVbusConfig(VOID)
{
WRITE_UINT32(USB_VBUS_IO_CONFIG_VAL, USB2_VBUS_IO_BASE_REG + USB2_VBUS_IO_OFFSET);
udelay(VBUS_CONFIG_WAIT_TIME);
}
STATIC VOID UsbCrgC(VOID)
{
UINT32 reg;
reg = USB_PWREN_CONFIG_VAL;
WRITE_UINT32(reg, USB_PWREN_CONFIG_REG);
/* set usb2 CRG default val */
reg = USB2_CRG_DEFAULT_VAL;
WRITE_UINT32(reg, USB2_CTRL);
udelay(USB2_CTRL_CONFIG_WAIT_TIME);
/* open UTMI clk */
reg = GET_UINT32(USB2_CTRL);
reg |= USB2_UTMI_CKEN;
WRITE_UINT32(reg, USB2_CTRL);
/* open phy apb clk */
reg = GET_UINT32(USB2_CTRL);
reg |= USB2_PHY_APB_CKEN;
WRITE_UINT32(reg, USB2_CTRL);
/* open ctrl ref clk */
reg = GET_UINT32(USB2_CTRL);
reg |= USB2_REF_CKEN;
WRITE_UINT32(reg, USB2_CTRL);
/* open bus clk */
reg = GET_UINT32(USB2_CTRL);
reg |= USB2_BUS_CKEN;
WRITE_UINT32(reg, USB2_CTRL);
/* open phy pll clk */
reg = GET_UINT32(USB2_CTRL);
reg |= USB2_PHY_PLL_CKEN;
WRITE_UINT32(reg, USB2_CTRL);
/* open phy xtal clk */
reg = GET_UINT32(USB2_CTRL);
reg |= USB2_PHY_XTAL_CKEN;
WRITE_UINT32(reg, USB2_CTRL);
/* freeclk_cksel_free */
reg = GET_UINT32(USB2_CTRL);
reg |= USB2_FREECLK_CKSEL;
WRITE_UINT32(reg, USB2_CTRL);
udelay(USB2_CTRL_CONFIG_WAIT_TIME);
/* release phy apb */
reg = GET_UINT32(USB2_CTRL);
reg &= ~USB2_PHY_APB_RST;
WRITE_UINT32(reg, USB2_CTRL);
udelay(USB2_CTRL_CONFIG_WAIT_TIME);
/* por noreset */
reg = GET_UINT32(USB2_CTRL);
reg &= ~USB2_PHY_REQ;
WRITE_UINT32(reg, USB2_CTRL);
reg = GET_UINT32(USB2_PHY_BASE_REG + RG_PLL_OFFSET);
reg &= ~RG_PLL_EN_MASK;
reg |= RG_PLL_EN_VAL;
WRITE_UINT32(reg, USB2_PHY_BASE_REG + RG_PLL_OFFSET);
udelay(PLL_CONFIG_WAIT_TIME);
/* cancel TPOR */
reg = GET_UINT32(USB2_CTRL);
reg &= ~USB2_PHY_PORT_TREQ;
WRITE_UINT32(reg, USB2_CTRL);
udelay(USB2_CTRL_CONFIG_WAIT_TIME);
/* vcc reset */
reg = GET_UINT32(USB2_CTRL);
reg &= ~USB2_VCC_SRST_REQ;
WRITE_UINT32(reg, USB2_CTRL);
}
STATIC VOID UsbCtrlC(VOID)
{
UINT32 reg;
reg = GET_UINT32(REG_GUSB3PIPECTL0);
reg |= PCS_SSP_SOFT_RESET;
WRITE_UINT32(reg, REG_GUSB3PIPECTL0);
udelay(CTRL_CONFIG_WAIT_TIME);
reg = GET_UINT32(REG_GCTL);
reg &= ~PORT_CAP_DIR;
reg |= PORT_SET_HOST; /* [13:12] 01: Host; 10: Device; 11: OTG */
WRITE_UINT32(reg, REG_GCTL);
udelay(CTRL_CONFIG_WAIT_TIME);
reg = GET_UINT32(REG_GUSB3PIPECTL0);
reg &= ~PCS_SSP_SOFT_RESET;
reg &= ~PORT_DISABLE_SUSPEND; /* disable suspend */
WRITE_UINT32(reg, REG_GUSB3PIPECTL0);
udelay(CTRL_CONFIG_WAIT_TIME);
WRITE_UINT32(USB2_G_TXTHRCFG, GTXTHRCFG);
WRITE_UINT32(USB2_G_RXTHRCFG, GRXTHRCFG);
udelay(CTRL_CONFIG_WAIT_TIME);
}
VOID HisiUsbPhyOn(VOID)
{
UsbVbusConfig();
UsbCrgC();
UsbCtrlC();
/* USB2 eye config */
UsbEyeConfig();
/* USB2 trim config */
UsbTrimConfig();
/* USB2 svb config */
UsbSvbConfig();
}
VOID HisiUsbPhyOff(VOID)
{
UINT32 reg;
/* por noreset */
reg = GET_UINT32(USB2_CTRL);
reg &= ~USB2_PHY_REQ;
WRITE_UINT32(reg, USB2_CTRL);
udelay(USB_PHY_OFF_WAIT_TIME);
/* cancel TPOR */
reg = GET_UINT32(USB2_CTRL);
reg &= ~USB2_PHY_PORT_TREQ;
WRITE_UINT32(reg, USB2_CTRL);
udelay(USB_PHY_OFF_WAIT_TIME);
/* vcc reset */
reg = GET_UINT32(USB2_CTRL);
reg &= ~USB2_VCC_SRST_REQ;
WRITE_UINT32(reg, USB2_CTRL);
}
VOID HiUsb3StartHcd(VOID)
{
HisiUsbPhyOn();
}
VOID HiUsb3StopHcd(VOID)
{
HisiUsbPhyOff();
}
VOID HiUsb3Host2Device(VOID)
{
UINT32 reg;
reg = GET_UINT32(REG_GCTL);
reg &= ~PORT_CAP_DIR; /* [13:12] Clear Mode Bits */
reg |= PORT_SET_DEVICE; /* [13:12] 01: Host; 10: Device; 11: OTG */
WRITE_UINT32(reg, REG_GCTL);
udelay(MODE_SWITCH_WAIT_TIME);
}
BOOL HiUsbIsDeviceMode(VOID)
{
return g_otgUsbdevStat;
}
VOID UsbOtgSwSetDeviceState(VOID)
{
g_otgUsbdevStat = TRUE;
}
VOID UsbOtgSwClearDeviceState(VOID)
{
g_otgUsbdevStat = FALSE;
}
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif