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IssueNo: #I3EPPI

Browse Source 
Description: platform directory refactoring
Sig: kernel
Feature or Bugfix: Feature
Binary Source: No
This commit is contained in:
likailong
2021-04-02 08:18:25 +08:00
parent 90b9c37b66
commit 3fe7ec0200
21 changed files with 83 additions and 1531 deletions
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123
arch/arm/include/gic_common.h Normal file
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/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _GIC_COMMON_H
#define _GIC_COMMON_H
#include "stdint.h"
#include "target_config.h"
#include "los_config.h"
/* gic arch revision */
enum {
GICV1 = 1,
GICV2,
GICV3,
GICV4
};
#define GIC_REV_MASK 0xF0
#define GIC_REV_OFFSET 0x4
#ifdef LOSCFG_PLATFORM_BSP_GIC_V2
#define GICC_CTLR (GICC_OFFSET + 0x00) /* CPU Interface Control Register */
#define GICC_PMR (GICC_OFFSET + 0x04) /* Interrupt Priority Mask Register */
#define GICC_BPR (GICC_OFFSET + 0x08) /* Binary Point Register */
#define GICC_IAR (GICC_OFFSET + 0x0c) /* Interrupt Acknowledge Register */
#define GICC_EOIR (GICC_OFFSET + 0x10) /* End of Interrupt Register */
#define GICC_RPR (GICC_OFFSET + 0x14) /* Running Priority Register */
#define GICC_HPPIR (GICC_OFFSET + 0x18) /* Highest Priority Pending Interrupt Register */
#endif
#define GICD_CTLR (GICD_OFFSET + 0x000) /* Distributor Control Register */
#define GICD_TYPER (GICD_OFFSET + 0x004) /* Interrupt Controller Type Register */
#define GICD_IIDR (GICD_OFFSET + 0x008) /* Distributor Implementer Identification Register */
#define GICD_IGROUPR(n) (GICD_OFFSET + 0x080 + (n) * 4) /* Interrupt Group Registers */
#define GICD_ISENABLER(n) (GICD_OFFSET + 0x100 + (n) * 4) /* Interrupt Set-Enable Registers */
#define GICD_ICENABLER(n) (GICD_OFFSET + 0x180 + (n) * 4) /* Interrupt Clear-Enable Registers */
#define GICD_ISPENDR(n) (GICD_OFFSET + 0x200 + (n) * 4) /* Interrupt Set-Pending Registers */
#define GICD_ICPENDR(n) (GICD_OFFSET + 0x280 + (n) * 4) /* Interrupt Clear-Pending Registers */
#define GICD_ISACTIVER(n) (GICD_OFFSET + 0x300 + (n) * 4) /* GICv2 Interrupt Set-Active Registers */
#define GICD_ICACTIVER(n) (GICD_OFFSET + 0x380 + (n) * 4) /* Interrupt Clear-Active Registers */
#define GICD_IPRIORITYR(n) (GICD_OFFSET + 0x400 + (n) * 4) /* Interrupt Priority Registers */
#define GICD_ITARGETSR(n) (GICD_OFFSET + 0x800 + (n) * 4) /* Interrupt Processor Targets Registers */
#define GICD_ICFGR(n) (GICD_OFFSET + 0xc00 + (n) * 4) /* Interrupt Configuration Registers */
#define GICD_SGIR (GICD_OFFSET + 0xf00) /* Software Generated Interrupt Register */
#define GICD_CPENDSGIR(n) (GICD_OFFSET + 0xf10 + (n) * 4) /* SGI Clear-Pending Registers; NOT available on cortex-a9 */
#define GICD_SPENDSGIR(n) (GICD_OFFSET + 0xf20 + (n) * 4) /* SGI Set-Pending Registers; NOT available on cortex-a9 */
#define GICD_PIDR2V2 (GICD_OFFSET + 0xfe8)
#define GICD_PIDR2V3 (GICD_OFFSET + 0xffe8)
#ifdef LOSCFG_PLATFORM_BSP_GIC_V3
#define GICD_IGRPMODR(n) (GICD_OFFSET + 0x0d00 + (n) * 4) /* Interrupt Group Mode Reisters */
#define GICD_IROUTER(n) (GICD_OFFSET + 0x6000 + (n) * 8) /* Interrupt Rounter Reisters */
#endif
#define GIC_REG_8(reg) (*(volatile UINT8 *)((UINTPTR)(GIC_BASE_ADDR + (reg))))
#define GIC_REG_32(reg) (*(volatile UINT32 *)((UINTPTR)(GIC_BASE_ADDR + (reg))))
#define GIC_REG_64(reg) (*(volatile UINT64 *)((UINTPTR)(GIC_BASE_ADDR + (reg))))
#define GICD_INT_DEF_PRI 0xa0U
#define GICD_INT_DEF_PRI_X4 (((UINT32)GICD_INT_DEF_PRI << 24) | \
((UINT32)GICD_INT_DEF_PRI << 16) | \
((UINT32)GICD_INT_DEF_PRI << 8) | \
(UINT32)GICD_INT_DEF_PRI)
#define GIC_MIN_SPI_NUM 32
/* Interrupt preemption config */
#define GIC_PRIORITY_MASK 0xFFU
#define GIC_PRIORITY_OFFSET 8
/*
* The number of bits to shift for an interrupt priority is dependent
* on the number of bits implemented by the interrupt controller.
* If the MAX_BINARY_POINT_VALUE is 7,
* it means that interrupt preemption is not supported.
*/
#ifndef LOSCFG_ARCH_INTERRUPT_PREEMPTION
#define MAX_BINARY_POINT_VALUE 7
#define PRIORITY_SHIFT 0
#define GIC_MAX_INTERRUPT_PREEMPTION_LEVEL 0U
#else
#define PRIORITY_SHIFT ((MAX_BINARY_POINT_VALUE + 1) % GIC_PRIORITY_OFFSET)
#define GIC_MAX_INTERRUPT_PREEMPTION_LEVEL ((UINT8)((GIC_PRIORITY_MASK + 1) >> PRIORITY_SHIFT))
#endif
#define GIC_INTR_PRIO_MASK ((UINT8)(0xFFFFFFFFU << PRIORITY_SHIFT))
/*
* The preemption level is up to 128, and the maximum value corresponding to the interrupt priority is 254 [7:1].
* If the GIC_MAX_INTERRUPT_PREEMPTION_LEVEL is 0, the minimum priority is 0xff.
*/
#define MIN_INTERRUPT_PRIORITY ((UINT8)((GIC_MAX_INTERRUPT_PREEMPTION_LEVEL - 1) << PRIORITY_SHIFT))
#endif

203
arch/arm/include/gic_v3.h Normal file
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/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _GIC_V3_H_
#define _GIC_V3_H_
#include "stdint.h"
#include "target_config.h"
#include "los_hw_cpu.h"
#define BIT_32(bit) (1u << bit)
#define BIT_64(bit) (1ul << bit)
#define ICC_CTLR_EL1 "S3_0_C12_C12_4"
#define ICC_PMR_EL1 "S3_0_C4_C6_0"
#define ICC_IAR1_EL1 "S3_0_C12_C12_0"
#define ICC_SRE_EL1 "S3_0_C12_C12_5"
#define ICC_BPR0_EL1 "S3_0_C12_C8_3"
#define ICC_BPR1_EL1 "S3_0_C12_C12_3"
#define ICC_IGRPEN0_EL1 "S3_0_C12_C12_6"
#define ICC_IGRPEN1_EL1 "S3_0_C12_C12_7"
#define ICC_EOIR1_EL1 "S3_0_C12_C12_1"
#define ICC_SGI1R_EL1 "S3_0_C12_C11_5"
#define ICC_EOIR0_EL1 "S3_0_c12_c8_1"
#define ICC_IAR0_EL1 "S3_0_C12_C8_0"
#define ICC_CTLR_EL3 "S3_6_C12_C12_4"
#define ICC_SRE_EL3 "S3_6_C12_C12_5"
#define ICC_IGRPEN1_EL3 "S3_6_C12_C12_7"
/* GICD_CTLR bit definitions */
#define CTLR_ENALBE_G0 BIT_32(0)
#define CTLR_ENABLE_G1NS BIT_32(1)
#define CTLR_ENABLE_G1S BIT_32(2)
#define CTLR_RES0 BIT_32(3)
#define CTLR_ARE_S BIT_32(4)
#define CTLR_ARE_NS BIT_32(5)
#define CTLR_DS BIT_32(6)
#define CTLR_E1NWF BIT_32(7)
#define GICD_CTLR_RWP BIT_32(31)
/* peripheral identification registers */
#define GICD_CIDR0 (GICD_OFFSET + 0xfff0)
#define GICD_CIDR1 (GICD_OFFSET + 0xfff4)
#define GICD_CIDR2 (GICD_OFFSET + 0xfff8)
#define GICD_CIDR3 (GICD_OFFSET + 0xfffc)
#define GICD_PIDR0 (GICD_OFFSET + 0xffe0)
#define GICD_PIDR1 (GICD_OFFSET + 0xffe4)
#define GICD_PIDR2 (GICD_OFFSET + 0xffe8)
#define GICD_PIDR3 (GICD_OFFSET + 0xffec)
/* GICD_PIDR bit definitions and masks */
#define GICD_PIDR2_ARCHREV_SHIFT 4
#define GICD_PIDR2_ARCHREV_MASK 0xf
/* redistributor registers */
#define GICR_SGI_OFFSET (GICR_OFFSET + 0x10000)
#define GICR_CTLR(i) (GICR_OFFSET + GICR_STRIDE * (i) + 0x0000)
#define GICR_IIDR(i) (GICR_OFFSET + GICR_STRIDE * (i) + 0x0004)
#define GICR_TYPER(i, n) (GICR_OFFSET + GICR_STRIDE * (i) + 0x0008 + (n)*4)
#define GICR_STATUSR(i) (GICR_OFFSET + GICR_STRIDE * (i) + 0x0010)
#define GICR_WAKER(i) (GICR_OFFSET + GICR_STRIDE * (i) + 0x0014)
#define GICR_IGROUPR0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0080)
#define GICR_IGRPMOD0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0d00)
#define GICR_ISENABLER0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0100)
#define GICR_ICENABLER0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0180)
#define GICR_ISPENDR0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0200)
#define GICR_ICPENDR0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0280)
#define GICR_ISACTIVER0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0300)
#define GICR_ICACTIVER0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0380)
#define GICR_IPRIORITYR0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0400)
#define GICR_ICFGR0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0c00)
#define GICR_ICFGR1(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0c04)
#define GICR_NSACR(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0e00)
#define GICR_WAKER_PROCESSORSLEEP_LEN 1U
#define GICR_WAKER_PROCESSORSLEEP_OFFSET 1
#define GICR_WAKER_CHILDRENASLEEP_LEN 1U
#define GICR_WAKER_CHILDRENASLEEP_OFFSET 2
#define GICR_WAKER_PROCESSORSLEEP (GICR_WAKER_PROCESSORSLEEP_LEN << GICR_WAKER_PROCESSORSLEEP_OFFSET)
#define GICR_WAKER_CHILDRENASLEEP (GICR_WAKER_CHILDRENASLEEP_LEN << GICR_WAKER_CHILDRENASLEEP_OFFSET)
STATIC INLINE VOID GiccSetCtlr(UINT32 val)
{
#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
__asm__ volatile("msr " ICC_CTLR_EL3 ", %0" ::"r"(val));
#else
__asm__ volatile("msr " ICC_CTLR_EL1 ", %0" ::"r"(val));
#endif
ISB;
}
STATIC INLINE VOID GiccSetPmr(UINT32 val)
{
__asm__ volatile("msr " ICC_PMR_EL1 ", %0" ::"r"(val));
ISB;
DSB;
}
STATIC INLINE VOID GiccSetIgrpen0(UINT32 val)
{
__asm__ volatile("msr " ICC_IGRPEN0_EL1 ", %0" ::"r"(val));
ISB;
}
STATIC INLINE VOID GiccSetIgrpen1(UINT32 val)
{
#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
__asm__ volatile("msr " ICC_IGRPEN1_EL3 ", %0" ::"r"(val));
#else
__asm__ volatile("msr " ICC_IGRPEN1_EL1 ", %0" ::"r"(val));
#endif
ISB;
}
STATIC INLINE UINT32 GiccGetSre(VOID)
{
UINT32 temp;
#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
__asm__ volatile("mrs %0, " ICC_SRE_EL3 : "=r"(temp));
#else
__asm__ volatile("mrs %0, " ICC_SRE_EL1 : "=r"(temp));
#endif
return temp;
}
STATIC INLINE VOID GiccSetSre(UINT32 val)
{
#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
__asm__ volatile("msr " ICC_SRE_EL3 ", %0" ::"r"(val));
#else
__asm__ volatile("msr " ICC_SRE_EL1 ", %0" ::"r"(val));
#endif
ISB;
}
STATIC INLINE VOID GiccSetEoir(UINT32 val)
{
#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
__asm__ volatile("msr " ICC_EOIR0_EL1 ", %0" ::"r"(val));
#else
__asm__ volatile("msr " ICC_EOIR1_EL1 ", %0" ::"r"(val));
#endif
ISB;
}
STATIC INLINE UINT32 GiccGetIar(VOID)
{
UINT32 temp;
#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
__asm__ volatile("mrs %0, " ICC_IAR0_EL1 : "=r"(temp));
#else
__asm__ volatile("mrs %0, " ICC_IAR1_EL1 : "=r"(temp));
#endif
DSB;
return temp;
}
STATIC INLINE VOID GiccSetSgi1r(UINT64 val)
{
__asm__ volatile("msr " ICC_SGI1R_EL1 ", %0" ::"r"(val));
ISB;
DSB;
}
STATIC INLINE VOID GiccSetBpr0(UINT32 val)
{
__asm__ volatile("msr " ICC_BPR0_EL1 ", %0" ::"r"(val));
ISB;
DSB;
}
#endif

63
arch/arm/include/hal_hwi.h Normal file
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/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _HWI_H
#define _HWI_H
#include "los_typedef.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
extern VOID HalIrqInit(VOID);
extern VOID HalIrqInitPercpu(VOID);
extern VOID HalIrqMask(UINT32 vector);
extern VOID HalIrqUnmask(UINT32 vector);
extern VOID HalIrqPending(UINT32 vector);
extern VOID HalIrqClear(UINT32 vector);
extern CHAR *HalIrqVersion(VOID);
extern UINT32 HalCurIrqGet(VOID);
extern UINT32 HalIrqSetPrio(UINT32 vector, UINT8 priority);
#if (LOSCFG_KERNEL_SMP == YES)
extern VOID HalIrqSendIpi(UINT32 target, UINT32 ipi);
extern VOID HalIrqSetAffinity(UINT32 vector, UINT32 cpuMask);
#endif
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _HWI_H */