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IssueNo: #I3EPPI

Browse Source 
Description: platform directory refactoring
Sig: kernel
Feature or Bugfix: Feature
Binary Source: No
This commit is contained in:
likailong
2021-04-02 08:18:25 +08:00
parent 90b9c37b66
commit 3fe7ec0200
21 changed files with 83 additions and 1531 deletions
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26
arch/arm/Kconfig
View File

@@ -75,3 +75,29 @@ config ARCH_CORTEX_A7
config ARCH_CPU
string
default "cortex-a7" if ARCH_CORTEX_A7
#
# Supported GIC version
#
choice
prompt "GIC version"
default PLATFORM_BSP_GIC_V2
help
Interrupt Controller.
config PLATFORM_BSP_GIC_V2
bool "GIC Version 2"
help
This GIC(General Interrupt Controller) version 2 driver is compatatble with
GIC version 1 and version 2.
config PLATFORM_BSP_GIC_V3
bool "GIC Version 3"
depends on ARCH_ARM_V8A || ARCH_ARM_V8R
help
General Interrupt Controller version 3.
endchoice

3
arch/arm/arm.mk
View File

@@ -42,7 +42,10 @@ LITEOS_ARCH_ARM :=
endif
LITEOS_BASELIB += -l$(LOSCFG_ARCH_CPU)
LITEOS_BASELIB += -lgic
LIB_SUBDIRS += arch/arm/$(LITEOS_ARCH_ARM)
LIB_SUBDIRS += arch/arm/gic
# CPU compile options
ifeq ($(LOSCFG_ARCH_ARM_AARCH64), y)

65
arch/arm/arm/include/hal_timer.h Normal file
View File

@@ -0,0 +1,65 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_TIMER_H
#define _LOS_TIMER_H
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
extern UINT32 HalClockFreqRead(VOID);
extern VOID HalClockFreqWrite(UINT32 freq);
extern VOID HalClockStart(VOID);
extern VOID HalClockIrqClear(VOID);
extern VOID HalClockInit(VOID);
extern UINT64 HalClockGetCycles(VOID);
extern VOID HalDelayUs(UINT32 usecs);
extern UINT64 hi_sched_clock(VOID);
extern UINT32 HalClockGetTickTimerCycles(VOID);
extern VOID HalClockTickTimerReload(UINT64 cycles);
extern UINT32 HrtimersInit(VOID);
extern VOID HrtimerClockIrqClear(VOID);
extern VOID HrtimerClockStart(UINT32 period);
extern VOID HrtimerClockStop(VOID);
extern UINT32 HrtimerClockValueGet(VOID);
extern VOID HrtimerClockInit(VOID);
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_TIMER_H */

188
arch/arm/arm/src/arm_generic_timer.c Normal file
View File

@@ -0,0 +1,188 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_hw_pri.h"
#include "los_tick_pri.h"
#include "los_sched_pri.h"
#include "los_sys_pri.h"
#include "gic_common.h"
#define STRING_COMB(x, y, z) x ## y ## z
#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
#define TIMER_REG(reg) STRING_COMB(TIMER_REG_, CNTPS, reg)
#else
#define TIMER_REG(reg) STRING_COMB(TIMER_REG_, CNTP, reg)
#endif
#define TIMER_REG_CTL TIMER_REG(_CTL) /* 32 bits */
#define TIMER_REG_TVAL TIMER_REG(_TVAL) /* 32 bits */
#define TIMER_REG_CVAL TIMER_REG(_CVAL) /* 64 bits */
#define TIMER_REG_CT TIMER_REG(CT) /* 64 bits */
#ifdef __LP64__
#define TIMER_REG_CNTFRQ cntfrq_el0
/* CNTP AArch64 registers */
#define TIMER_REG_CNTP_CTL cntp_ctl_el0
#define TIMER_REG_CNTP_TVAL cntp_tval_el0
#define TIMER_REG_CNTP_CVAL cntp_cval_el0
#define TIMER_REG_CNTPCT cntpct_el0
/* CNTPS AArch64 registers */
#define TIMER_REG_CNTPS_CTL cntps_ctl_el1
#define TIMER_REG_CNTPS_TVAL cntps_tval_el1
#define TIMER_REG_CNTPS_CVAL cntps_cval_el1
#define TIMER_REG_CNTPSCT cntpct_el0
#define READ_TIMER_REG32(reg) AARCH64_SYSREG_READ(reg)
#define READ_TIMER_REG64(reg) AARCH64_SYSREG_READ(reg)
#define WRITE_TIMER_REG32(reg, val) AARCH64_SYSREG_WRITE(reg, (UINT64)(val))
#define WRITE_TIMER_REG64(reg, val) AARCH64_SYSREG_WRITE(reg, val)
#else /* Aarch32 */
#define TIMER_REG_CNTFRQ CP15_REG(c14, 0, c0, 0)
/* CNTP AArch32 registers */
#define TIMER_REG_CNTP_CTL CP15_REG(c14, 0, c2, 1)
#define TIMER_REG_CNTP_TVAL CP15_REG(c14, 0, c2, 0)
#define TIMER_REG_CNTP_CVAL CP15_REG64(c14, 2)
#define TIMER_REG_CNTPCT CP15_REG64(c14, 0)
/* CNTPS AArch32 registers are banked and accessed though CNTP */
#define CNTPS CNTP
#define READ_TIMER_REG32(reg) ARM_SYSREG_READ(reg)
#define READ_TIMER_REG64(reg) ARM_SYSREG64_READ(reg)
#define WRITE_TIMER_REG32(reg, val) ARM_SYSREG_WRITE(reg, val)
#define WRITE_TIMER_REG64(reg, val) ARM_SYSREG64_WRITE(reg, val)
#endif
UINT32 HalClockFreqRead(VOID)
{
return READ_TIMER_REG32(TIMER_REG_CNTFRQ);
}
VOID HalClockFreqWrite(UINT32 freq)
{
WRITE_TIMER_REG32(TIMER_REG_CNTFRQ, freq);
}
STATIC_INLINE VOID TimerCtlWrite(UINT32 cntpCtl)
{
WRITE_TIMER_REG32(TIMER_REG_CTL, cntpCtl);
}
STATIC_INLINE UINT64 TimerCvalRead(VOID)
{
return READ_TIMER_REG64(TIMER_REG_CVAL);
}
STATIC_INLINE VOID TimerCvalWrite(UINT64 cval)
{
WRITE_TIMER_REG64(TIMER_REG_CVAL, cval);
}
STATIC_INLINE VOID TimerTvalWrite(UINT32 tval)
{
WRITE_TIMER_REG32(TIMER_REG_TVAL, tval);
}
UINT64 HalClockGetCycles(VOID)
{
UINT64 cntpct;
cntpct = READ_TIMER_REG64(TIMER_REG_CT);
return cntpct;
}
LITE_OS_SEC_TEXT_INIT VOID HalClockInit(VOID)
{
UINT32 ret;
g_sysClock = HalClockFreqRead();
ret = LOS_HwiCreate(OS_TICK_INT_NUM, MIN_INTERRUPT_PRIORITY, 0, OsTickHandler, 0);
if (ret != LOS_OK) {
PRINT_ERR("%s, %d create tick irq failed, ret:0x%x\n", __FUNCTION__, __LINE__, ret);
}
}
LITE_OS_SEC_TEXT_INIT VOID HalClockStart(VOID)
{
UINT32 ret = OsSchedSetTickTimerType(64); /* 64 bit tick timer */
if (ret != LOS_OK) {
return;
}
HalIrqUnmask(OS_TICK_INT_NUM);
/* triggle the first tick */
TimerCtlWrite(0);
TimerTvalWrite(OS_CYCLE_PER_TICK);
TimerCtlWrite(1);
}
VOID HalDelayUs(UINT32 usecs)
{
UINT64 cycles = (UINT64)usecs * g_sysClock / OS_SYS_US_PER_SECOND;
UINT64 deadline = HalClockGetCycles() + cycles;
while (HalClockGetCycles() < deadline) {
__asm__ volatile ("nop");
}
}
UINT64 hi_sched_clock(VOID)
{
return LOS_CurrNanosec();
}
UINT32 HalClockGetTickTimerCycles(VOID)
{
UINT64 cval = TimerCvalRead();
UINT64 cycles = HalClockGetCycles();
return (UINT32)((cval > cycles) ? (cval - cycles) : 0);
}
VOID HalClockTickTimerReload(UINT64 cycles)
{
HalIrqMask(OS_TICK_INT_NUM);
HalIrqClear(OS_TICK_INT_NUM);
TimerCtlWrite(0);
TimerCvalWrite(HalClockGetCycles() + cycles);
TimerCtlWrite(1);
HalIrqUnmask(OS_TICK_INT_NUM);
}

4
arch/arm/arm/src/los_hw_tick.c
View File

@@ -65,9 +65,9 @@ LITE_OS_SEC_TEXT_MINOR VOID LOS_GetCpuCycle(UINT32 *highCnt, UINT32 *lowCnt)
LITE_OS_SEC_TEXT_MINOR UINT64 LOS_CurrNanosec(VOID)
{
DOUBLE nanos;
UINT64 nanos;
nanos = (DOUBLE)HalClockGetCycles() * OS_SYS_NS_PER_SECOND / g_sysClock;
nanos = (UINT64)HalClockGetCycles() * OS_SYS_NS_PER_SECOND / g_sysClock;
return (UINT64)nanos;
}

48
arch/arm/gic/Makefile Executable file
View File

@@ -0,0 +1,48 @@
# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without modification,
# are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice, this list of
# conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice, this list
# of conditions and the following disclaimer in the documentation and/or other materials
# provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its contributors may be used
# to endorse or promote products derived from this software without specific prior written
# permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
include $(LITEOSTOPDIR)/config.mk
MODULE_NAME := $(notdir $(shell pwd))
# LOCAL_SRCS := $(wildcard *.c)
ifeq ($(LOSCFG_PLATFORM_BSP_GIC_V2), y)
LOCAL_SRCS := gic_v2.c
else ifeq ($(LOSCFG_PLATFORM_BSP_GIC_V3), y)
LOCAL_SRCS := gic_v3.c
endif
LOCAL_INCLUDE := \
-I $(LITEOSTOPDIR)/kernel/base/include \
-I $(LITEOSTOPDIR)/arch/arm/include \
-I $(LITEOSTOPDIR)/arch/arm/arm/src/include \
LOCAL_FLAGS := $(LOCAL_INCLUDE)
include $(MODULE)

194
arch/arm/gic/gic_v2.c Normal file
View File

@@ -0,0 +1,194 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "gic_common.h"
#include "los_hwi.h"
#include "los_hwi_pri.h"
#include "los_mp.h"
STATIC_ASSERT(OS_USER_HWI_MAX <= 1020, "hwi max is too large!");
#ifdef LOSCFG_PLATFORM_BSP_GIC_V2
STATIC UINT32 g_curIrqNum = 0;
#if (LOSCFG_KERNEL_SMP == YES)
/*
* filter description
* 0b00: forward to the cpu interfaces specified in cpu_mask
* 0b01: forward to all cpu interfaces
* 0b10: forward only to the cpu interface that request the irq
*/
STATIC VOID GicWriteSgi(UINT32 vector, UINT32 cpuMask, UINT32 filter)
{
UINT32 val = ((filter & 0x3) << 24) | ((cpuMask & 0xFF) << 16) |
(vector & 0xF);
GIC_REG_32(GICD_SGIR) = val;
}
VOID HalIrqSendIpi(UINT32 target, UINT32 ipi)
{
GicWriteSgi(ipi, target, 0);
}
VOID HalIrqSetAffinity(UINT32 vector, UINT32 cpuMask)
{
UINT32 offset = vector / 4;
UINT32 index = vector & 0x3;
GIC_REG_8(GICD_ITARGETSR(offset) + index) = cpuMask;
}
#endif
UINT32 HalCurIrqGet(VOID)
{
return g_curIrqNum;
}
VOID HalIrqMask(UINT32 vector)
{
if ((vector > OS_USER_HWI_MAX) || (vector < OS_USER_HWI_MIN)) {
return;
}
GIC_REG_32(GICD_ICENABLER(vector / 32)) = 1U << (vector % 32);
}
VOID HalIrqUnmask(UINT32 vector)
{
if ((vector > OS_USER_HWI_MAX) || (vector < OS_USER_HWI_MIN)) {
return;
}
GIC_REG_32(GICD_ISENABLER(vector >> 5)) = 1U << (vector % 32);
}
VOID HalIrqPending(UINT32 vector)
{
if ((vector > OS_USER_HWI_MAX) || (vector < OS_USER_HWI_MIN)) {
return;
}
GIC_REG_32(GICD_ISPENDR(vector >> 5)) = 1U << (vector % 32);
}
VOID HalIrqClear(UINT32 vector)
{
GIC_REG_32(GICC_EOIR) = vector;
}
VOID HalIrqInitPercpu(VOID)
{
/* unmask interrupts */
GIC_REG_32(GICC_PMR) = 0xFF;
/* enable gic cpu interface */
GIC_REG_32(GICC_CTLR) = 1;
}
VOID HalIrqInit(VOID)
{
UINT32 i;
/* set externel interrupts to be level triggered, active low. */
for (i = 32; i < OS_HWI_MAX_NUM; i += 16) {
GIC_REG_32(GICD_ICFGR(i / 16)) = 0;
}
/* set externel interrupts to CPU 0 */
for (i = 32; i < OS_HWI_MAX_NUM; i += 4) {
GIC_REG_32(GICD_ITARGETSR(i / 4)) = 0x01010101;
}
/* set priority on all interrupts */
for (i = 0; i < OS_HWI_MAX_NUM; i += 4) {
GIC_REG_32(GICD_IPRIORITYR(i / 4)) = GICD_INT_DEF_PRI_X4;
}
/* disable all interrupts. */
for (i = 0; i < OS_HWI_MAX_NUM; i += 32) {
GIC_REG_32(GICD_ICENABLER(i / 32)) = ~0;
}
HalIrqInitPercpu();
/* enable gic distributor control */
GIC_REG_32(GICD_CTLR) = 1;
#if (LOSCFG_KERNEL_SMP == YES)
/* register inter-processor interrupt */
(VOID)LOS_HwiCreate(LOS_MP_IPI_WAKEUP, 0xa0, 0, OsMpWakeHandler, 0);
(VOID)LOS_HwiCreate(LOS_MP_IPI_SCHEDULE, 0xa0, 0, OsMpScheduleHandler, 0);
(VOID)LOS_HwiCreate(LOS_MP_IPI_HALT, 0xa0, 0, OsMpHaltHandler, 0);
#endif
}
VOID HalIrqHandler(VOID)
{
UINT32 iar = GIC_REG_32(GICC_IAR);
UINT32 vector = iar & 0x3FFU;
/*
* invalid irq number, mainly the spurious interrupts 0x3ff,
* gicv2 valid irq ranges from 0~1019, we use OS_HWI_MAX_NUM
* to do the checking.
*/
if (vector >= OS_HWI_MAX_NUM) {
return;
}
g_curIrqNum = vector;
OsInterrupt(vector);
/* use orignal iar to do the EOI */
GIC_REG_32(GICC_EOIR) = iar;
}
CHAR *HalIrqVersion(VOID)
{
UINT32 pidr = GIC_REG_32(GICD_PIDR2V2);
CHAR *irqVerString = NULL;
switch (pidr >> GIC_REV_OFFSET) {
case GICV1:
irqVerString = "GICv1";
break;
case GICV2:
irqVerString = "GICv2";
break;
default:
irqVerString = "unknown";
}
return irqVerString;
}
#endif

447
arch/arm/gic/gic_v3.c Normal file
View File

@@ -0,0 +1,447 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "gic_common.h"
#include "gic_v3.h"
#include "los_typedef.h"
#include "los_hwi.h"
#include "los_hwi_pri.h"
#include "los_mp.h"
#ifdef LOSCFG_PLATFORM_BSP_GIC_V3
STATIC UINT32 g_curIrqNum = 0;
STATIC INLINE UINT64 MpidrToAffinity(UINT64 mpidr)
{
return ((MPIDR_AFF_LEVEL(mpidr, 3) << 32) |
(MPIDR_AFF_LEVEL(mpidr, 2) << 16) |
(MPIDR_AFF_LEVEL(mpidr, 1) << 8) |
(MPIDR_AFF_LEVEL(mpidr, 0)));
}
#if (LOSCFG_KERNEL_SMP == YES)
STATIC UINT32 NextCpu(UINT32 cpu, UINT32 cpuMask)
{
UINT32 next = cpu + 1;
while (next < LOSCFG_KERNEL_CORE_NUM) {
if (cpuMask & (1U << next)) {
goto OUT;
}
next++;
}
OUT:
return next;
}
STATIC UINT16 GicTargetList(UINT32 *base, UINT32 cpuMask, UINT64 cluster)
{
UINT32 nextCpu;
UINT16 tList = 0;
UINT32 cpu = *base;
UINT64 mpidr = CPU_MAP_GET(cpu);
while (cpu < LOSCFG_KERNEL_CORE_NUM) {
tList |= 1U << (mpidr & 0xf);
nextCpu = NextCpu(cpu, cpuMask);
if (nextCpu >= LOSCFG_KERNEL_CORE_NUM) {
goto out;
}
cpu = nextCpu;
mpidr = CPU_MAP_GET(cpu);
if (cluster != (mpidr & ~0xffUL)) {
cpu--;
goto out;
}
}
out:
*base = cpu;
return tList;
}
STATIC VOID GicSgi(UINT32 irq, UINT32 cpuMask)
{
UINT16 tList;
UINT32 cpu = 0;
UINT64 val, cluster;
while (cpuMask && (cpu < LOSCFG_KERNEL_CORE_NUM)) {
if (cpuMask & (1U << cpu)) {
cluster = CPU_MAP_GET(cpu) & ~0xffUL;
tList = GicTargetList(&cpu, cpuMask, cluster);
/* Generates a Group 1 interrupt for the current security state */
val = ((MPIDR_AFF_LEVEL(cluster, 3) << 48) |
(MPIDR_AFF_LEVEL(cluster, 2) << 32) |
(MPIDR_AFF_LEVEL(cluster, 1) << 16) |
(irq << 24) | tList);
GiccSetSgi1r(val);
}
cpu++;
}
}
VOID HalIrqSendIpi(UINT32 target, UINT32 ipi)
{
GicSgi(ipi, target);
}
VOID HalIrqSetAffinity(UINT32 irq, UINT32 cpuMask)
{
UINT64 affinity = MpidrToAffinity(NextCpu(0, cpuMask));
/* When ARE is on, use router */
GIC_REG_64(GICD_IROUTER(irq)) = affinity;
}
#endif
STATIC VOID GicWaitForRwp(UINT64 reg)
{
INT32 count = 1000000; /* 1s */
while (GIC_REG_32(reg) & GICD_CTLR_RWP) {
count -= 1;
if (!count) {
PRINTK("gic_v3: rwp timeout 0x%x\n", GIC_REG_32(reg));
return;
}
}
}
STATIC INLINE VOID GicdSetGroup(UINT32 irq)
{
/* configure spi as group 0 on secure mode and group 1 on unsecure mode */
#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
GIC_REG_32(GICD_IGROUPR(irq / 32)) = 0;
#else
GIC_REG_32(GICD_IGROUPR(irq / 32)) = 0xffffffff;
#endif
}
STATIC INLINE VOID GicrSetWaker(UINT32 cpu)
{
GIC_REG_32(GICR_WAKER(cpu)) &= ~GICR_WAKER_PROCESSORSLEEP;
DSB;
ISB;
while ((GIC_REG_32(GICR_WAKER(cpu)) & 0x4) == GICR_WAKER_CHILDRENASLEEP);
}
STATIC INLINE VOID GicrSetGroup(UINT32 cpu)
{
/* configure sgi/ppi as group 0 on secure mode and group 1 on unsecure mode */
#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
GIC_REG_32(GICR_IGROUPR0(cpu)) = 0;
GIC_REG_32(GICR_IGRPMOD0(cpu)) = 0;
#else
GIC_REG_32(GICR_IGROUPR0(cpu)) = 0xffffffff;
#endif
}
STATIC VOID GicdSetPmr(UINT32 irq, UINT8 priority)
{
UINT32 pos = irq >> 2; /* one irq have the 8-bit interrupt priority field */
UINT32 newPri = GIC_REG_32(GICD_IPRIORITYR(pos));
/* Shift and mask the correct bits for the priority */
newPri &= ~(GIC_PRIORITY_MASK << ((irq % 4) * GIC_PRIORITY_OFFSET));
newPri |= priority << ((irq % 4) * GIC_PRIORITY_OFFSET);
GIC_REG_32(GICD_IPRIORITYR(pos)) = newPri;
}
STATIC VOID GicrSetPmr(UINT32 irq, UINT8 priority)
{
UINT32 cpu = ArchCurrCpuid();
UINT32 pos = irq >> 2; /* one irq have the 8-bit interrupt priority field */
UINT32 newPri = GIC_REG_32(GICR_IPRIORITYR0(cpu) + pos * 4);
/* Clear priority offset bits and set new priority */
newPri &= ~(GIC_PRIORITY_MASK << ((irq % 4) * GIC_PRIORITY_OFFSET));
newPri |= priority << ((irq % 4) * GIC_PRIORITY_OFFSET);
GIC_REG_32(GICR_IPRIORITYR0(cpu) + pos * 4) = newPri;
}
STATIC VOID GiccInitPercpu(VOID)
{
/* enable system register interface */
UINT32 sre = GiccGetSre();
if (!(sre & 0x1)) {
GiccSetSre(sre | 0x1);
/*
* Need to check that the SRE bit has actually been set. If
* not, it means that SRE is disabled at up EL level. We're going to
* die painfully, and there is nothing we can do about it.
*/
sre = GiccGetSre();
LOS_ASSERT(sre & 0x1);
}
#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
/* Enable group 0 and disable grp1ns grp1s interrupts */
GiccSetIgrpen0(1);
GiccSetIgrpen1(0);
/*
* For priority grouping.
* The value of this field control show the 8-bit interrupt priority field
* is split into a group priority field, that determines interrupt preemption,
* and a subpriority field.
*/
GiccSetBpr0(MAX_BINARY_POINT_VALUE);
#else
/* enable group 1 interrupts */
GiccSetIgrpen1(1);
#endif
/* set priority threshold to max */
GiccSetPmr(0xff);
/* EOI deactivates interrupt too (mode 0) */
GiccSetCtlr(0);
}
UINT32 HalCurIrqGet(VOID)
{
return g_curIrqNum;
}
VOID HalIrqMask(UINT32 vector)
{
INT32 i;
const UINT32 mask = 1U << (vector % 32);
if ((vector > OS_USER_HWI_MAX) || (vector < OS_USER_HWI_MIN)) {
return;
}
if (vector < 32) {
for (i = 0; i < LOSCFG_KERNEL_CORE_NUM; i++) {
GIC_REG_32(GICR_ICENABLER0(i)) = mask;
GicWaitForRwp(GICR_CTLR(i));
}
} else {
GIC_REG_32(GICD_ICENABLER(vector >> 5)) = mask;
GicWaitForRwp(GICD_CTLR);
}
}
VOID HalIrqUnmask(UINT32 vector)
{
INT32 i;
const UINT32 mask = 1U << (vector % 32);
if ((vector > OS_USER_HWI_MAX) || (vector < OS_USER_HWI_MIN)) {
return;
}
if (vector < 32) {
for (i = 0; i < LOSCFG_KERNEL_CORE_NUM; i++) {
GIC_REG_32(GICR_ISENABLER0(i)) = mask;
GicWaitForRwp(GICR_CTLR(i));
}
} else {
GIC_REG_32(GICD_ISENABLER(vector >> 5)) = mask;
GicWaitForRwp(GICD_CTLR);
}
}
VOID HalIrqPending(UINT32 vector)
{
if ((vector > OS_USER_HWI_MAX) || (vector < OS_USER_HWI_MIN)) {
return;
}
GIC_REG_32(GICD_ISPENDR(vector >> 5)) = 1U << (vector % 32);
}
VOID HalIrqClear(UINT32 vector)
{
GiccSetEoir(vector);
ISB;
}
UINT32 HalIrqSetPrio(UINT32 vector, UINT8 priority)
{
UINT8 prio = priority;
if (vector > OS_HWI_MAX_NUM) {
PRINT_ERR("Invalid irq value %u, max irq is %u\n", vector, OS_HWI_MAX_NUM);
return LOS_NOK;
}
prio = prio & (UINT8)GIC_INTR_PRIO_MASK;
if (vector >= GIC_MIN_SPI_NUM) {
GicdSetPmr(vector, prio);
} else {
GicrSetPmr(vector, prio);
}
return LOS_OK;
}
VOID HalIrqInitPercpu(VOID)
{
INT32 idx;
UINT32 cpu = ArchCurrCpuid();
/* GICR init */
GicrSetWaker(cpu);
GicrSetGroup(cpu);
GicWaitForRwp(GICR_CTLR(cpu));
/* GICR: clear and mask sgi/ppi */
GIC_REG_32(GICR_ICENABLER0(cpu)) = 0xffffffff;
GIC_REG_32(GICR_ICPENDR0(cpu)) = 0xffffffff;
GIC_REG_32(GICR_ISENABLER0(cpu)) = 0xffffffff;
for (idx = 0; idx < GIC_MIN_SPI_NUM; idx += 1) {
GicrSetPmr(idx, MIN_INTERRUPT_PRIORITY);
}
GicWaitForRwp(GICR_CTLR(cpu));
/* GICC init */
GiccInitPercpu();
#ifdef LOSCFG_KERNEL_SMP
/* unmask ipi interrupts */
HalIrqUnmask(LOS_MP_IPI_WAKEUP);
HalIrqUnmask(LOS_MP_IPI_HALT);
#endif
}
VOID HalIrqInit(VOID)
{
UINT32 i;
UINT64 affinity;
/* disable distributor */
GIC_REG_32(GICD_CTLR) = 0;
GicWaitForRwp(GICD_CTLR);
ISB;
/* set externel interrupts to be level triggered, active low. */
for (i = 32; i < OS_HWI_MAX_NUM; i += 16) {
GIC_REG_32(GICD_ICFGR(i / 16)) = 0;
}
/* config distributer, mask and clear all spis, set group x */
for (i = 32; i < OS_HWI_MAX_NUM; i += 32) {
GIC_REG_32(GICD_ICENABLER(i / 32)) = 0xffffffff;
GIC_REG_32(GICD_ICPENDR(i / 32)) = 0xffffffff;
GIC_REG_32(GICD_IGRPMODR(i / 32)) = 0;
GicdSetGroup(i);
}
/* set spi priority as default */
for (i = 32; i < OS_HWI_MAX_NUM; i++) {
GicdSetPmr(i, MIN_INTERRUPT_PRIORITY);
}
GicWaitForRwp(GICD_CTLR);
/* disable all interrupts. */
for (i = 0; i < OS_HWI_MAX_NUM; i += 32) {
GIC_REG_32(GICD_ICENABLER(i / 32)) = 0xffffffff;
}
/* enable distributor with ARE, group 1 enabled */
GIC_REG_32(GICD_CTLR) = CTLR_ENALBE_G0 | CTLR_ENABLE_G1NS | CTLR_ARE_S;
/* set spi to boot cpu only. ARE must be enabled */
affinity = MpidrToAffinity(AARCH64_SYSREG_READ(mpidr_el1));
for (i = 32; i < OS_HWI_MAX_NUM; i++) {
GIC_REG_64(GICD_IROUTER(i)) = affinity;
}
HalIrqInitPercpu();
#if (LOSCFG_KERNEL_SMP == YES)
/* register inter-processor interrupt */
LOS_HwiCreate(LOS_MP_IPI_WAKEUP, 0xa0, 0, OsMpWakeHandler, 0);
LOS_HwiCreate(LOS_MP_IPI_SCHEDULE, 0xa0, 0, OsMpScheduleHandler, 0);
LOS_HwiCreate(LOS_MP_IPI_HALT, 0xa0, 0, OsMpScheduleHandler, 0);
#endif
}
VOID HalIrqHandler(VOID)
{
UINT32 iar = GiccGetIar();
UINT32 vector = iar & 0x3FFU;
/*
* invalid irq number, mainly the spurious interrupts 0x3ff,
* valid irq ranges from 0~1019, we use OS_HWI_MAX_NUM to do
* the checking.
*/
if (vector >= OS_HWI_MAX_NUM) {
return;
}
g_curIrqNum = vector;
OsInterrupt(vector);
GiccSetEoir(vector);
}
CHAR *HalIrqVersion(VOID)
{
UINT32 pidr = GIC_REG_32(GICD_PIDR2V3);
CHAR *irqVerString = NULL;
switch (pidr >> GIC_REV_OFFSET) {
case GICV3:
irqVerString = "GICv3";
break;
case GICV4:
irqVerString = "GICv4";
break;
default:
irqVerString = "unknown";
}
return irqVerString;
}
#endif

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/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _GIC_COMMON_H
#define _GIC_COMMON_H
#include "stdint.h"
#include "target_config.h"
#include "los_config.h"
/* gic arch revision */
enum {
GICV1 = 1,
GICV2,
GICV3,
GICV4
};
#define GIC_REV_MASK 0xF0
#define GIC_REV_OFFSET 0x4
#ifdef LOSCFG_PLATFORM_BSP_GIC_V2
#define GICC_CTLR (GICC_OFFSET + 0x00) /* CPU Interface Control Register */
#define GICC_PMR (GICC_OFFSET + 0x04) /* Interrupt Priority Mask Register */
#define GICC_BPR (GICC_OFFSET + 0x08) /* Binary Point Register */
#define GICC_IAR (GICC_OFFSET + 0x0c) /* Interrupt Acknowledge Register */
#define GICC_EOIR (GICC_OFFSET + 0x10) /* End of Interrupt Register */
#define GICC_RPR (GICC_OFFSET + 0x14) /* Running Priority Register */
#define GICC_HPPIR (GICC_OFFSET + 0x18) /* Highest Priority Pending Interrupt Register */
#endif
#define GICD_CTLR (GICD_OFFSET + 0x000) /* Distributor Control Register */
#define GICD_TYPER (GICD_OFFSET + 0x004) /* Interrupt Controller Type Register */
#define GICD_IIDR (GICD_OFFSET + 0x008) /* Distributor Implementer Identification Register */
#define GICD_IGROUPR(n) (GICD_OFFSET + 0x080 + (n) * 4) /* Interrupt Group Registers */
#define GICD_ISENABLER(n) (GICD_OFFSET + 0x100 + (n) * 4) /* Interrupt Set-Enable Registers */
#define GICD_ICENABLER(n) (GICD_OFFSET + 0x180 + (n) * 4) /* Interrupt Clear-Enable Registers */
#define GICD_ISPENDR(n) (GICD_OFFSET + 0x200 + (n) * 4) /* Interrupt Set-Pending Registers */
#define GICD_ICPENDR(n) (GICD_OFFSET + 0x280 + (n) * 4) /* Interrupt Clear-Pending Registers */
#define GICD_ISACTIVER(n) (GICD_OFFSET + 0x300 + (n) * 4) /* GICv2 Interrupt Set-Active Registers */
#define GICD_ICACTIVER(n) (GICD_OFFSET + 0x380 + (n) * 4) /* Interrupt Clear-Active Registers */
#define GICD_IPRIORITYR(n) (GICD_OFFSET + 0x400 + (n) * 4) /* Interrupt Priority Registers */
#define GICD_ITARGETSR(n) (GICD_OFFSET + 0x800 + (n) * 4) /* Interrupt Processor Targets Registers */
#define GICD_ICFGR(n) (GICD_OFFSET + 0xc00 + (n) * 4) /* Interrupt Configuration Registers */
#define GICD_SGIR (GICD_OFFSET + 0xf00) /* Software Generated Interrupt Register */
#define GICD_CPENDSGIR(n) (GICD_OFFSET + 0xf10 + (n) * 4) /* SGI Clear-Pending Registers; NOT available on cortex-a9 */
#define GICD_SPENDSGIR(n) (GICD_OFFSET + 0xf20 + (n) * 4) /* SGI Set-Pending Registers; NOT available on cortex-a9 */
#define GICD_PIDR2V2 (GICD_OFFSET + 0xfe8)
#define GICD_PIDR2V3 (GICD_OFFSET + 0xffe8)
#ifdef LOSCFG_PLATFORM_BSP_GIC_V3
#define GICD_IGRPMODR(n) (GICD_OFFSET + 0x0d00 + (n) * 4) /* Interrupt Group Mode Reisters */
#define GICD_IROUTER(n) (GICD_OFFSET + 0x6000 + (n) * 8) /* Interrupt Rounter Reisters */
#endif
#define GIC_REG_8(reg) (*(volatile UINT8 *)((UINTPTR)(GIC_BASE_ADDR + (reg))))
#define GIC_REG_32(reg) (*(volatile UINT32 *)((UINTPTR)(GIC_BASE_ADDR + (reg))))
#define GIC_REG_64(reg) (*(volatile UINT64 *)((UINTPTR)(GIC_BASE_ADDR + (reg))))
#define GICD_INT_DEF_PRI 0xa0U
#define GICD_INT_DEF_PRI_X4 (((UINT32)GICD_INT_DEF_PRI << 24) | \
((UINT32)GICD_INT_DEF_PRI << 16) | \
((UINT32)GICD_INT_DEF_PRI << 8) | \
(UINT32)GICD_INT_DEF_PRI)
#define GIC_MIN_SPI_NUM 32
/* Interrupt preemption config */
#define GIC_PRIORITY_MASK 0xFFU
#define GIC_PRIORITY_OFFSET 8
/*
* The number of bits to shift for an interrupt priority is dependent
* on the number of bits implemented by the interrupt controller.
* If the MAX_BINARY_POINT_VALUE is 7,
* it means that interrupt preemption is not supported.
*/
#ifndef LOSCFG_ARCH_INTERRUPT_PREEMPTION
#define MAX_BINARY_POINT_VALUE 7
#define PRIORITY_SHIFT 0
#define GIC_MAX_INTERRUPT_PREEMPTION_LEVEL 0U
#else
#define PRIORITY_SHIFT ((MAX_BINARY_POINT_VALUE + 1) % GIC_PRIORITY_OFFSET)
#define GIC_MAX_INTERRUPT_PREEMPTION_LEVEL ((UINT8)((GIC_PRIORITY_MASK + 1) >> PRIORITY_SHIFT))
#endif
#define GIC_INTR_PRIO_MASK ((UINT8)(0xFFFFFFFFU << PRIORITY_SHIFT))
/*
* The preemption level is up to 128, and the maximum value corresponding to the interrupt priority is 254 [7:1].
* If the GIC_MAX_INTERRUPT_PREEMPTION_LEVEL is 0, the minimum priority is 0xff.
*/
#define MIN_INTERRUPT_PRIORITY ((UINT8)((GIC_MAX_INTERRUPT_PREEMPTION_LEVEL - 1) << PRIORITY_SHIFT))
#endif

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/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _GIC_V3_H_
#define _GIC_V3_H_
#include "stdint.h"
#include "target_config.h"
#include "los_hw_cpu.h"
#define BIT_32(bit) (1u << bit)
#define BIT_64(bit) (1ul << bit)
#define ICC_CTLR_EL1 "S3_0_C12_C12_4"
#define ICC_PMR_EL1 "S3_0_C4_C6_0"
#define ICC_IAR1_EL1 "S3_0_C12_C12_0"
#define ICC_SRE_EL1 "S3_0_C12_C12_5"
#define ICC_BPR0_EL1 "S3_0_C12_C8_3"
#define ICC_BPR1_EL1 "S3_0_C12_C12_3"
#define ICC_IGRPEN0_EL1 "S3_0_C12_C12_6"
#define ICC_IGRPEN1_EL1 "S3_0_C12_C12_7"
#define ICC_EOIR1_EL1 "S3_0_C12_C12_1"
#define ICC_SGI1R_EL1 "S3_0_C12_C11_5"
#define ICC_EOIR0_EL1 "S3_0_c12_c8_1"
#define ICC_IAR0_EL1 "S3_0_C12_C8_0"
#define ICC_CTLR_EL3 "S3_6_C12_C12_4"
#define ICC_SRE_EL3 "S3_6_C12_C12_5"
#define ICC_IGRPEN1_EL3 "S3_6_C12_C12_7"
/* GICD_CTLR bit definitions */
#define CTLR_ENALBE_G0 BIT_32(0)
#define CTLR_ENABLE_G1NS BIT_32(1)
#define CTLR_ENABLE_G1S BIT_32(2)
#define CTLR_RES0 BIT_32(3)
#define CTLR_ARE_S BIT_32(4)
#define CTLR_ARE_NS BIT_32(5)
#define CTLR_DS BIT_32(6)
#define CTLR_E1NWF BIT_32(7)
#define GICD_CTLR_RWP BIT_32(31)
/* peripheral identification registers */
#define GICD_CIDR0 (GICD_OFFSET + 0xfff0)
#define GICD_CIDR1 (GICD_OFFSET + 0xfff4)
#define GICD_CIDR2 (GICD_OFFSET + 0xfff8)
#define GICD_CIDR3 (GICD_OFFSET + 0xfffc)
#define GICD_PIDR0 (GICD_OFFSET + 0xffe0)
#define GICD_PIDR1 (GICD_OFFSET + 0xffe4)
#define GICD_PIDR2 (GICD_OFFSET + 0xffe8)
#define GICD_PIDR3 (GICD_OFFSET + 0xffec)
/* GICD_PIDR bit definitions and masks */
#define GICD_PIDR2_ARCHREV_SHIFT 4
#define GICD_PIDR2_ARCHREV_MASK 0xf
/* redistributor registers */
#define GICR_SGI_OFFSET (GICR_OFFSET + 0x10000)
#define GICR_CTLR(i) (GICR_OFFSET + GICR_STRIDE * (i) + 0x0000)
#define GICR_IIDR(i) (GICR_OFFSET + GICR_STRIDE * (i) + 0x0004)
#define GICR_TYPER(i, n) (GICR_OFFSET + GICR_STRIDE * (i) + 0x0008 + (n)*4)
#define GICR_STATUSR(i) (GICR_OFFSET + GICR_STRIDE * (i) + 0x0010)
#define GICR_WAKER(i) (GICR_OFFSET + GICR_STRIDE * (i) + 0x0014)
#define GICR_IGROUPR0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0080)
#define GICR_IGRPMOD0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0d00)
#define GICR_ISENABLER0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0100)
#define GICR_ICENABLER0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0180)
#define GICR_ISPENDR0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0200)
#define GICR_ICPENDR0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0280)
#define GICR_ISACTIVER0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0300)
#define GICR_ICACTIVER0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0380)
#define GICR_IPRIORITYR0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0400)
#define GICR_ICFGR0(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0c00)
#define GICR_ICFGR1(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0c04)
#define GICR_NSACR(i) (GICR_SGI_OFFSET + GICR_STRIDE * (i) + 0x0e00)
#define GICR_WAKER_PROCESSORSLEEP_LEN 1U
#define GICR_WAKER_PROCESSORSLEEP_OFFSET 1
#define GICR_WAKER_CHILDRENASLEEP_LEN 1U
#define GICR_WAKER_CHILDRENASLEEP_OFFSET 2
#define GICR_WAKER_PROCESSORSLEEP (GICR_WAKER_PROCESSORSLEEP_LEN << GICR_WAKER_PROCESSORSLEEP_OFFSET)
#define GICR_WAKER_CHILDRENASLEEP (GICR_WAKER_CHILDRENASLEEP_LEN << GICR_WAKER_CHILDRENASLEEP_OFFSET)
STATIC INLINE VOID GiccSetCtlr(UINT32 val)
{
#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
__asm__ volatile("msr " ICC_CTLR_EL3 ", %0" ::"r"(val));
#else
__asm__ volatile("msr " ICC_CTLR_EL1 ", %0" ::"r"(val));
#endif
ISB;
}
STATIC INLINE VOID GiccSetPmr(UINT32 val)
{
__asm__ volatile("msr " ICC_PMR_EL1 ", %0" ::"r"(val));
ISB;
DSB;
}
STATIC INLINE VOID GiccSetIgrpen0(UINT32 val)
{
__asm__ volatile("msr " ICC_IGRPEN0_EL1 ", %0" ::"r"(val));
ISB;
}
STATIC INLINE VOID GiccSetIgrpen1(UINT32 val)
{
#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
__asm__ volatile("msr " ICC_IGRPEN1_EL3 ", %0" ::"r"(val));
#else
__asm__ volatile("msr " ICC_IGRPEN1_EL1 ", %0" ::"r"(val));
#endif
ISB;
}
STATIC INLINE UINT32 GiccGetSre(VOID)
{
UINT32 temp;
#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
__asm__ volatile("mrs %0, " ICC_SRE_EL3 : "=r"(temp));
#else
__asm__ volatile("mrs %0, " ICC_SRE_EL1 : "=r"(temp));
#endif
return temp;
}
STATIC INLINE VOID GiccSetSre(UINT32 val)
{
#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
__asm__ volatile("msr " ICC_SRE_EL3 ", %0" ::"r"(val));
#else
__asm__ volatile("msr " ICC_SRE_EL1 ", %0" ::"r"(val));
#endif
ISB;
}
STATIC INLINE VOID GiccSetEoir(UINT32 val)
{
#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
__asm__ volatile("msr " ICC_EOIR0_EL1 ", %0" ::"r"(val));
#else
__asm__ volatile("msr " ICC_EOIR1_EL1 ", %0" ::"r"(val));
#endif
ISB;
}
STATIC INLINE UINT32 GiccGetIar(VOID)
{
UINT32 temp;
#ifdef LOSCFG_ARCH_SECURE_MONITOR_MODE
__asm__ volatile("mrs %0, " ICC_IAR0_EL1 : "=r"(temp));
#else
__asm__ volatile("mrs %0, " ICC_IAR1_EL1 : "=r"(temp));
#endif
DSB;
return temp;
}
STATIC INLINE VOID GiccSetSgi1r(UINT64 val)
{
__asm__ volatile("msr " ICC_SGI1R_EL1 ", %0" ::"r"(val));
ISB;
DSB;
}
STATIC INLINE VOID GiccSetBpr0(UINT32 val)
{
__asm__ volatile("msr " ICC_BPR0_EL1 ", %0" ::"r"(val));
ISB;
DSB;
}
#endif

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/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _HWI_H
#define _HWI_H
#include "los_typedef.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
extern VOID HalIrqInit(VOID);
extern VOID HalIrqInitPercpu(VOID);
extern VOID HalIrqMask(UINT32 vector);
extern VOID HalIrqUnmask(UINT32 vector);
extern VOID HalIrqPending(UINT32 vector);
extern VOID HalIrqClear(UINT32 vector);
extern CHAR *HalIrqVersion(VOID);
extern UINT32 HalCurIrqGet(VOID);
extern UINT32 HalIrqSetPrio(UINT32 vector, UINT8 priority);
#if (LOSCFG_KERNEL_SMP == YES)
extern VOID HalIrqSendIpi(UINT32 target, UINT32 ipi);
extern VOID HalIrqSetAffinity(UINT32 vector, UINT32 cpuMask);
#endif
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _HWI_H */