From 29dde5d752e99d8ec151c5df99ba0c251332258d Mon Sep 17 00:00:00 2001 From: arvinzzz Date: Wed, 9 Mar 2022 16:23:03 +0800 Subject: [PATCH] =?UTF-8?q?refactor:=20=E5=90=AF=E5=8A=A8=E5=8A=A0?= =?UTF-8?q?=E6=B3=A8=E9=87=8A?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: arvinzzz Change-Id: I124e24f42b52c7ac1d848cbdeeb2e111d5813d33 --- arch/arm/arm/src/startup/reset_vector_mp.S | 13 +++++++------ arch/arm/arm/src/startup/reset_vector_up.S | 13 +++++++------ 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/arch/arm/arm/src/startup/reset_vector_mp.S b/arch/arm/arm/src/startup/reset_vector_mp.S index 7f7e2962..b1f9ff47 100644 --- a/arch/arm/arm/src/startup/reset_vector_mp.S +++ b/arch/arm/arm/src/startup/reset_vector_mp.S @@ -121,8 +121,9 @@ reset_vector: mcr p15, 0, r0, c13, c0, 4 /* do some early cpu setup: i/d cache disable, mmu disabled */ mrc p15, 0, r0, c1, c0, 0 - bic r0, #(1<<12) - bic r0, #(1<<2 | 1<<0) + bic r0, #(1 << 12) /* i cache */ + bic r0, #(1 << 2) /* d cache */ + bic r0, #(1 << 0) /* mmu */ mcr p15, 0, r0, c1, c0, 0 /* enable fpu+neon */ @@ -282,11 +283,11 @@ mmu_setup: mcr p15, 0, r12, c1, c0, 1 /* ACTLR, Auxlliary Control Register */ dsb mrc p15, 0, r12, c1, c0, 0 - bic r12, #(1 << 29 | 1 << 28) - orr r12, #(1 << 0) + bic r12, #(1 << 29 | 1 << 28) /* Disable TRE/AFE */ + orr r12, #(1 << 0) /* mmu enable */ bic r12, #(1 << 1) - orr r12, #(1 << 2) - orr r12, #(1 << 12) + orr r12, #(1 << 2) /* D cache enable */ + orr r12, #(1 << 12) /* I cache enable */ mcr p15, 0, r12, c1, c0, 0 /* Set SCTLR with r12: Turn on the MMU, I/D cache Disable TRE/AFE */ isb ldr pc, =1f /* Convert to VA */ diff --git a/arch/arm/arm/src/startup/reset_vector_up.S b/arch/arm/arm/src/startup/reset_vector_up.S index 75994ac1..a54f468a 100644 --- a/arch/arm/arm/src/startup/reset_vector_up.S +++ b/arch/arm/arm/src/startup/reset_vector_up.S @@ -101,8 +101,9 @@ __exception_handlers: reset_vector: /* do some early cpu setup: i/d cache disable, mmu disabled */ mrc p15, 0, r0, c1, c0, 0 - bic r0, #(1<<12) - bic r0, #(1<<2 | 1<<0) + bic r0, #(1 << 12) /* i cache */ + bic r0, #(1 << 2) /* d cache */ + bic r0, #(1 << 0) /* mmu */ mcr p15, 0, r0, c1, c0, 0 /* enable fpu+neon */ @@ -269,11 +270,11 @@ mmu_setup: isb mrc p15, 0, r12, c1, c0, 0 - bic r12, #(1 << 29 | 1 << 28) - orr r12, #(1 << 0) + bic r12, #(1 << 29 | 1 << 28) /* Disable TRE/AFE */ + orr r12, #(1 << 0) /* mmu enable */ bic r12, #(1 << 1) - orr r12, #(1 << 2) - orr r12, #(1 << 12) + orr r12, #(1 << 2) /* D cache enable */ + orr r12, #(1 << 12) /* I cache enable */ mcr p15, 0, r12, c1, c0, 0 /* Set SCTLR with r12: Turn on the MMU, I/D cache Disable TRE/AFE */ isb