style: Misspelling
Signed-off-by: lihongjin <lihongjin1@huawei.com> Change-Id: I13163f2e4d1e4b6e6c6bedaf9d4e705544df926b
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@@ -276,11 +276,11 @@ mmu_setup:
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mov r12, #0x7 /* 0b0111 */
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mcr p15, 0, r12, c3, c0, 0 /* Set DACR with 0b0111, client and manager domian */
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isb
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mrc p15, 0, r12, c1, c0, 1 /* ACTLR, Auxlliary Control Register */
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mrc p15, 0, r12, c1, c0, 1 /* ACTLR, Auxiliary Control Register */
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orr r12, r12, #(1 << 6) /* SMP, Enables coherent requests to the processor. */
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orr r12, r12, #(1 << 2) /* Enable D-side prefetch */
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orr r12, r12, #(1 << 11) /* Global BP Enable bit */
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mcr p15, 0, r12, c1, c0, 1 /* ACTLR, Auxlliary Control Register */
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mcr p15, 0, r12, c1, c0, 1 /* ACTLR, Auxiliary Control Register */
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dsb
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mrc p15, 0, r12, c1, c0, 0
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bic r12, #(1 << 29 | 1 << 28) /* Disable TRE/AFE */
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