style: Misspelling

Signed-off-by: lihongjin <lihongjin1@huawei.com>
Change-Id: I13163f2e4d1e4b6e6c6bedaf9d4e705544df926b
This commit is contained in:
lihongjin
2022-06-20 19:38:17 +08:00
parent 4acf1e9f8d
commit 1c0de289ec
37 changed files with 53 additions and 53 deletions

View File

@@ -276,11 +276,11 @@ mmu_setup:
mov r12, #0x7 /* 0b0111 */
mcr p15, 0, r12, c3, c0, 0 /* Set DACR with 0b0111, client and manager domian */
isb
mrc p15, 0, r12, c1, c0, 1 /* ACTLR, Auxlliary Control Register */
mrc p15, 0, r12, c1, c0, 1 /* ACTLR, Auxiliary Control Register */
orr r12, r12, #(1 << 6) /* SMP, Enables coherent requests to the processor. */
orr r12, r12, #(1 << 2) /* Enable D-side prefetch */
orr r12, r12, #(1 << 11) /* Global BP Enable bit */
mcr p15, 0, r12, c1, c0, 1 /* ACTLR, Auxlliary Control Register */
mcr p15, 0, r12, c1, c0, 1 /* ACTLR, Auxiliary Control Register */
dsb
mrc p15, 0, r12, c1, c0, 0
bic r12, #(1 << 29 | 1 << 28) /* Disable TRE/AFE */