diff --git a/docs/.vuepress/sidebar.js b/docs/.vuepress/sidebar.js
index 89db920..c712845 100755
--- a/docs/.vuepress/sidebar.js
+++ b/docs/.vuepress/sidebar.js
@@ -16,7 +16,6 @@ const sidebar = {
     '/doc/component/gui'
   ],
   'board': [
-    '/doc/board/aiit-arm32',
     '/doc/board/stm32f407-st-discovery',
     '/doc/board/stm32f407zgt6',
     '/doc/board/hifive1-rev',
diff --git a/docs/doc/board/README.md b/docs/doc/board/README.md
index 5431378..b686efb 100644
--- a/docs/doc/board/README.md
+++ b/docs/doc/board/README.md
@@ -4,8 +4,6 @@
 
 ## ARM
 
-* [aiit-arm32](/doc/board/aiit-arm32.md)
-
 * [stm32f407-st-discovery](/doc/board/stm32f407-st-discovery.md)
 
 * [stm32f407zgt6](/doc/board/stm32f407zgt6.md)
diff --git a/docs/doc/board/aiit-arm32.md b/docs/doc/board/aiit-arm32.md
deleted file mode 100644
index cdca956..0000000
--- a/docs/doc/board/aiit-arm32.md
+++ /dev/null
@@ -1,7 +0,0 @@
-# aiit-arm32
-## 综述
-<div class ="tablebox_aiit_arm32">
-<img src="" alt="aiit-arm32"/>
-<p>AIIT-ARM32</p>
-    <span>XiUOS最新分支支持aiit-arm32开发板，该开发板作为一种标准的板子，支持各种上层组件和应用程序。</span>
-</div>
\ No newline at end of file
diff --git a/docs/doc/board/aiit-arm64.md b/docs/doc/board/aiit-arm64.md
deleted file mode 100644
index b0d0314..0000000
--- a/docs/doc/board/aiit-arm64.md
+++ /dev/null
@@ -1,58 +0,0 @@
-# aiit-arm64
-## 综述
-<div class ="tablebox_aiit-arm64">
-<div class="imgbox">
-<img src="" alt="aiit-arm64"/>
-</div>
-<p>AIIT-ARM64</p>
-    <span>XiUOS最新分支支持stm32f407-st-discovery开发板，该开发板作为一种标准的板子，支持各种上层组件和应用程序。</span>
-  </div>
-
-## 硬件特点
-
-+ Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions 
-+ Memories
-<p style="text-indent:2em">1. Up to 1 Mbyte of Flash memory</p>
-<p style="text-indent:2em">2. Up to 192+4 Kbytes of SRAM including 64-Kbyte of CCM (core coupled memory) data RAM </p>
-<p style="text-indent:2em">3. Up to 192+4 Kbytes of SRAM including 64-Kbyte of CCM (core coupled memory) data RAM</p>
-<p style="text-indent:2em">4. 512 bytes of OTP memory</p>
-<p style="text-indent:2em">5. Flexible static memory controller supporting Compact Flash, SRAM, PSRAM, NOR and NAND memories</p>
-+ LCD parallel interface, 8080/6800 modes
-+ Clock, reset and supply management 
-<p style="text-indent:2em">1. 1.8 V to 3.6 V application supply and I/Os</p>
-<p style="text-indent:2em">2. POR, PDR, PVD and BOR</p>
-<p style="text-indent:2em">3. 4-to-26 MHz crystal oscillator </p>
-<p style="text-indent:2em">4. Internal 16 MHz factory-trimmed RC (1% accuracy)</p>
-<p style="text-indent:2em">5. 32 kHz oscillator for RTC with calibration</p>
-<p style="text-indent:2em">6. Internal 32 kHz RC with calibration </p>
-+ Low-power operation 
-<p style="text-indent:2em">1. Sleep, Stop and Standby modes </p>
-<p style="text-indent:2em">2. V<sub>BAT</sub> supply for RTC, 20×32 bit backup registers + optional 4 KB backup SRAM </p>
-+ 3×12-bit, 2.4 MSPS A/D converters: up to 24 channels and 7.2 MSPS in triple interleaved mode 
-+ 2×12-bit D/A converters 
-+ General-purpose DMA: 16-stream DMA controller with FIFOs and burst support 
-+ Up to 17 timers: up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
-+ Debug mode 
-<p style="text-indent:2em">1. Serial wire debug (SWD) & JTAG interfaces </p>
-<p style="text-indent:2em">2. Cortex-M4 Embedded Trace Macrocell™  </p>
-+ Up to 140 I/O ports with interrupt capability 
-<p style="text-indent:2em">1. Up to 136 fast I/Os up to 84 MHz  </p>
-<p style="text-indent:2em">2. Up to 138 5 V-tolerant I/Os  </p> 
-+ Up to 15 communication interfaces 
-<p style="text-indent:2em">1. Up to 3 × I<sup>2</sup>C interfaces (SMBus/PMBus)   </p>
-<p style="text-indent:2em">2. Up to 4 USARTs/2 UARTs (10.5 Mbit/s, ISO 7816 interface, LIN, IrDA, modem control)   </p> 
-<p style="text-indent:2em">3. Up to 3 SPIs (42 Mbits/s), 2 with muxed full-duplex I2S to achieve audio class accuracy via internal audio PLL or external clock   </p>
-<p style="text-indent:2em">4. 2 × CAN interfaces (2.0B Active)  </p> 
-<p style="text-indent:2em">5. SDIO interface   </p>
-+ Advanced connectivity 
-<p style="text-indent:2em">1. USB 2.0 full-speed device/host/OTG controller with on-chip PHY  </p>
-<p style="text-indent:2em">2. USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI</p> 
-<p style="text-indent:2em">3. 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII </p>
-+ 8- to 14-bit parallel camera interface up to 54 Mbytes/s 
-+ True random number generator 
-+ CRC calculation unit
-+ 96-bit unique ID
-+ RTC: subsecond accuracy, hardware calendar 
-
-## 支持的功能
-