add selfterminal dir
This commit is contained in:
parent
2d94ad99f4
commit
1450699c63
|
@ -71,6 +71,10 @@ module.exports = {
|
|||
text: '开发板',
|
||||
link: '/doc/board/',
|
||||
},
|
||||
{
|
||||
text: '自研终端',
|
||||
link: '/doc/selfterminal/'
|
||||
},
|
||||
{
|
||||
text: '应用开发',
|
||||
link: '/doc/appdev/',
|
||||
|
@ -145,6 +149,10 @@ module.exports = {
|
|||
title: '开发板',
|
||||
children: getSidebarByCategory('board','en')
|
||||
},
|
||||
{
|
||||
title: '自研终端',
|
||||
children: getSidebarByCategory('selfterminal','en')
|
||||
},
|
||||
{
|
||||
title: '应用开发',
|
||||
children: getSidebarByCategory('appdev','en')
|
||||
|
|
|
@ -65,6 +65,10 @@ const sidebar = {
|
|||
'/doc/processor/riscv',
|
||||
'/doc/processor/riscv_sk',
|
||||
'/doc/processor/riscv_fpga'
|
||||
],
|
||||
'selfterminal': [
|
||||
'/doc/selfterminal/aiit-arm',
|
||||
'/doc/selfterminal/aiit-riscv'
|
||||
]
|
||||
}
|
||||
|
||||
|
|
|
@ -0,0 +1,8 @@
|
|||
# 自研终端
|
||||
|
||||
---
|
||||
|
||||
* [aiit_arm](/doc/selfterminal/aiit-arm.md)
|
||||
|
||||
* [aiit_riscv](/doc/selfterminal/aiit-riscv.md)
|
||||
|
|
@ -0,0 +1 @@
|
|||
# aiit-arm
|
|
@ -0,0 +1 @@
|
|||
# aiit-riscv
|
Loading…
Reference in New Issue