TXuian
222 lines
7.3 KiB
C
222 lines
7.3 KiB
C
/*
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* Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file ccm_pll.c
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* @brief support imx6q soc ccm pll functions
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* @version 3.0
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* @author AIIT XUOS Lab
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* @date 2023.09.08
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*/
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/*************************************************
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File name: ccm_pll.c
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Description: support imx6q soc ccm pll functions
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Others:
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History:
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1. Date: 2023-08-28
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Author: AIIT XUOS Lab
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Modification:
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1. Delete unnecessary functions;
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2. Slim clock_gating_config to fit only uart and gpt(clock)
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*************************************************/
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#include "soc_memory_map.h"
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#include <stdbool.h>
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#include <stdint.h>
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#include "regsccm.h"
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#include "regsccmanalog.h"
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#include "regsgpc.h"
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#include "regsepit.h"
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#include "regsgpt.h"
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#include "ccm_pll.h"
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////////////////////////////////////////////////////////////////////////////////
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// Variables
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////////////////////////////////////////////////////////////////////////////////
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const uint32_t PLL1_OUTPUT = 792000000;
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const uint32_t PLL2_OUTPUT[] = { 528000000, 396000000, 352000000, 198000000, 594000000 };
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const uint32_t PLL3_OUTPUT[] = { 480000000, 720000000, 540000000, 508235294, 454736842 };
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const uint32_t PLL4_OUTPUT = 650000000;
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const uint32_t PLL5_OUTPUT = 650000000;
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////////////////////////////////////////////////////////////////////////////////
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// Code
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////////////////////////////////////////////////////////////////////////////////
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uint32_t get_main_clock(main_clocks_t clock)
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{
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uint32_t ret_val = 0;
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uint32_t pre_periph_clk_sel = HW_CCM_CBCMR.B.PRE_PERIPH_CLK_SEL;
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switch (clock) {
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case CPU_CLK:
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ret_val = PLL1_OUTPUT;
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break;
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#if !defined(CHIP_MX6SL)
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case AXI_CLK:
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ret_val = PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.AXI_PODF + 1);
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break;
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case MMDC_CH0_AXI_CLK:
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ret_val = PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.MMDC_CH0_AXI_PODF + 1);
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break;
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#endif
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case AHB_CLK:
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ret_val = PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.AHB_PODF + 1);
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break;
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case IPG_CLK:
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ret_val = PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.AHB_PODF + 1) / (HW_CCM_CBCDR.B.IPG_PODF + 1);
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break;
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case IPG_PER_CLK:
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ret_val = PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.AHB_PODF + 1) / (HW_CCM_CBCDR.B.IPG_PODF + 1) / (HW_CCM_CSCMR1.B.PERCLK_PODF + 1);
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break;
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#if !defined(CHIP_MX6SL)
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case MMDC_CH1_AXI_CLK:
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ret_val = PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.MMDC_CH1_AXI_PODF + 1);
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break;
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#endif
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default:
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break;
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}
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return ret_val;
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}
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uint32_t get_peri_clock(peri_clocks_t clock)
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{
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uint32_t ret_val = 0;
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switch (clock) {
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case UART1_MODULE_CLK:
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case UART2_MODULE_CLK:
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case UART3_MODULE_CLK:
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case UART4_MODULE_CLK:
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// UART source clock is a fixed PLL3 / 6
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ret_val = PLL3_OUTPUT[0] / 6 / (HW_CCM_CSCDR1.B.UART_CLK_PODF + 1);
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break;
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// eCSPI clock:
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// PLL3(480) -> /8 -> CSCDR2[ECSPI_CLK_PODF]
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case SPI_CLK:
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ret_val = PLL3_OUTPUT[0] / 8 / (HW_CCM_CSCDR2.B.ECSPI_CLK_PODF + 1);
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break;
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#if !defined(CHIP_MX6SL)
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case RAWNAND_CLK:
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ret_val = PLL3_OUTPUT[0] / (HW_CCM_CS2CDR.B.ENFC_CLK_PRED + 1) / (HW_CCM_CS2CDR.B.ENFC_CLK_PODF + 1);
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break;
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case CAN_CLK:
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// For i.mx6dq/sdl CAN source clock is a fixed PLL3 / 8
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ret_val = PLL3_OUTPUT[0] / 8 / (HW_CCM_CSCMR2.B.CAN_CLK_PODF + 1);
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break;
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#endif
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default:
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break;
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}
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return ret_val;
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}
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void ccm_set_lpm_wakeup_source(uint32_t irq_id, bool doEnable)
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{
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uint32_t reg_offset = 0;
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uint32_t bit_offset = 0;
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uint32_t gpc_imr = 0;
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// calculate the offset of the register handling that interrupt ID
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// ID starts at 32, so for instance ID=89 is handled by IMR2 because
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// the integer part of the division is reg_offset = 2
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reg_offset = (irq_id / 32);
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// and the rest of the previous division is used to calculate the bit
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// offset in the register, so for ID=89 this is bit_offset = 25
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bit_offset = irq_id - 32 * reg_offset;
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// get the current value of the corresponding GPC_IMRx register
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gpc_imr = *((volatile uint32_t*)(HW_GPC_IMR1_ADDR + (reg_offset - 1) * 4));
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if (doEnable) {
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// clear the corresponding bit to unmask the interrupt source
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gpc_imr &= ~(1 << bit_offset);
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// write the new mask
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*((volatile uint32_t*)(HW_GPC_IMR1_ADDR + (reg_offset - 1) * 4)) = (gpc_imr);
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} else {
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// set the corresponding bit to mask the interrupt source
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gpc_imr |= (1 << bit_offset);
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// write the new mask
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*((volatile uint32_t*)(HW_GPC_IMR1_ADDR + (reg_offset - 1) * 4)) = (gpc_imr);
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}
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}
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/*!
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* Set/unset clock gating for a peripheral.
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* @param ccm_ccgrx Address of the clock gating register: CCM_CCGR1,...
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* @param cgx_offset Offset of the clock gating field: CG(x).
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* @param gating_mode Clock gating mode: CLOCK_ON or CLOCK_OFF.
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*/
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void ccm_ccgr_config(uint32_t ccm_ccgrx, uint32_t cgx_offset, uint32_t gating_mode)
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{
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if (gating_mode == CLOCK_ON) {
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*(volatile uint32_t*)(ccm_ccgrx) |= cgx_offset;
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} else {
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*(volatile uint32_t*)(ccm_ccgrx) &= ~cgx_offset;
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}
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}
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void clock_gating_config(uint32_t base_address, uint32_t gating_mode)
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{
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uint32_t ccm_ccgrx = 0;
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uint32_t cgx_offset = 0;
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switch (base_address) {
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case REGS_EPIT1_BASE:
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ccm_ccgrx = HW_CCM_CCGR1_ADDR;
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cgx_offset = CG(6);
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break;
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case REGS_EPIT2_BASE:
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ccm_ccgrx = HW_CCM_CCGR1_ADDR;
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cgx_offset = CG(7);
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break;
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default:
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break;
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}
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// apply changes only if a valid address was found
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if (ccm_ccgrx != 0) {
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ccm_ccgr_config(ccm_ccgrx, cgx_offset, gating_mode);
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}
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}
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////////////////////////////////////////////////////////////////////////////////
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// End of file
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////////////////////////////////////////////////////////////////////////////////
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