Wang_Weigen
127 lines
3.5 KiB
C
127 lines
3.5 KiB
C
/*
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* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
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* Copyright 2016 NXP
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* All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*************************************************
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File name: fsl_common
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Description:
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Others: take for references
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https://github.com/open-isa-org/open-isa.org
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History:
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1. Date: 2022-02-16
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Author: AIIT XUOS Lab
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Modification:
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*************************************************/
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#include "fsl_common.h"
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// #include "fsl_debug_console.h"
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#ifndef NDEBUG
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#if (defined(__CC_ARM)) || (defined(__ICCARM__))
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void __aeabi_assert(const char *failedExpr, const char *file, int line)
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{
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PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
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for (;;)
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{
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__BKPT(0);
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}
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}
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#elif(defined(__GNUC__))
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void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
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{
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PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
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for (;;)
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{
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__BKPT(0);
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}
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}
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#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */
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#endif /* NDEBUG */
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#ifndef __GIC_PRIO_BITS
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#ifndef __riscv
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uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
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{
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/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
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#if defined(__CC_ARM)
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extern uint32_t Image$$VECTOR_ROM$$Base[];
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extern uint32_t Image$$VECTOR_RAM$$Base[];
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extern uint32_t Image$$RW_m_data$$Base[];
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#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
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#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
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#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
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#elif defined(__ICCARM__)
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extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
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extern uint32_t __VECTOR_TABLE[];
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extern uint32_t __VECTOR_RAM[];
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#elif defined(__GNUC__)
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extern uint32_t __VECTOR_TABLE[];
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extern uint32_t __VECTOR_RAM[];
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extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
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uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
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#endif /* defined(__CC_ARM) */
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uint32_t n;
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uint32_t ret;
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uint32_t irqMaskValue;
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irqMaskValue = DisableGlobalIRQ();
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if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
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{
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/* Copy the vector table from ROM to RAM */
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for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
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{
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__VECTOR_RAM[n] = __VECTOR_TABLE[n];
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}
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/* Point the VTOR to the position of vector table */
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SCB->VTOR = (uint32_t)__VECTOR_RAM;
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}
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ret = __VECTOR_RAM[irq + 16];
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/* make sure the __VECTOR_RAM is noncachable */
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__VECTOR_RAM[irq + 16] = irqHandler;
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EnableGlobalIRQ(irqMaskValue);
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return ret;
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}
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#endif
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#endif
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#ifndef QN908XC_SERIES
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#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
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void EnableDeepSleepIRQ(IRQn_Type interrupt)
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{
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uint32_t index = 0;
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uint32_t intNumber = (uint32_t)interrupt;
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while (intNumber >= 32u)
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{
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index++;
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intNumber -= 32u;
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}
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SYSCON->STARTERSET[index] = 1u << intNumber;
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EnableIRQ(interrupt); /* also enable interrupt at NVIC */
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}
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void DisableDeepSleepIRQ(IRQn_Type interrupt)
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{
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uint32_t index = 0;
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uint32_t intNumber = (uint32_t)interrupt;
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while (intNumber >= 32u)
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{
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index++;
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intNumber -= 32u;
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}
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DisableIRQ(interrupt); /* also disable interrupt at NVIC */
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SYSCON->STARTERCLR[index] = 1u << intNumber;
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}
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#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
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#endif /* QN908XC_SERIES */
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