Commit Graph

10 Commits

Author SHA1 Message Date
Liu_Weichao 0bacf4bd1d add UART1 Kconfig on aiit-riscv64-board 2022-09-06 09:32:29 +08:00
Liu_Weichao 1fd4e3981d optimize ch438 function on aiit-riscv64-board and xidatong-riscv64 2022-09-05 18:03:09 +08:00
Liu_Weichao 5de4b9eec0 add ch438 for xidatong-riscv64 board 2022-09-01 09:20:15 +08:00
Liu_Weichao f55022fc46 delete useless H file on xidatong-riscv64 board 2022-08-31 10:51:14 +08:00
Liu_Weichao 76017d0d0d delete useless config on riscv-board 2022-08-24 17:33:38 +08:00
TXuian cb4a9d03e0 fit musl for riscv64 boards. 2022-07-27 05:35:56 -07:00
Liu_Weichao 80e08450fe fix compile error include watchdog and uart configure error 2022-06-08 11:09:50 +08:00
Liu_Weichao 808f00ade1 feat add sem obtain wait_time and modify e220 lora receive len operation 2022-04-26 17:57:32 +08:00
Liu_Weichao 6be4d4b5ca feat add winddirection_qs_fx and windspeed_qs_fs for sensor framework 2022-03-08 16:15:38 +08:00
Liu_Weichao 5078ff66cc feat modify XiUOS_Kernel dir from Ubiquitous/XiUOS to Ubiquitous/XiZi 2022-03-01 14:15:01 +08:00