support spi module
This commit is contained in:
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f942af6c43
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@ -35,6 +35,7 @@ extern int ExtSramInit(void);
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#include <connect_ethernet.h>
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#include <connect_uart.h>
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#include <connect_adc.h>
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#include <connect_spi.h>
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#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
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4 bits for subpriority */
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@ -634,8 +635,10 @@ void InitBoardHardware()
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Imrt1052HwAdcInit();
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#endif
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#ifdef BSP_USING_SPI
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Imrt1052HwSpiInit();
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#endif
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InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
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}
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@ -44,6 +44,10 @@ menuconfig BSP_USING_SPI
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default y
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select RESOURCES_SPI
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if BSP_USING_SPI
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source "$BSP_DIR/third_party_driver/spi/Kconfig"
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endif
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menuconfig BSP_USING_SEMC
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bool "Using SEMC device"
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default y
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,56 @@
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/*
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* Copyright (c) 2020 AIIT XUOS Lab
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* XiUOS is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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* http://license.coscl.org.cn/MulanPSL2
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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* See the Mulan PSL v2 for more details.
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*/
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/**
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* @file connect_spi.h
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* @brief define stm32f407-st-discovery-board spi function and struct
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* @version 1.0
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* @author AIIT XUOS Lab
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* @date 2021-04-25
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*/
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#ifndef CONNECT_SPI_H
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#define CONNECT_SPI_H
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#include <xiuos.h>
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#include <device.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define SPI_USING_RX_DMA_FLAG (1<<0)
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#define SPI_USING_TX_DMA_FLAG (1<<1)
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struct Stm32HwSpi
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{
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LPSPI_Type *base;
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uint8_t irq;
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uint8_t mode;
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void *priv_data;
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};
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struct Stm32Spi
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{
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LPSPI_Type *instance;
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char *bus_name;
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struct SpiBus spi_bus;
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};
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int Imrt1052HwSpiInit(void);
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x_err_t HwSpiDeviceAttach(const char *bus_name, const char *device_name);
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#ifdef __cplusplus
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}
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#endif
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#endif
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@ -0,0 +1,45 @@
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config BSP_USING_SPI1
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bool "Enable SPI1"
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default y
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if BSP_USING_SPI1
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config SPI_1_BUS_NAME
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string "spi1 bus name"
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default "spi1"
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config SPI_1_DRV_NAME
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string "spi bus 1 driver name"
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default "spi1_drv"
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config SPI_1_DEV_NAME_0
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string "spi bus 1 device name"
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default "spi1_dev"
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endif
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config BSP_USING_SPI2
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bool "Enable SPI2"
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default y
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if BSP_USING_SPI2
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config SPI_2_BUS_NAME
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string "spi2 bus name"
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default "spi2"
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config SPI_2_DRV_NAME
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string "spi bus 2 driver name"
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default "spi2_drv"
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config SPI_2_DEV_NAME_0
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string "spi bus 2 device name"
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default "spi2_dev"
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endif
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config BSP_USING_SPI3
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bool "Enable SPI3"
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default y
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if BSP_USING_SPI3
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config SPI_3_BUS_NAME
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string "spi3 bus name"
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default "spi3"
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config SPI_3_DRV_NAME
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string "spi bus 3 driver name"
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default "spi3_drv"
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config SPI_3_DEV_NAME_0
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string "spi bus 3 device name"
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default "spi3_dev"
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endif
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@ -1,3 +1,3 @@
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SRC_FILES := fsl_lpspi.c lpspi_interrupt.c connect_flash_spi.c flexspi_nor_flash_ops.c flexspi_nor_polling_transfer.c fsl_flexspi.c
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SRC_FILES := fsl_lpspi.c connect_spi.c connect_flash_spi.c flexspi_nor_flash_ops.c flexspi_nor_polling_transfer.c fsl_flexspi.c
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include $(KERNEL_ROOT)/compiler.mk
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File diff suppressed because it is too large
Load Diff
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@ -1,492 +0,0 @@
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/*
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* Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/**
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* @file lpspi_interrupt.c
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* @brief Demo for SPI function
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* @version 1.0
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* @author AIIT XUOS Lab
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* @date 2022.1.18
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*/
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#include "fsl_device_registers.h"
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#include "fsl_debug_console.h"
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#include "fsl_lpspi.h"
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#include "board.h"
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#include "fsl_common.h"
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#include "pin_mux.h"
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#if ((defined FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT))
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#include "fsl_intmux.h"
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#endif
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* Master related */
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#define EXAMPLE_LPSPI_MASTER_BASEADDR (LPSPI3)
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#define EXAMPLE_LPSPI_MASTER_IRQN (LPSPI3_IRQn)
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#define EXAMPLE_LPSPI_MASTER_IRQHandler (LPSPI3_IRQHandler)
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#define EXAMPLE_LPSPI_MASTER_PCS_FOR_INIT (kLPSPI_Pcs0)
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#define EXAMPLE_LPSPI_MASTER_PCS_FOR_TRANSFER (kLPSPI_MasterPcs0)
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/* Slave related */
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#define EXAMPLE_LPSPI_SLAVE_BASEADDR (LPSPI1)
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#define EXAMPLE_LPSPI_SLAVE_IRQN (LPSPI1_IRQn)
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#define EXAMPLE_LPSPI_SLAVE_IRQHandler (LPSPI1_IRQHandler)
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#define EXAMPLE_LPSPI_SLAVE_PCS_FOR_INIT (kLPSPI_Pcs0)
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#define EXAMPLE_LPSPI_SLAVE_PCS_FOR_TRANSFER (kLPSPI_SlavePcs0)
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/* Select USB1 PLL PFD0 (720 MHz) as lpspi clock source */
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#define EXAMPLE_LPSPI_CLOCK_SOURCE_SELECT (1U)
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/* Clock divider for master lpspi clock source */
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#define EXAMPLE_LPSPI_CLOCK_SOURCE_DIVIDER (7U)
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#define EXAMPLE_LPSPI_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk) / (EXAMPLE_LPSPI_CLOCK_SOURCE_DIVIDER + 1U))
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#define EXAMPLE_LPSPI_MASTER_CLOCK_FREQ EXAMPLE_LPSPI_CLOCK_FREQ
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#define EXAMPLE_LPSPI_SLAVE_CLOCK_FREQ EXAMPLE_LPSPI_CLOCK_FREQ
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#define TRANSFER_SIZE (512U) /*! Transfer dataSize .*/
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#define TRANSFER_BAUDRATE (500000U) /*! Transfer baudrate - 500k */
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#define spi_print KPrintf
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#define spi_trace() KPrintf("lw: [%s][%d] passed!\n", __func__, __LINE__)
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/* LPSPI user callback */
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void LPSPI_SlaveUserCallback(LPSPI_Type *base, lpspi_slave_handle_t *handle, status_t status, void *userData);
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void LPSPI_MasterUserCallback(LPSPI_Type *base, lpspi_master_handle_t *handle, status_t status, void *userData);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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uint8_t masterRxData[TRANSFER_SIZE] = {0};
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uint8_t masterTxData[TRANSFER_SIZE] = {0};
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uint8_t slaveRxData[TRANSFER_SIZE] = {0};
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uint8_t slaveTxData[TRANSFER_SIZE] = {0};
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volatile uint32_t slaveTxCount;
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volatile uint32_t slaveRxCount;
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uint8_t g_slaveRxWatermark;
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uint8_t g_slaveFifoSize;
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volatile uint32_t masterTxCount;
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volatile uint32_t masterRxCount;
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uint8_t g_masterRxWatermark;
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uint8_t g_masterFifoSize;
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volatile bool isSlaveTransferCompleted = false;
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volatile bool isMasterTransferCompleted = false;
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/*******************************************************************************
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* Code
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******************************************************************************/
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void LPSPI_SlaveUserCallback(LPSPI_Type *base, lpspi_slave_handle_t *handle, status_t status, void *userData)
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{
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if (status == kStatus_Success)
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{
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spi_print("This is LPSPI slave transfer completed callback. \r\n");
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spi_print("It's a successful transfer. \r\n\r\n");
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}
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else if (status == kStatus_LPSPI_Error)
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{
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spi_print("This is LPSPI slave transfer completed callback. \r\n");
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spi_print("Error occurred in this transfer. \r\n\r\n");
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}
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else
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{
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__NOP();
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}
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isSlaveTransferCompleted = true;
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}
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void LPSPI_MasterUserCallback(LPSPI_Type *base, lpspi_master_handle_t *handle, status_t status, void *userData)
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{
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isMasterTransferCompleted = true;
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}
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void EXAMPLE_LPSPI_SLAVE_IRQHandler(int vector, void *param)
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{
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if (slaveRxCount < TRANSFER_SIZE)
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{
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while (LPSPI_GetRxFifoCount(EXAMPLE_LPSPI_SLAVE_BASEADDR))
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{
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slaveRxData[slaveRxCount] = LPSPI_ReadData(EXAMPLE_LPSPI_SLAVE_BASEADDR);
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slaveRxCount++;
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if (slaveTxCount < TRANSFER_SIZE)
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{
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LPSPI_WriteData(EXAMPLE_LPSPI_SLAVE_BASEADDR, slaveTxData[slaveTxCount]);
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slaveTxCount++;
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}
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if (slaveRxCount == TRANSFER_SIZE)
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{
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break;
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}
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}
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}
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/*Update rxWatermark. There isn't RX interrupt for the last datas if the RX count is not greater than rxWatermark.*/
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if ((TRANSFER_SIZE - slaveRxCount) <= g_slaveRxWatermark)
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{
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EXAMPLE_LPSPI_SLAVE_BASEADDR->FCR =
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(EXAMPLE_LPSPI_SLAVE_BASEADDR->FCR & (~LPSPI_FCR_RXWATER_MASK)) |
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LPSPI_FCR_RXWATER(((TRANSFER_SIZE - slaveRxCount) > 1) ? ((TRANSFER_SIZE - slaveRxCount) - 1U) : (0U));
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}
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/* Check if remaining receive byte count matches user request */
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if ((slaveRxCount == TRANSFER_SIZE) && (slaveTxCount == TRANSFER_SIZE))
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{
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isSlaveTransferCompleted = true;
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/* Disable interrupt requests */
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LPSPI_DisableInterrupts(EXAMPLE_LPSPI_SLAVE_BASEADDR, kLPSPI_RxInterruptEnable);
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}
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/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
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exception return operation might vector to incorrect interrupt */
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#if defined __CORTEX_M && (__CORTEX_M == 4U)
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__DSB();
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#endif
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}
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DECLARE_HW_IRQ(EXAMPLE_LPSPI_SLAVE_IRQN, EXAMPLE_LPSPI_SLAVE_IRQHandler, NONE);
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void EXAMPLE_LPSPI_MASTER_IRQHandler(int vector, void *param)
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{
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if (masterRxCount < TRANSFER_SIZE)
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{
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/* First, disable the interrupts to avoid potentially triggering another interrupt
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* while reading out the RX FIFO as more data may be coming into the RX FIFO. We'll
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* re-enable the interrupts EXAMPLE_LPSPI_MASTER_BASEADDRd on the LPSPI state after reading out the FIFO.
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*/
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LPSPI_DisableInterrupts(EXAMPLE_LPSPI_MASTER_BASEADDR, kLPSPI_RxInterruptEnable);
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while (LPSPI_GetRxFifoCount(EXAMPLE_LPSPI_MASTER_BASEADDR))
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{
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/*Read out the data*/
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masterRxData[masterRxCount] = LPSPI_ReadData(EXAMPLE_LPSPI_MASTER_BASEADDR);
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masterRxCount++;
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if (masterRxCount == TRANSFER_SIZE)
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{
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break;
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}
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}
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/* Re-enable the interrupts only if rxCount indicates there is more data to receive,
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* else we may get a spurious interrupt.
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* */
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if (masterRxCount < TRANSFER_SIZE)
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{
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/* Set the TDF and RDF interrupt enables simultaneously to avoid race conditions */
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LPSPI_EnableInterrupts(EXAMPLE_LPSPI_MASTER_BASEADDR, kLPSPI_RxInterruptEnable);
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}
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}
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/*Update rxWatermark. There isn't RX interrupt for the last datas if the RX count is not greater than rxWatermark.*/
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if ((TRANSFER_SIZE - masterRxCount) <= g_masterRxWatermark)
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{
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EXAMPLE_LPSPI_MASTER_BASEADDR->FCR =
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(EXAMPLE_LPSPI_MASTER_BASEADDR->FCR & (~LPSPI_FCR_RXWATER_MASK)) |
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LPSPI_FCR_RXWATER(((TRANSFER_SIZE - masterRxCount) > 1) ? ((TRANSFER_SIZE - masterRxCount) - 1U) : (0U));
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}
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if (masterTxCount < TRANSFER_SIZE)
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{
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while ((LPSPI_GetTxFifoCount(EXAMPLE_LPSPI_MASTER_BASEADDR) < g_masterFifoSize) &&
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(masterTxCount - masterRxCount < g_masterFifoSize))
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{
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/*Write the word to TX register*/
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LPSPI_WriteData(EXAMPLE_LPSPI_MASTER_BASEADDR, masterTxData[masterTxCount]);
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++masterTxCount;
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if (masterTxCount == TRANSFER_SIZE)
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{
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break;
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}
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}
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}
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/* Check if we're done with this transfer.*/
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if ((masterTxCount == TRANSFER_SIZE) && (masterRxCount == TRANSFER_SIZE))
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{
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isMasterTransferCompleted = true;
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/* Complete the transfer and disable the interrupts */
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LPSPI_DisableInterrupts(EXAMPLE_LPSPI_MASTER_BASEADDR, kLPSPI_AllInterruptEnable);
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}
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/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
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exception return operation might vector to incorrect interrupt */
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#if defined __CORTEX_M && (__CORTEX_M == 4U)
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__DSB();
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#endif
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}
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DECLARE_HW_IRQ(EXAMPLE_LPSPI_MASTER_IRQN, EXAMPLE_LPSPI_MASTER_IRQHandler, NONE);
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void lpspi_config_init(void)
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{
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lpspi_master_config_t masterConfig;
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lpspi_slave_config_t slaveConfig;
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/*Master config*/
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masterConfig.baudRate = TRANSFER_BAUDRATE;
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masterConfig.bitsPerFrame = 8;
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masterConfig.cpol = kLPSPI_ClockPolarityActiveHigh;
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masterConfig.cpha = kLPSPI_ClockPhaseFirstEdge;
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masterConfig.direction = kLPSPI_MsbFirst;
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masterConfig.pcsToSckDelayInNanoSec = 1000000000 / masterConfig.baudRate;
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masterConfig.lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig.baudRate;
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masterConfig.betweenTransferDelayInNanoSec = 1000000000 / masterConfig.baudRate;
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masterConfig.whichPcs = EXAMPLE_LPSPI_MASTER_PCS_FOR_INIT;
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masterConfig.pcsActiveHighOrLow = kLPSPI_PcsActiveLow;
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masterConfig.pinCfg = kLPSPI_SdiInSdoOut;
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masterConfig.dataOutConfig = kLpspiDataOutRetained;
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LPSPI_MasterInit(EXAMPLE_LPSPI_MASTER_BASEADDR, &masterConfig, EXAMPLE_LPSPI_MASTER_CLOCK_FREQ);
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/*Slave config*/
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slaveConfig.bitsPerFrame = masterConfig.bitsPerFrame;
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slaveConfig.cpol = masterConfig.cpol;
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slaveConfig.cpha = masterConfig.cpha;
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slaveConfig.direction = masterConfig.direction;
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slaveConfig.whichPcs = EXAMPLE_LPSPI_SLAVE_PCS_FOR_INIT;
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slaveConfig.pcsActiveHighOrLow = masterConfig.pcsActiveHighOrLow;
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slaveConfig.pinCfg = kLPSPI_SdiInSdoOut;
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slaveConfig.dataOutConfig = kLpspiDataOutRetained;
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LPSPI_SlaveInit(EXAMPLE_LPSPI_SLAVE_BASEADDR, &slaveConfig);
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}
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/*!
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* @brief Main function
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*/
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int test_spi(void)
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{
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/*Set clock source for LPSPI*/
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CLOCK_SetMux(kCLOCK_LpspiMux, EXAMPLE_LPSPI_CLOCK_SOURCE_SELECT);
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CLOCK_SetDiv(kCLOCK_LpspiDiv, EXAMPLE_LPSPI_CLOCK_SOURCE_DIVIDER);
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spi_print("LPSPI functional interrupt example start.\r\n");
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spi_print("This example use one lpspi instance as master and another as slave on one board.\r\n");
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spi_print("Master uses interrupt way and slave uses interrupt way.\r\n");
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spi_print(
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"Note that some LPSPI instances interrupt is in INTMUX ,"
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"you should set the intmux when you porting this example accordingly \r\n");
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spi_print("Please make sure you make the correct line connection. Basically, the connection is: \r\n");
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spi_print("LPSPI_master -- LPSPI_slave \r\n");
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spi_print(" CLK -- CLK \r\n");
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spi_print(" PCS -- PCS \r\n");
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spi_print(" SOUT -- SIN \r\n");
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spi_print(" SIN -- SOUT \r\n");
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|
||||
uint32_t errorCount;
|
||||
uint32_t i;
|
||||
uint32_t whichPcs;
|
||||
uint8_t txWatermark;
|
||||
|
||||
/*Set up the transfer data*/
|
||||
for (i = 0; i < TRANSFER_SIZE; i++)
|
||||
{
|
||||
masterTxData[i] = i % 256;
|
||||
masterRxData[i] = 0;
|
||||
|
||||
slaveTxData[i] = ~masterTxData[i];
|
||||
slaveRxData[i] = 0;
|
||||
}
|
||||
|
||||
lpspi_config_init();
|
||||
|
||||
/******************Set up slave first ******************/
|
||||
isSlaveTransferCompleted = false;
|
||||
slaveTxCount = 0;
|
||||
slaveRxCount = 0;
|
||||
whichPcs = EXAMPLE_LPSPI_SLAVE_PCS_FOR_INIT;
|
||||
|
||||
/*The TX and RX FIFO sizes are always the same*/
|
||||
g_slaveFifoSize = LPSPI_GetRxFifoSize(EXAMPLE_LPSPI_SLAVE_BASEADDR);
|
||||
|
||||
/*Set the RX and TX watermarks to reduce the ISR times.*/
|
||||
if (g_slaveFifoSize > 1)
|
||||
{
|
||||
txWatermark = 1;
|
||||
g_slaveRxWatermark = g_slaveFifoSize - 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
txWatermark = 0;
|
||||
g_slaveRxWatermark = 0;
|
||||
}
|
||||
|
||||
LPSPI_SetFifoWatermarks(EXAMPLE_LPSPI_SLAVE_BASEADDR, txWatermark, g_slaveRxWatermark);
|
||||
|
||||
LPSPI_Enable(EXAMPLE_LPSPI_SLAVE_BASEADDR, false);
|
||||
EXAMPLE_LPSPI_SLAVE_BASEADDR->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK);
|
||||
LPSPI_Enable(EXAMPLE_LPSPI_SLAVE_BASEADDR, true);
|
||||
|
||||
/*Flush FIFO , clear status , disable all the interrupts.*/
|
||||
LPSPI_FlushFifo(EXAMPLE_LPSPI_SLAVE_BASEADDR, true, true);
|
||||
LPSPI_ClearStatusFlags(EXAMPLE_LPSPI_SLAVE_BASEADDR, kLPSPI_AllStatusFlag);
|
||||
LPSPI_DisableInterrupts(EXAMPLE_LPSPI_SLAVE_BASEADDR, kLPSPI_AllInterruptEnable);
|
||||
|
||||
EXAMPLE_LPSPI_SLAVE_BASEADDR->TCR =
|
||||
(EXAMPLE_LPSPI_SLAVE_BASEADDR->TCR &
|
||||
~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | LPSPI_TCR_PCS_MASK)) |
|
||||
LPSPI_TCR_CONT(0) | LPSPI_TCR_CONTC(0) | LPSPI_TCR_RXMSK(0) | LPSPI_TCR_TXMSK(0) | LPSPI_TCR_PCS(whichPcs);
|
||||
|
||||
/* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX ,
|
||||
* and you should also enable the INTMUX interrupt in your application.
|
||||
*/
|
||||
EnableIRQ(EXAMPLE_LPSPI_SLAVE_IRQN);
|
||||
|
||||
/*TCR is also shared the FIFO , so wait for TCR written.*/
|
||||
while (LPSPI_GetTxFifoCount(EXAMPLE_LPSPI_SLAVE_BASEADDR) != 0)
|
||||
{
|
||||
}
|
||||
|
||||
spi_trace();
|
||||
|
||||
/*Fill up the TX data in FIFO */
|
||||
while (LPSPI_GetTxFifoCount(EXAMPLE_LPSPI_SLAVE_BASEADDR) < g_slaveFifoSize)
|
||||
{
|
||||
/*Write the word to TX register*/
|
||||
LPSPI_WriteData(EXAMPLE_LPSPI_SLAVE_BASEADDR, slaveTxData[slaveTxCount]);
|
||||
++slaveTxCount;
|
||||
|
||||
if (slaveTxCount == TRANSFER_SIZE)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
spi_trace();
|
||||
|
||||
LPSPI_EnableInterrupts(EXAMPLE_LPSPI_SLAVE_BASEADDR, kLPSPI_RxInterruptEnable);
|
||||
|
||||
/******************Set up master transfer******************/
|
||||
isMasterTransferCompleted = false;
|
||||
masterTxCount = 0;
|
||||
masterRxCount = 0;
|
||||
whichPcs = EXAMPLE_LPSPI_MASTER_PCS_FOR_INIT;
|
||||
|
||||
/*The TX and RX FIFO sizes are always the same*/
|
||||
g_masterFifoSize = LPSPI_GetRxFifoSize(EXAMPLE_LPSPI_MASTER_BASEADDR);
|
||||
|
||||
/*Set the RX and TX watermarks to reduce the ISR times.*/
|
||||
if (g_masterFifoSize > 1)
|
||||
{
|
||||
txWatermark = 1;
|
||||
g_masterRxWatermark = g_masterFifoSize - 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
txWatermark = 0;
|
||||
g_masterRxWatermark = 0;
|
||||
}
|
||||
|
||||
LPSPI_SetFifoWatermarks(EXAMPLE_LPSPI_MASTER_BASEADDR, txWatermark, g_masterRxWatermark);
|
||||
|
||||
LPSPI_Enable(EXAMPLE_LPSPI_MASTER_BASEADDR, false);
|
||||
EXAMPLE_LPSPI_MASTER_BASEADDR->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK);
|
||||
LPSPI_Enable(EXAMPLE_LPSPI_MASTER_BASEADDR, true);
|
||||
|
||||
/*Flush FIFO , clear status , disable all the inerrupts.*/
|
||||
LPSPI_FlushFifo(EXAMPLE_LPSPI_MASTER_BASEADDR, true, true);
|
||||
LPSPI_ClearStatusFlags(EXAMPLE_LPSPI_MASTER_BASEADDR, kLPSPI_AllStatusFlag);
|
||||
LPSPI_DisableInterrupts(EXAMPLE_LPSPI_MASTER_BASEADDR, kLPSPI_AllInterruptEnable);
|
||||
|
||||
EXAMPLE_LPSPI_MASTER_BASEADDR->TCR =
|
||||
(EXAMPLE_LPSPI_MASTER_BASEADDR->TCR &
|
||||
~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | LPSPI_TCR_PCS_MASK)) |
|
||||
LPSPI_TCR_CONT(0) | LPSPI_TCR_CONTC(0) | LPSPI_TCR_RXMSK(0) | LPSPI_TCR_TXMSK(0) | LPSPI_TCR_PCS(whichPcs);
|
||||
|
||||
/* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX ,
|
||||
* and you should also enable the INTMUX interupt in your application.
|
||||
*/
|
||||
EnableIRQ(EXAMPLE_LPSPI_MASTER_IRQN);
|
||||
|
||||
/*TCR is also shared the FIFO , so wait for TCR written.*/
|
||||
while (LPSPI_GetTxFifoCount(EXAMPLE_LPSPI_MASTER_BASEADDR) != 0)
|
||||
{
|
||||
}
|
||||
|
||||
spi_trace();
|
||||
|
||||
/*Fill up the TX data in FIFO */
|
||||
while ((LPSPI_GetTxFifoCount(EXAMPLE_LPSPI_MASTER_BASEADDR) < g_masterFifoSize) &&
|
||||
(masterTxCount - masterRxCount < g_masterFifoSize))
|
||||
{
|
||||
/*Write the word to TX register*/
|
||||
LPSPI_WriteData(EXAMPLE_LPSPI_MASTER_BASEADDR, masterTxData[masterTxCount]);
|
||||
++masterTxCount;
|
||||
|
||||
spi_trace();
|
||||
|
||||
if (masterTxCount == TRANSFER_SIZE)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
spi_trace();
|
||||
|
||||
LPSPI_EnableInterrupts(EXAMPLE_LPSPI_MASTER_BASEADDR, kLPSPI_RxInterruptEnable);
|
||||
|
||||
/******************Wait for master and slave transfer completed.******************/
|
||||
while ((!isSlaveTransferCompleted) || (!isMasterTransferCompleted))
|
||||
{
|
||||
}
|
||||
|
||||
spi_trace();
|
||||
|
||||
errorCount = 0;
|
||||
for (i = 0; i < TRANSFER_SIZE; i++)
|
||||
{
|
||||
if (masterTxData[i] != slaveRxData[i])
|
||||
{
|
||||
errorCount++;
|
||||
}
|
||||
|
||||
if (slaveTxData[i] != masterRxData[i])
|
||||
{
|
||||
errorCount++;
|
||||
}
|
||||
}
|
||||
if (errorCount == 0)
|
||||
{
|
||||
spi_print("\r\nLPSPI transfer all data matched! \r\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
spi_print("\r\nError occurred in LPSPI transfer ! \r\n");
|
||||
}
|
||||
|
||||
LPSPI_Deinit(EXAMPLE_LPSPI_MASTER_BASEADDR);
|
||||
LPSPI_Deinit(EXAMPLE_LPSPI_SLAVE_BASEADDR);
|
||||
|
||||
spi_print("End of example. \r\n");
|
||||
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
spi_trace();
|
||||
|
||||
}
|
||||
|
||||
SHELL_EXPORT_CMD (SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(0),
|
||||
spi, test_spi, SPI test );
|
||||
|
|
@ -16,7 +16,7 @@
|
|||
/**
|
||||
* @file connect_spi.c
|
||||
* @brief support stm32f407-st-discovery-board spi function and register to bus framework
|
||||
* @version 1.0
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-04-25
|
||||
*/
|
||||
|
@ -26,10 +26,10 @@ File name: connect_spi.c
|
|||
Description: support stm32f407-st-discovery-board spi configure and spi bus register function
|
||||
Others: take RT-Thread v4.0.2/bsp/stm32/libraries/HAL_Drivers/drv_spi.c for references
|
||||
https://github.com/RT-Thread/rt-thread/tree/v4.0.2
|
||||
History:
|
||||
History:
|
||||
1. Date: 2021-04-25
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
Modification:
|
||||
1. support stm32f407-st-discovery-board spi configure, write and read
|
||||
2. support stm32f407-st-discovery-board spi bus device and driver register
|
||||
*************************************************/
|
||||
|
@ -97,9 +97,9 @@ Modification:
|
|||
* This function SPI device initialization
|
||||
*
|
||||
* @param spi_drv SPI device structure pointer
|
||||
*
|
||||
*
|
||||
* @param cfg SPI device operating mode configuration structure pointer
|
||||
*
|
||||
*
|
||||
* @return if successful return EOK
|
||||
*/
|
||||
|
||||
|
@ -204,7 +204,7 @@ static x_err_t Stm32SpiInit(struct Stm32Spi *spi_drv, struct SpiMasterParam *cfg
|
|||
/* DMA configuration */
|
||||
if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG){
|
||||
DMA_Init(spi_drv->dma.dma_rx.instance, &spi_drv->dma.dma_rx.init);
|
||||
|
||||
|
||||
prioritygroup = NVIC_GetPriorityGrouping();
|
||||
|
||||
NVIC_SetPriority(spi_drv->dma.dma_rx.dma_irq, NVIC_EncodePriority(prioritygroup, 0, 0));
|
||||
|
@ -236,7 +236,7 @@ static void DmaSpiConfig(struct SpiBus *spi_bus, uint32_t setting_len, void *rx_
|
|||
if(spi->spi_dma_flag & SPI_USING_RX_DMA_FLAG)
|
||||
{
|
||||
spi->dma.dma_rx.setting_len = setting_len;
|
||||
DMA_DeInit(spi->dma.dma_rx.instance);
|
||||
DMA_DeInit(spi->dma.dma_rx.instance);
|
||||
while(DMA_GetCmdStatus(spi->dma.dma_rx.instance) != DISABLE);
|
||||
spi->dma.dma_rx.init.DMA_Channel = spi->dma.dma_rx.channel;
|
||||
spi->dma.dma_rx.init.DMA_PeripheralBaseAddr = (uint32_t)&(spi->instance->DR);
|
||||
|
@ -276,7 +276,7 @@ static void DmaSpiConfig(struct SpiBus *spi_bus, uint32_t setting_len, void *rx_
|
|||
if(spi->spi_dma_flag & SPI_USING_TX_DMA_FLAG)
|
||||
{
|
||||
spi->dma.dma_tx.setting_len = setting_len;
|
||||
DMA_DeInit(spi->dma.dma_tx.instance);
|
||||
DMA_DeInit(spi->dma.dma_tx.instance);
|
||||
while(DMA_GetCmdStatus(spi->dma.dma_tx.instance) != DISABLE);
|
||||
spi->dma.dma_tx.init.DMA_PeripheralBaseAddr = (uint32_t)&(spi->instance->DR);
|
||||
spi->dma.dma_tx.init.DMA_Memory0BaseAddr = (uint32_t)tx_base_addr;
|
||||
|
@ -374,18 +374,18 @@ static int SpiWaitUntilTimeout(SPI_InitTypeDef spi_init, SPI_TypeDef *spi_instan
|
|||
/**
|
||||
* This function SPI sends data through DMA
|
||||
*
|
||||
* @param spi_init SPI Init structure
|
||||
*
|
||||
* @param spi_init SPI Init structure
|
||||
*
|
||||
* @param spi_instance SPI control handle
|
||||
*
|
||||
*
|
||||
* @param dma_init DMA Init structure
|
||||
*
|
||||
*
|
||||
* @param dma_instance DMA Controller
|
||||
*
|
||||
*
|
||||
* @param p_data Send data buffer address
|
||||
*
|
||||
*
|
||||
* @param size Amount of data sent
|
||||
*
|
||||
*
|
||||
* @return if successful return EOK
|
||||
*/
|
||||
int SpiTransmitDma(SPI_InitTypeDef spi_init, SPI_TypeDef *spi_instance, DMA_InitTypeDef dma_init, DMA_Stream_TypeDef *dma_instance, uint8_t *p_data, uint16_t size)
|
||||
|
@ -457,24 +457,24 @@ error :
|
|||
/**
|
||||
* This function SPI carries out duplex communication through DMA
|
||||
*
|
||||
* @param spi_init SPI Init structure
|
||||
*
|
||||
* @param spi_init SPI Init structure
|
||||
*
|
||||
* @param spi_instance SPI control handle
|
||||
*
|
||||
*
|
||||
* @param dmarx_init DMA Init structure---Rx
|
||||
*
|
||||
*
|
||||
* @param dmarx_instance DMA Controller
|
||||
*
|
||||
*
|
||||
* @param dmatx_init DMA Init structure---Tx
|
||||
*
|
||||
*
|
||||
* @param dmatx_instance DMA Controller
|
||||
*
|
||||
*
|
||||
* @param p_txdata Send data buffer address
|
||||
*
|
||||
*
|
||||
* @param p_rxdata Receive data buffer address
|
||||
*
|
||||
* @param size Amount of data
|
||||
*
|
||||
*
|
||||
* @param size Amount of data
|
||||
*
|
||||
* @return if successful return EOK
|
||||
*/
|
||||
int SpiTransmitreceiveDma(SPI_InitTypeDef spi_init, SPI_TypeDef *spi_instance, DMA_InitTypeDef dmarx_init, DMA_Stream_TypeDef *dmarx_instance, DMA_InitTypeDef dmatx_init, DMA_Stream_TypeDef *dmatx_instance, uint8_t *p_txdata, uint8_t *p_rxdata, uint16_t size)
|
||||
|
@ -588,22 +588,22 @@ error :
|
|||
/**
|
||||
* This function SPI receives data through DMA
|
||||
*
|
||||
* @param spi_init SPI Init structure
|
||||
*
|
||||
* @param spi_init SPI Init structure
|
||||
*
|
||||
* @param spi_instance SPI control handle
|
||||
*
|
||||
*
|
||||
* @param dmarx_init DMA Init structure---Rx
|
||||
*
|
||||
*
|
||||
* @param dmarx_instance DMA Controller
|
||||
*
|
||||
*
|
||||
* @param dmatx_init DMA Init structure---Tx
|
||||
*
|
||||
*
|
||||
* @param dmatx_instance DMA Controller
|
||||
*
|
||||
*
|
||||
* @param p_data Receive data buffer address
|
||||
*
|
||||
* @param size Amount of data
|
||||
*
|
||||
*
|
||||
* @param size Amount of data
|
||||
*
|
||||
* @return if successful return EOK
|
||||
*/
|
||||
int SpiReceiveDma(SPI_InitTypeDef spi_init, SPI_TypeDef *spi_instance, DMA_InitTypeDef dmarx_init, DMA_Stream_TypeDef *dmarx_instance, DMA_InitTypeDef dmatx_init, DMA_Stream_TypeDef *dmatx_instance, uint8_t *p_data, uint16_t size)
|
||||
|
@ -676,18 +676,18 @@ error:
|
|||
return errorcode;
|
||||
}
|
||||
/**
|
||||
* This function SPI receives data
|
||||
* This function SPI receives data
|
||||
*
|
||||
* @param spi_init SPI Init structure
|
||||
*
|
||||
* @param spi_init SPI Init structure
|
||||
*
|
||||
* @param spi_instance SPI control handle
|
||||
*
|
||||
*
|
||||
* @param p_data Transmit data buffer address
|
||||
*
|
||||
* @param size Amount of data
|
||||
*
|
||||
*
|
||||
* @param size Amount of data
|
||||
*
|
||||
* @param Timeout waiting time
|
||||
*
|
||||
*
|
||||
* @return if successful return EOK
|
||||
*/
|
||||
int SpiTransmit(SPI_InitTypeDef spi_init, SPI_TypeDef *spi_instance, uint8_t *p_data, uint16_t size, uint32_t Timeout)
|
||||
|
@ -784,7 +784,7 @@ int SpiTransmit(SPI_InitTypeDef spi_init, SPI_TypeDef *spi_instance, uint8_t *p_
|
|||
errorcode = 3;
|
||||
goto error;
|
||||
}
|
||||
|
||||
|
||||
/* Check Busy flag */
|
||||
if(SpiWaitUntilTimeout(spi_init, spi_instance, SPI_FLAG_BSY, RESET, Timeout, tickstart) != 0){
|
||||
errorcode = 1;
|
||||
|
@ -797,18 +797,18 @@ error:
|
|||
/**
|
||||
* This function SPI Transmit and receive
|
||||
*
|
||||
* @param spi_init SPI Init structure
|
||||
*
|
||||
* @param spi_init SPI Init structure
|
||||
*
|
||||
* @param spi_instance SPI control handle
|
||||
*
|
||||
*
|
||||
* @param p_txdata Transmit data buffer address
|
||||
*
|
||||
*
|
||||
* @param p_rxdata receive data buffer address
|
||||
*
|
||||
* @param size Amount of data
|
||||
*
|
||||
*
|
||||
* @param size Amount of data
|
||||
*
|
||||
* @param Timeout waiting time
|
||||
*
|
||||
*
|
||||
* @return if successful return EOK
|
||||
*/
|
||||
int SpiTransmitreceive(SPI_InitTypeDef spi_init, SPI_TypeDef *spi_instance, uint8_t *p_txdata, uint8_t *p_rxdata, uint16_t size, uint32_t Timeout)
|
||||
|
@ -824,9 +824,9 @@ int SpiTransmitreceive(SPI_InitTypeDef spi_init, SPI_TypeDef *spi_instance, uint
|
|||
|
||||
/* Init tickstart for timeout management*/
|
||||
tickstart = CurrentTicksGain() * 1000 / TICK_PER_SECOND;
|
||||
|
||||
|
||||
tmp = spi_init.SPI_Mode;
|
||||
|
||||
|
||||
if(!((tmp == SPI_Mode_Master) && (spi_init.SPI_Direction == SPI_Direction_2Lines_FullDuplex))){
|
||||
errorcode = 2;
|
||||
goto error;
|
||||
|
@ -864,7 +864,7 @@ int SpiTransmitreceive(SPI_InitTypeDef spi_init, SPI_TypeDef *spi_instance, uint
|
|||
spi_instance->DR = *((uint16_t *)p_txdata);
|
||||
p_txdata += sizeof(uint16_t);
|
||||
tx_xfer_count--;
|
||||
/* Next Data is a reception (Rx). Tx not allowed */
|
||||
/* Next Data is a reception (Rx). Tx not allowed */
|
||||
txallowed = 0U;
|
||||
}
|
||||
|
||||
|
@ -874,7 +874,7 @@ int SpiTransmitreceive(SPI_InitTypeDef spi_init, SPI_TypeDef *spi_instance, uint
|
|||
*((uint16_t *)p_rxdata) = spi_instance->DR;
|
||||
p_rxdata += sizeof(uint16_t);
|
||||
rx_xfer_count--;
|
||||
/* Next Data is a Transmission (Tx). Tx is allowed */
|
||||
/* Next Data is a Transmission (Tx). Tx is allowed */
|
||||
txallowed = 1U;
|
||||
}
|
||||
if((Timeout != 0xFFFFFFFFU) && ((CurrentTicksGain() * 1000 / TICK_PER_SECOND-tickstart) >= Timeout)){
|
||||
|
@ -934,23 +934,23 @@ int SpiTransmitreceive(SPI_InitTypeDef spi_init, SPI_TypeDef *spi_instance, uint
|
|||
errorcode = 1;
|
||||
goto error;
|
||||
}
|
||||
|
||||
|
||||
error :
|
||||
return errorcode;
|
||||
}
|
||||
/**
|
||||
* This function SPI receive data
|
||||
*
|
||||
* @param spi_init SPI Init structure
|
||||
*
|
||||
* @param spi_init SPI Init structure
|
||||
*
|
||||
* @param spi_instance SPI control handle
|
||||
*
|
||||
*
|
||||
* @param p_data data buffer address
|
||||
*
|
||||
* @param size Amount of data
|
||||
*
|
||||
*
|
||||
* @param size Amount of data
|
||||
*
|
||||
* @param Timeout waiting time
|
||||
*
|
||||
*
|
||||
* @return if successful return EOK
|
||||
*/
|
||||
int SpiReceive(SPI_InitTypeDef spi_init, SPI_TypeDef *spi_instance, uint8_t *p_data, uint16_t size, uint32_t Timeout)
|
||||
|
@ -1047,9 +1047,9 @@ error :
|
|||
* This function SPI write data
|
||||
*
|
||||
* @param spi_dev SPI device structure handle
|
||||
*
|
||||
*
|
||||
* @param spi_datacfg SPI device information structure handle
|
||||
*
|
||||
*
|
||||
* @return datacfg length
|
||||
*/
|
||||
static uint32 Stm32SpiWriteData(struct SpiHardwareDevice *spi_dev, struct SpiDataStandard *spi_datacfg)
|
||||
|
@ -1067,7 +1067,7 @@ static uint32 Stm32SpiWriteData(struct SpiHardwareDevice *spi_dev, struct SpiDat
|
|||
SPI_InitTypeDef *spi_init = &StmSpi->init;
|
||||
struct Stm32HwSpiCs *cs = (struct Stm32HwSpiCs *)spi_dev->private_data;
|
||||
|
||||
while(NONE != spi_datacfg) {
|
||||
while(NONE != spi_datacfg) {
|
||||
if(spi_datacfg->spi_chip_select) {
|
||||
GPIO_WriteBit(cs->GPIOx, cs->GPIO_Pin, Bit_RESET);
|
||||
}
|
||||
|
@ -1086,7 +1086,7 @@ static uint32 Stm32SpiWriteData(struct SpiHardwareDevice *spi_dev, struct SpiDat
|
|||
/* calculate the start address */
|
||||
already_send_length = spi_datacfg->length - send_length - message_length;
|
||||
WriteBuf = (uint8 *)spi_datacfg->tx_buff + already_send_length;
|
||||
|
||||
|
||||
/* start once data exchange in DMA mode */
|
||||
if (spi_datacfg->tx_buff) {
|
||||
if (StmSpi->spi_dma_flag & SPI_USING_TX_DMA_FLAG) {
|
||||
|
@ -1105,7 +1105,7 @@ static uint32 Stm32SpiWriteData(struct SpiHardwareDevice *spi_dev, struct SpiDat
|
|||
if (spi_datacfg->spi_cs_release) {
|
||||
GPIO_WriteBit(cs->GPIOx, cs->GPIO_Pin, Bit_SET);
|
||||
}
|
||||
|
||||
|
||||
spi_datacfg = spi_datacfg->next;
|
||||
}
|
||||
|
||||
|
@ -1116,9 +1116,9 @@ static uint32 Stm32SpiWriteData(struct SpiHardwareDevice *spi_dev, struct SpiDat
|
|||
* This function SPI read data
|
||||
*
|
||||
* @param spi_dev SPI device structure handle
|
||||
*
|
||||
*
|
||||
* @param spi_datacfg SPI device information structure handle
|
||||
*
|
||||
*
|
||||
* @return datacfg length
|
||||
*/
|
||||
static uint32 Stm32SpiReadData(struct SpiHardwareDevice *spi_dev, struct SpiDataStandard *spi_datacfg)
|
||||
|
@ -1136,7 +1136,7 @@ static uint32 Stm32SpiReadData(struct SpiHardwareDevice *spi_dev, struct SpiData
|
|||
SPI_InitTypeDef *spi_init = &StmSpi->init;
|
||||
struct Stm32HwSpiCs *cs = (struct Stm32HwSpiCs *)spi_dev->private_data;
|
||||
|
||||
while (NONE != spi_datacfg) {
|
||||
while (NONE != spi_datacfg) {
|
||||
if (spi_datacfg->spi_chip_select) {
|
||||
GPIO_WriteBit(cs->GPIOx, cs->GPIO_Pin, Bit_RESET);
|
||||
}
|
||||
|
@ -1155,7 +1155,7 @@ static uint32 Stm32SpiReadData(struct SpiHardwareDevice *spi_dev, struct SpiData
|
|||
/* calculate the start address */
|
||||
already_send_length = spi_datacfg->length - read_length - message_length;
|
||||
ReadBuf = (uint8 *)spi_datacfg->rx_buff + already_send_length;
|
||||
|
||||
|
||||
/* start once data exchange in DMA mode */
|
||||
if (spi_datacfg->rx_buff) {
|
||||
//memset((uint8_t *)ReadBuf, 0xff, read_length);
|
||||
|
@ -1175,7 +1175,7 @@ static uint32 Stm32SpiReadData(struct SpiHardwareDevice *spi_dev, struct SpiData
|
|||
if (spi_datacfg->spi_cs_release) {
|
||||
GPIO_WriteBit(cs->GPIOx, cs->GPIO_Pin, Bit_SET);
|
||||
}
|
||||
|
||||
|
||||
spi_read_length += spi_datacfg->length;
|
||||
spi_datacfg = spi_datacfg->next;
|
||||
}
|
||||
|
@ -1187,7 +1187,7 @@ static uint32 Stm32SpiReadData(struct SpiHardwareDevice *spi_dev, struct SpiData
|
|||
* This function SPI driver initialization function
|
||||
*
|
||||
* @param spi_drv SPI driver structure handle
|
||||
*
|
||||
*
|
||||
* @return if successful return EOK
|
||||
*/
|
||||
static uint32 SpiDrvInit(struct SpiDriver *spi_drv)
|
||||
|
@ -1205,9 +1205,9 @@ static uint32 SpiDrvInit(struct SpiDriver *spi_drv)
|
|||
* This function SPI driver configuration param
|
||||
*
|
||||
* @param spi_drv SPI driver structure handle
|
||||
*
|
||||
*
|
||||
* @param spi_param SPI master param structure handle
|
||||
*
|
||||
*
|
||||
* @return if successful return EOK
|
||||
*/
|
||||
static uint32 SpiDrvConfigure(struct SpiDriver *spi_drv, struct SpiMasterParam *spi_param)
|
||||
|
@ -1218,7 +1218,7 @@ static uint32 SpiDrvConfigure(struct SpiDriver *spi_drv, struct SpiMasterParam *
|
|||
SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_drv->driver.private_data);
|
||||
|
||||
dev_param->spi_master_param = spi_param;
|
||||
dev_param->spi_master_param->spi_work_mode = dev_param->spi_master_param->spi_work_mode & SPI_MODE_MASK;
|
||||
dev_param->spi_master_param->spi_work_mode = dev_param->spi_master_param->spi_work_mode & SPI_MODE_MASK;
|
||||
|
||||
return EOK;
|
||||
}
|
||||
|
@ -1321,7 +1321,7 @@ DECLARE_HW_IRQ(DMA1_Stream2_IRQn, DMA1_Stream2_IRQHandler, NONE);
|
|||
#endif
|
||||
|
||||
/**
|
||||
* This function RCC clock configuration function
|
||||
* This function RCC clock configuration function
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
|
@ -1329,25 +1329,25 @@ static void RCCConfiguration(void)
|
|||
{
|
||||
#ifdef BSP_USING_SPI1
|
||||
RCC_AHB1PeriphClockCmd(SPI1_GPIO_RCC, ENABLE);
|
||||
|
||||
|
||||
RCC_APB2PeriphClockCmd(RCC_APBPeriph_SPI1, ENABLE);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_SPI2
|
||||
RCC_AHB1PeriphClockCmd(SPI2_GPIO_RCC | SPI2_GPIO_RCC_SCK, ENABLE);
|
||||
|
||||
|
||||
RCC_APB1PeriphClockCmd(RCC_APBPeriph_SPI2, ENABLE);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_SPI3
|
||||
RCC_AHB1PeriphClockCmd(SPI3_GPIO_RCC | SPI3_GPIO_RCC_NSS, ENABLE);
|
||||
|
||||
|
||||
RCC_APB2PeriphClockCmd(RCC_APBPeriph_SPI3, ENABLE);
|
||||
#endif
|
||||
}
|
||||
/**
|
||||
* This function GPIO Configuration function
|
||||
*
|
||||
* This function GPIO Configuration function
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void GPIOConfiguration(void)
|
||||
|
@ -1366,7 +1366,7 @@ static void GPIOConfiguration(void)
|
|||
GPIO_PinAFConfig(SPI1_GPIO, SPI1_SCK_PIN_SOURCE, GPIO_AF_SPI1);
|
||||
GPIO_PinAFConfig(SPI1_GPIO, SPI1_MISO_PIN_SOURCE, GPIO_AF_SPI1);
|
||||
GPIO_PinAFConfig(SPI1_GPIO, SPI1_MOSI_PIN_SOURCE, GPIO_AF_SPI1);
|
||||
|
||||
|
||||
GPIO_Init(SPI1_GPIO, &gpio_initstructure); /*SPI pin initialization*/
|
||||
#endif
|
||||
|
||||
|
@ -1382,7 +1382,7 @@ static void GPIOConfiguration(void)
|
|||
GPIO_PinAFConfig(SPI2_GPIO, SPI2_NSS_PIN_SOURCE, GPIO_AF_SPI2);
|
||||
GPIO_PinAFConfig(SPI2_GPIO, SPI2_MISO_PIN_SOURCE, GPIO_AF_SPI2);
|
||||
GPIO_PinAFConfig(SPI2_GPIO, SPI2_MOSI_PIN_SOURCE, GPIO_AF_SPI2);
|
||||
|
||||
|
||||
GPIO_Init(SPI2_GPIO, &gpio_initstructure);
|
||||
#endif
|
||||
|
||||
|
@ -1397,18 +1397,18 @@ static void GPIOConfiguration(void)
|
|||
GPIO_PinAFConfig(SPI3_GPIO, SPI3_SCK_PIN_SOURCE, GPIO_AF_SPI3);
|
||||
GPIO_PinAFConfig(SPI3_GPIO, SPI3_MISO_PIN_SOURCE, GPIO_AF_SPI3);
|
||||
GPIO_PinAFConfig(SPI3_GPIO, SPI3_MOSI_PIN_SOURCE, GPIO_AF_SPI3);
|
||||
|
||||
|
||||
GPIO_Init(SPI3_GPIO, &gpio_initstructure);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* This function Init the spi bus 、spi driver and attach to the bus
|
||||
* This function Init the spi bus 、spi driver and attach to the bus
|
||||
*
|
||||
* @param spi_bus Spi bus info pointer
|
||||
*
|
||||
*
|
||||
* @param spi_driver Spi driver info pointer
|
||||
*
|
||||
*
|
||||
* @return EOK
|
||||
*/
|
||||
static int BoardSpiBusInit(struct Stm32Spi *stm32spi_bus, struct SpiDriver *spi_driver, char* drv_name)
|
||||
|
@ -1434,14 +1434,14 @@ static int BoardSpiBusInit(struct Stm32Spi *stm32spi_bus, struct SpiDriver *spi_
|
|||
if (EOK != ret) {
|
||||
KPrintf("Board_Spi_init SpiDriverAttachToBus error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* This function SPI bus initialization
|
||||
* This function SPI bus initialization
|
||||
*
|
||||
* @return EOK
|
||||
*/
|
||||
|
@ -1513,16 +1513,16 @@ static int Stm32HwSpiBusInit(void)
|
|||
}
|
||||
|
||||
/**
|
||||
* This function Mount the spi device to the bus
|
||||
* This function Mount the spi device to the bus
|
||||
*
|
||||
* @param bus_name Bus Name
|
||||
*
|
||||
*
|
||||
* @param device_name spi device name
|
||||
*
|
||||
*
|
||||
* @param cs_gpiox GPIO pin configuration handle
|
||||
*
|
||||
*
|
||||
* @param cs_gpio_pin GPIO number
|
||||
*
|
||||
*
|
||||
* @return EOK
|
||||
*/
|
||||
x_err_t HwSpiDeviceAttach(const char *bus_name, const char *device_name, GPIO_TypeDef *cs_gpiox, uint16_t cs_gpio_pin)
|
||||
|
@ -1575,8 +1575,8 @@ x_err_t HwSpiDeviceAttach(const char *bus_name, const char *device_name, GPIO_Ty
|
|||
}
|
||||
|
||||
/**
|
||||
* This function Get DMA information
|
||||
*
|
||||
* This function Get DMA information
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void Stm32GetDmaInfo(void)
|
||||
|
@ -1588,7 +1588,7 @@ static void Stm32GetDmaInfo(void)
|
|||
spi1.dma.dma_rx.channel = DMA_Channel_3;
|
||||
spi1.dma.dma_rx.dma_irq = DMA2_Stream0_IRQn;
|
||||
#endif
|
||||
#ifdef BSP_SPI1_TX_USING_DMA /*SPI1 uses DMA send enable*/
|
||||
#ifdef BSP_SPI1_TX_USING_DMA /*SPI1 uses DMA send enable*/
|
||||
spi1.spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
|
||||
spi1.dma.dma_tx.instance = DMA2_Stream3;
|
||||
spi1.dma.dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN;
|
||||
|
@ -1628,7 +1628,7 @@ static void Stm32GetDmaInfo(void)
|
|||
}
|
||||
|
||||
/**
|
||||
* This function hardware spi initialization
|
||||
* This function hardware spi initialization
|
||||
*
|
||||
* @return EOK
|
||||
*/
|
||||
|
|
Loading…
Reference in New Issue