Support armv8 smp
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TXuian
parent
6114b4618f
commit
bd7966c5a3
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@ -73,7 +73,7 @@ Modification:
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#include "cortex_a72.h"
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#define NR_CPU 1 // maximum number of CPUs
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#define NR_CPU 4 // maximum number of CPUs
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__attribute__((always_inline)) static inline uint64_t EL0_mode() // Set ARM mode to EL0
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{
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@ -1,5 +1,4 @@
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SRC_FILES := boot.S \
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start.c \
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smp.c \
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cortexA72.S
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@ -1,6 +1,6 @@
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export CROSS_COMPILE ?= aarch64-none-elf-
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export DEVICE = -mtune=cortex-a72 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie
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export CFLAGS := $(DEVICE) -Wall -Werror -O0 -g -fno-omit-frame-pointer -fPIC
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export CFLAGS := $(DEVICE) -Wall -Werror -O2 -g -fno-omit-frame-pointer -fPIC
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# export AFLAGS := -c $(DEVICE) -x assembler-with-cpp -D__ASSEMBLY__ -gdwarf-2
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export LFLAGS := $(DEVICE) -Wl,-T -Wl,$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/nxp_ls1028.lds -Wl,--start-group,-lgcc,-lc,--end-group
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export CXXFLAGS :=
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@ -14,35 +14,6 @@ Modification:
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1. No modifications
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*************************************************/
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.section ".text","ax"
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/*
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* bool arm_set_interrupt_state(bool enable)
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*/
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.global arm_set_interrupt_state
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.func arm_set_interrupt_state
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arm_set_interrupt_state:
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mrs x2, spsr_el1
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cmp x0, #0
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b.eq disable_interrupts
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bic x1, x2, #0xc0 // disable IRQ and FIQ
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b set_interrupt_state_end
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disable_interrupts:
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orr x1, x2, #0xc0 // enable IRQ and FIQ
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set_interrupt_state_end:
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msr spsr_el1, x1
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// 测试x2的第7位（FIQ位）
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tst x2, #0x80
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mov x0, #1 //
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b.eq fiq_set_to_0 //
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ret
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fiq_set_to_0:
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mov x0, #0 // 如果FIQ位被设置，则设置x0为0
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ret
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.endfunc
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.global cpu_get_current
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# int cpu_get_current(void)@
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@ -54,17 +25,11 @@ cpu_get_current:
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ret
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.endfunc
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.global get_arm_private_peripheral_base
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# uint32_t get_arm_private_peripheral_base(void)
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.func get_arm_private_peripheral_base
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get_arm_private_peripheral_base:
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# Get base address of private perpherial space
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# mrc p15, 4, r0, c15, c0, 0 Read periph base address
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mov x0, #0x00A00000
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.global psci_call
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psci_call:
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hvc #0
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ret
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.endfunc
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# ------------------------------------------------------------
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# End of cortexA72.s
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@ -45,12 +45,15 @@ Author: AIIT XUOS Lab
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Modification:
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1. No modifications
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*************************************************/
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#include "cortex_a72.h"
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#include <stdint.h>
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#define PSCI_CPUON 0xc4000003
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extern void _boot_start();
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void psci_call(uint64_t fn, uint8_t cpuid, uint64_t entry, uint64_t ctxid);
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void cpu_start_secondary(uint8_t cpu_id)
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{
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return;
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psci_call(PSCI_CPUON, cpu_id, (uintptr_t)&_boot_start, 0);
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}
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void start_smp_cache_broadcast(int cpu_id)
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@ -1,18 +0,0 @@
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#include "core.h"
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#include "cortex_a72.h"
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#include "memlayout.h"
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// void _entry();
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void _boot_start();
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void main();
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extern char end[];
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// entry.S needs one stack per CPU.
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__attribute__((aligned(16))) char stack0[4096 * NR_CPU];
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// entry.S jumps here in supervisor mode (EL1) on stack0.
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// in qemu-system-aarch64, default EL (Exeception Level) is 1.
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void start()
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{
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main();
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}
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@ -15,10 +15,7 @@
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#include "clock_common_op.h"
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#include "log.h"
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// armv8 generic timer driver
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#define CNTV_CTL_ENABLE (1 << 0)
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#define CNTV_CTL_IMASK (1 << 1)
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#define CNTV_CTL_ISTATUS (1 << 2)
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@ -26,14 +23,16 @@
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static void enable_timer()
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{
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uint32_t c = r_cntv_ctl_el0();
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c = CNTV_CTL_ENABLE;
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c |= CNTV_CTL_ENABLE;
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c &= ~CNTV_CTL_IMASK;
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w_cntv_ctl_el0(c);
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}
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static void disable_timer()
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{
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uint32_t c = r_cntv_ctl_el0();
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c = CNTV_CTL_IMASK;
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c |= CNTV_CTL_IMASK;
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c &= ~CNTV_CTL_ENABLE;
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w_cntv_ctl_el0(c);
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}
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@ -26,9 +26,9 @@ Author: AIIT XUOS Lab
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Modification:
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1. first version
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*************************************************/
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#include <assert.h>
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#include <stdio.h>
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#include <stdint.h>
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#include "assert.h"
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#include "core.h"
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#include "exception_registers.h"
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#include "multicores.h"
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@ -50,7 +50,7 @@ void kernel_abort_handler(struct trapframe* tf)
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case 0b100001:
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iabort_handler(tf);
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break;
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default:
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default: {
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uint64_t ec = (esr >> 26) & 0x3f;
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uint64_t iss = esr & 0x1ffffff;
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ERROR("esr: %016lx %016lx %016lx\n", esr, ec, iss);
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@ -58,6 +58,7 @@ void kernel_abort_handler(struct trapframe* tf)
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ERROR("Current Task: %s.\n", cur_cpu()->task->name);
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panic("Unimplemented Error Occured.\n");
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}
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}
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panic("Return from abort handler.\n");
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}
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@ -85,9 +86,9 @@ void syscall_arch_handler(struct trapframe* tf)
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case 0b100001:
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iabort_handler(tf);
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break;
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default:
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printf("USYSCALL: unexpected ec: %016lx", esr);
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printf(" elr = %016lx far = %016lx\n", r_elr_el1(), r_far_el1());
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default: {
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ERROR("USYSCALL: unexpected ec: %016lx", esr);
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ERROR(" elr = %016lx far = %016lx\n", r_elr_el1(), r_far_el1());
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// kill error task
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xizi_enter_kernel();
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assert(cur_cpu()->task != NULL);
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@ -96,3 +97,4 @@ void syscall_arch_handler(struct trapframe* tf)
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panic("dabort end should never be reashed.\n");
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}
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}
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}
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@ -11,7 +11,7 @@ cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mflo
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endif
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ifeq ($(BOARD), ok1028a-c)
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toolchain ?= aarch64-none-elf-
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user_ldflags = -N
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user_ldflags = -N -Ttext 0
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cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
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endif
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