xidatong-riscv64 support reboot cmd on nuttx

Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/configs/btnsh/defconfig

@@ -57,6 +57,7 @@ CONFIG_UART0_SERIAL_CONSOLE=y
 CONFIG_READLINE_TABCOMPLETION=y
 CONFIG_SCHED_HPWORK=y
 CONFIG_DEV_GPIO=y
+CONFIG_BOARDCTL_RESET=y
 CONFIG_BSP_USING_CH438=y
 CONFIG_CH438_EXTUART2=y
 CONFIG_CH438_EXTUART2_BAUD=9600

Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/configs/loransh/defconfig

@@ -57,6 +57,7 @@ CONFIG_UART0_SERIAL_CONSOLE=y
 CONFIG_READLINE_TABCOMPLETION=y
 CONFIG_SCHED_HPWORK=y
 CONFIG_DEV_GPIO=y
+CONFIG_BOARDCTL_RESET=y
 CONFIG_BSP_USING_CH438=y
 CONFIG_CH438_EXTUART3=y
 CONFIG_SUPPORT_CONNECTION_FRAMEWORK=y

Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/configs/nsh/defconfig

@@ -57,3 +57,4 @@ CONFIG_UART0_SERIAL_CONSOLE=y
 CONFIG_READLINE_TABCOMPLETION=y
 CONFIG_SCHED_HPWORK=y
 CONFIG_DEV_GPIO=y
+CONFIG_BOARDCTL_RESET=y

Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/configs/zbnsh/defconfig

@@ -57,6 +57,7 @@ CONFIG_UART0_SERIAL_CONSOLE=y
 CONFIG_READLINE_TABCOMPLETION=y
 CONFIG_SCHED_HPWORK=y
 CONFIG_DEV_GPIO=y
+CONFIG_BOARDCTL_RESET=y
 CONFIG_BSP_USING_CH438=y
 CONFIG_CH438_EXTUART1=y
 CONFIG_SUPPORT_CONNECTION_FRAMEWORK=y

Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/Makefile

@@ -22,6 +22,10 @@ include $(TOPDIR)/Make.defs
 
 CSRCS  = k210_bringup.c k210_boot.c
 
+ifeq ($(CONFIG_BOARDCTL_RESET),y)
+CSRCS += k210_reset.c
+endif
+
 ifeq ($(CONFIG_BOARDCTL),y)
 CSRCS += k210_appinit.c
 endif

Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_reset.c

@@ -0,0 +1,60 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+ * @file k210_reset.c
+ * @brief k210_reset.c support reboot
+ * @version 1.0
+ * @author AIIT XUOS Lab
+ * @date 2022.06.27
+ */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/board.h>
+#include <nuttx/arch.h>
+
+#ifdef CONFIG_BOARDCTL_RESET
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_reset
+ *
+ * Description:
+ *   Reset board.  Support for this function is required by board-level
+ *   logic if CONFIG_BOARDCTL_RESET is selected.
+ *
+ * Input Parameters:
+ *   status - Status information provided with the reset event.  This
+ *            meaning of this status information is board-specific.  If not
+ *            used by a board, the value zero may be provided in calls to
+ *            board_reset().
+ *
+ * Returned Value:
+ *   If this function returns, then it was not possible to power-off the
+ *   board due to some constraints.  The return value int this case is a
+ *   board-specific reason for the failure to shutdown.
+ *
+ ****************************************************************************/
+int board_reset(int status)
+{
+  up_systemreset();
+  return 0;
+}
+
+#endif /* CONFIG_BOARDCTL_RESET */

Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/Kconfig

@@ -0,0 +1,245 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_RISCV
+comment "RISC-V Options"
+
+choice
+	prompt "RISC-V chip selection"
+	default ARCH_CHIP_RISCV_CUSTOM
+
+config ARCH_CHIP_FE310
+	bool "SiFive FE310"
+	select ARCH_RV32
+	select ARCH_RV_ISA_M
+	select ARCH_RV_ISA_A
+	select ARCH_RV_ISA_C
+	---help---
+		SiFive FE310 processor (E31 RISC-V Core with MAC extensions).
+
+config ARCH_CHIP_K210
+	bool "Kendryte K210"
+	select ARCH_RV64
+	select ARCH_RV_ISA_M
+	select ARCH_RV_ISA_A
+	select ARCH_RV_ISA_C
+	select ARCH_HAVE_MPU
+	select ARCH_HAVE_TESTSET
+	select ARCH_HAVE_MULTICPU
+	select ARCH_HAVE_RESET
+	---help---
+		Kendryte K210 processor (RISC-V 64bit core with GC extensions)
+
+config ARCH_CHIP_LITEX
+	bool "Enjoy Digital LITEX VEXRISCV"
+	select ARCH_RV32
+	select ARCH_RV_ISA_M
+	select ARCH_RV_ISA_A
+	---help---
+		Enjoy Digital LITEX VEXRISCV softcore processor (RV32IMA).
+
+config ARCH_CHIP_BL602
+	bool "BouffaloLab BL602"
+	select ARCH_RV32
+	select ARCH_RV_ISA_M
+	select ARCH_RV_ISA_A
+	select ARCH_RV_ISA_C
+	select ARCH_HAVE_FPU
+	select ARCH_HAVE_RESET
+	---help---
+		BouffaloLab BL602(rv32imfc)
+
+config ARCH_CHIP_ESP32C3
+	bool "Espressif ESP32-C3"
+	select ARCH_RV32
+	select ARCH_RV_ISA_M
+	select ARCH_RV_ISA_C
+	select ARCH_VECNOTIRQ
+	select ARCH_HAVE_RESET
+	select LIBC_ARCH_ATOMIC
+	select LIBC_ARCH_MEMCPY
+	select LIBC_ARCH_MEMCHR
+	select LIBC_ARCH_MEMCMP
+	select LIBC_ARCH_MEMMOVE
+	select LIBC_ARCH_MEMSET
+	select LIBC_ARCH_STRCHR
+	select LIBC_ARCH_STRCMP
+	select LIBC_ARCH_STRCPY
+	select LIBC_ARCH_STRLCPY
+	select LIBC_ARCH_STRNCPY
+	select LIBC_ARCH_STRLEN
+	select LIBC_ARCH_STRNLEN
+	select ARCH_HAVE_TEXT_HEAP
+	select ARCH_HAVE_BOOTLOADER
+	---help---
+		Espressif ESP32-C3 (RV32IMC).
+
+config ARCH_CHIP_C906
+	bool "THEAD C906"
+	select ARCH_RV64
+	select ARCH_RV_ISA_M
+	select ARCH_RV_ISA_A
+	select ARCH_RV_ISA_C
+	select ARCH_HAVE_FPU
+	select ARCH_HAVE_DPFPU
+	select ARCH_HAVE_MPU
+	---help---
+		THEAD C906 processor (RISC-V 64bit core with GCVX extensions).
+
+config ARCH_CHIP_MPFS
+	bool "MicroChip Polarfire (MPFS)"
+	select ARCH_RV64
+	select ARCH_RV_ISA_M
+	select ARCH_RV_ISA_A
+	select ARCH_RV_ISA_C
+	select ARCH_HAVE_FPU
+	select ARCH_HAVE_DPFPU
+	select ARCH_HAVE_MPU
+	select ARCH_HAVE_MMU
+	select ARCH_MMU_TYPE_SV39
+	select ARCH_HAVE_RESET
+	select ARCH_HAVE_SPI_CS_CONTROL
+	select ARCH_HAVE_PWM_MULTICHAN
+	select PMP_HAS_LIMITED_FEATURES
+	---help---
+		MicroChip Polarfire processor (RISC-V 64bit core with GCVX extensions).
+
+config ARCH_CHIP_RV32M1
+	bool "NXP RV32M1"
+	select ARCH_RV32
+	select ARCH_RV_ISA_M
+	select ARCH_RV_ISA_C
+	---help---
+		NXP RV32M1 processor (RISC-V Core with PULP extensions).
+
+config ARCH_CHIP_QEMU_RV
+	bool "QEMU RV"
+	select ARCH_HAVE_FPU
+	select ARCH_HAVE_DPFPU
+	select ARCH_HAVE_MULTICPU
+	---help---
+		QEMU Generic RV32/RV64 processor
+
+config ARCH_CHIP_RISCV_CUSTOM
+	bool "Custom RISC-V chip"
+	select ARCH_CHIP_CUSTOM
+	---help---
+		Select this option if there is no directory for the chip under arch/risc-v/src/.
+
+endchoice
+
+config ARCH_RV32
+	bool
+	default n
+
+config ARCH_RV64
+	bool
+	default n
+	select LIBC_ARCH_ELF_64BIT if LIBC_ARCH_ELF
+
+config ARCH_RV_ISA_M
+	bool
+	default n
+
+config ARCH_RV_ISA_A
+	bool
+	default n
+	select ARCH_HAVE_TESTSET
+
+config ARCH_RV_ISA_C
+	bool
+	default n
+
+config ARCH_FAMILY
+	string
+	default "rv32"		if ARCH_RV32
+	default "rv64"		if ARCH_RV64
+
+config ARCH_CHIP
+	string
+	default "fe310"		if ARCH_CHIP_FE310
+	default "k210"		if ARCH_CHIP_K210
+	default "litex"		if ARCH_CHIP_LITEX
+	default "bl602"		if ARCH_CHIP_BL602
+	default "esp32c3"	if ARCH_CHIP_ESP32C3
+	default "c906"		if ARCH_CHIP_C906
+	default "mpfs"		if ARCH_CHIP_MPFS
+	default "rv32m1"	if ARCH_CHIP_RV32M1
+	default "qemu-rv"	if ARCH_CHIP_QEMU_RV
+
+config ARCH_RISCV_INTXCPT_EXTENSIONS
+	bool "RISC-V Integer Context Extensions"
+	default n
+	depends on RV32M1_OPENISA_TOOLCHAIN
+	---help---
+		RISC-V could be customized with extensions. Some Integer Context
+		Registers have to be saved and restored when Contexts switch.
+
+if ARCH_RISCV_INTXCPT_EXTENSIONS
+
+config ARCH_RISCV_INTXCPT_EXTREGS
+	int "Number of Extral RISC-V Integer Context Registers"
+	default 0
+
+endif
+
+config ARCH_MMU_TYPE_SV39
+	bool
+	default n
+
+# MPU has certain architecture dependent configurations, which are presented
+# here. Default is that the full RISC-V PMP specification is supported.
+
+config PMP_HAS_LIMITED_FEATURES
+	bool
+	default n
+
+config ARCH_MPU_MIN_BLOCK_SIZE
+	int "Minimum MPU (PMP) block size"
+	default 4	if !PMP_HAS_LIMITED_FEATURES
+
+config ARCH_MPU_HAS_TOR
+	bool "PMP supports TOR"
+	default y	if !PMP_HAS_LIMITED_FEATURES
+
+config ARCH_MPU_HAS_NO4
+	bool "PMP supports NO4"
+	default y	if !PMP_HAS_LIMITED_FEATURES
+
+config ARCH_MPU_HAS_NAPOT
+	bool "PMP supports NAPOT"
+	default y	if !PMP_HAS_LIMITED_FEATURES
+
+source "arch/risc-v/src/opensbi/Kconfig"
+source "arch/risc-v/src/common/Kconfig"
+
+if ARCH_CHIP_FE310
+source "arch/risc-v/src/fe310/Kconfig"
+endif
+if ARCH_CHIP_K210
+source "arch/risc-v/src/k210/Kconfig"
+endif
+if ARCH_CHIP_LITEX
+source "arch/risc-v/src/litex/Kconfig"
+endif
+if ARCH_CHIP_BL602
+source "arch/risc-v/src/bl602/Kconfig"
+endif
+if ARCH_CHIP_ESP32C3
+source "arch/risc-v/src/esp32c3/Kconfig"
+endif
+if ARCH_CHIP_C906
+source "arch/risc-v/src/c906/Kconfig"
+endif
+if ARCH_CHIP_MPFS
+source "arch/risc-v/src/mpfs/Kconfig"
+endif
+if ARCH_CHIP_RV32M1
+source "arch/risc-v/src/rv32m1/Kconfig"
+endif
+if ARCH_CHIP_QEMU_RV
+source "arch/risc-v/src/qemu-rv/Kconfig"
+endif
+endif

Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/Make.defs

@@ -54,7 +54,7 @@ endif
 
 # Specify our C code within this directory to be included
 CHIP_CSRCS  = k210_allocateheap.c k210_clockconfig.c
-CHIP_CSRCS += k210_irq.c k210_irq_dispatch.c
+CHIP_CSRCS += k210_irq.c k210_irq_dispatch.c k210_systemreset.c
 CHIP_CSRCS += k210_lowputc.c k210_serial.c k210_fpioa.c
 CHIP_CSRCS += k210_start.c k210_timerisr.c k210_gpiohs.c
 

Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/risc-v/src/k210/k210_systemreset.c

@@ -0,0 +1,64 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+ * @file k210_systemreset.c
+ * @briefk210_systemreset.c support reboot
+ * @version 1.0
+ * @author AIIT XUOS Lab
+ * @date 2022.06.27
+ */
+
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+
+#include "riscv_internal.h"
+#include "hardware/k210_memorymap.h"
+ 
+ typedef struct _k210_soft_reset
+{
+    uint32_t soft_reset : 1;
+    uint32_t reserved : 31;
+} __attribute__((packed, aligned(4))) k210_soft_reset_t;
+
+volatile k210_soft_reset_t *const reset = (volatile k210_soft_reset_t *)(K210_SYSCTL_BASE + 0x30);
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_systemreset
+ *
+ * Description:
+ *   Internal reset logic.
+ *
+ ****************************************************************************/
+
+void up_systemreset(void)
+{
+  reset->soft_reset = 1;
+
+  /* Wait for the reset */
+
+  for (; ; );
+}
+