Support XiZi_AIoT
This commit is contained in:
TXuian
@@ -0,0 +1,4 @@
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# The following three platforms support compatiable instructions.
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SRC_DIR := armv7-a
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include $(KERNEL_ROOT)/compiler.mk
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@@ -0,0 +1,4 @@
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# The following three platforms support compatiable instructions.
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SRC_DIR := cortex-a9
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include $(KERNEL_ROOT)/compiler.mk
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@@ -0,0 +1,3 @@
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SRC_DIR := uart_io_for_imx6q_sabrelite
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include $(KERNEL_ROOT)/compiler.mk
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+3
@@ -0,0 +1,3 @@
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SRC_FILES := imx_uart.c iomux_v3.c
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include $(KERNEL_ROOT)/compiler.mk
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Executable
+189
@@ -0,0 +1,189 @@
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/*
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* Copyright (c) 2010-2012, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file imx_uart.c
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* @brief support imx6q uart function
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* @version 3.0
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* @author AIIT XUOS Lab
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* @date 2023.09.08
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*/
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/*************************************************
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File name: imx_uart.c
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Description: imx6q board uart function
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Others:
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History:
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1. Date: 2023-08-28
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Author: AIIT XUOS Lab
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Modification:
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1. first version
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*************************************************/
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#include "crm_regs.h"
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#include "regs_pins.h"
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#include "regsuart.h"
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#include "soc_memory_map.h"
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#include "imx_uart.h"
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#include "uart_common_ope.h"
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static void UartInitGpio(void)
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{
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/* UART1 TXD */
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mxc_iomux_v3_setup_pad(MX6Q_PAD_SD3_DAT6__UART1_TXD);
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/* UART1 RXD */
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mxc_iomux_v3_setup_pad(MX6Q_PAD_SD3_DAT7__UART1_RXD);
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/* UART2 TXD */
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mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D26__UART2_TXD);
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/* UART2 RXD */
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mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D27__UART2_RXD);
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}
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static uint32_t GetUartClk(void)
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{
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uint32_t freq = 80000000, reg, podf;
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reg = mmio_read(MXC_CCM_CSCDR1);
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podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
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freq /= (podf + 1);
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return freq;
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}
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static void UartInitRegsInstance(uint32_t instance, uint32_t uart_baud_rate)
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{
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uint32_t uart_clk;
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HW_UART_UCR1_WR(instance, 0);
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HW_UART_UCR2_WR(instance, 0);
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while (!(HW_UART_UCR2(instance).B.SRST))
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;
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HW_UART_UCR3_WR(instance, 0x0704);
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HW_UART_UCR4_WR(instance, 0x8000);
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HW_UART_UESC_WR(instance, 0x002B);
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HW_UART_UTIM_WR(instance, 0);
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HW_UART_UTS_WR(instance, 0);
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uart_clk = GetUartClk();
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HW_UART_UFCR_WR(instance, 4 << 7);
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HW_UART_UBIR_WR(instance, 0x0F);
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HW_UART_UBMR_WR(instance, uart_clk / (2 * uart_baud_rate));
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HW_UART_UCR2_WR(instance, BM_UART_UCR2_WS | BM_UART_UCR2_IRTS | BM_UART_UCR2_RXEN | BM_UART_UCR2_TXEN | BM_UART_UCR2_SRST);
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HW_UART_UCR1_WR(instance, 1);
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}
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__attribute__((__always_inline__)) static inline void UartPutCharInstance(uint32_t instance, uint8_t* ch)
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{
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/* Wait for Tx FIFO not full */
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while (HW_UART_UTS(instance).B.TXFULL)
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;
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if ((char)*ch == '\n') {
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HW_UART_UTXD_WR(instance, '\r');
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while (HW_UART_UTS(instance).B.TXFULL)
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;
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}
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HW_UART_UTXD_WR(instance, *ch);
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}
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__attribute__((__always_inline__)) static inline uint8_t UartGetCharInstance(uint32_t instance)
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{
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uint32_t read_data;
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/* If Rx FIFO has no data ready */
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if (!(HW_UART_USR2(instance).B.RDR))
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return 0xFF;
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read_data = HW_UART_URXD_RD(instance);
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/* If error are detected */
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if (read_data & 0x7C00)
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return 0xFF;
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return (uint8_t) read_data;
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}
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__attribute__((__always_inline__)) static inline uint32_t UartGetIrqnumInstance(uint32_t instance)
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{
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return UART_IRQS(instance);
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}
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static inline void UartInitInstance(uint32_t instance)
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{
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static char init = 0;
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if (init == 0) {
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mxc_iomux_v3_init((void*)IOMUXC_BASE_ADDR);
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UartInitGpio();
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}
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init = 1;
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UartInitRegsInstance(instance, UART_BAUD_RATE);
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}
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static void UartPutChar(uint8_t ch)
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{
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UartPutCharInstance(IMX6Q_UART_INSTANCE, &ch);
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}
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static uint8_t UartGetChar()
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{
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return UartGetCharInstance(IMX6Q_UART_INSTANCE);
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}
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static void UartInit()
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{
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UartInitInstance(IMX6Q_UART_INSTANCE);
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}
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static uint32_t UartGetIrqnum()
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{
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return UartGetIrqnumInstance(IMX6Q_UART_INSTANCE);
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}
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/// @todo make this static
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static struct XiziSerialDriver hardkernel_serial_driver = (struct XiziSerialDriver) {
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.sys_serial_init = UartInit,
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.get_serial_irqnum = UartGetIrqnum,
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.putc = UartPutChar,
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.getc = UartGetChar,
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};
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struct XiziSerialDriver* hardkernel_uart_init(struct TraceTag* hardkernel_tag)
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{
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hardkernel_serial_driver.sys_serial_init();
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return &hardkernel_serial_driver;
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}
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+584
@@ -0,0 +1,584 @@
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/*
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* Copyright (C) 2010-2012 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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/**
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* @file crm_regs.h
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* @brief support imx6q clock control module define, reference from u-boot-2009-08/cpu/arm_cortexa8/mx6/crm_regs.h
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* @version 3.0
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* @author AIIT XUOS Lab
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* @date 2023.09.08
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*/
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#ifndef __ARCH_ARM_MACH_MX6_CRM_REGS_H__
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#define __ARCH_ARM_MACH_MX6_CRM_REGS_H__
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#define MXC_CCM_BASE CCM_BASE_ADDR
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// /* Register addresses of CCM*/
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// #define MXC_CCM_CCR (MXC_CCM_BASE + 0x00)
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// #define MXC_CCM_CCDR (MXC_CCM_BASE + 0x04)
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// #define MXC_CCM_CSR (MXC_CCM_BASE + 0x08)
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// #define MXC_CCM_CCSR (MXC_CCM_BASE + 0x0C)
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// #define MXC_CCM_CACRR (MXC_CCM_BASE + 0x10)
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// #define MXC_CCM_CBCDR (MXC_CCM_BASE + 0x14)
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// #define MXC_CCM_CBCMR (MXC_CCM_BASE + 0x18)
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// #define MXC_CCM_CSCMR1 (MXC_CCM_BASE + 0x1C)
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// #define MXC_CCM_CSCMR2 (MXC_CCM_BASE + 0x20)
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#define MXC_CCM_CSCDR1 (MXC_CCM_BASE + 0x24)
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// #define MXC_CCM_CS1CDR (MXC_CCM_BASE + 0x28)
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// #define MXC_CCM_CS2CDR (MXC_CCM_BASE + 0x2C)
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// #define MXC_CCM_CDCDR (MXC_CCM_BASE + 0x30)
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// #define MXC_CCM_CHSCDR (MXC_CCM_BASE + 0x34)
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// #define MXC_CCM_CSCDR2 (MXC_CCM_BASE + 0x38)
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// #define MXC_CCM_CSCDR3 (MXC_CCM_BASE + 0x3C)
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// #define MXC_CCM_CSCDR4 (MXC_CCM_BASE + 0x40)
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// #define MXC_CCM_CWDR (MXC_CCM_BASE + 0x44)
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// #define MXC_CCM_CDHIPR (MXC_CCM_BASE + 0x48)
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// #define MXC_CCM_CDCR (MXC_CCM_BASE + 0x4C)
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// #define MXC_CCM_CTOR (MXC_CCM_BASE + 0x50)
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// #define MXC_CCM_CLPCR (MXC_CCM_BASE + 0x54)
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// #define MXC_CCM_CISR (MXC_CCM_BASE + 0x58)
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// #define MXC_CCM_CIMR (MXC_CCM_BASE + 0x5C)
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// #define MXC_CCM_CCOSR (MXC_CCM_BASE + 0x60)
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// #define MXC_CCM_CGPR (MXC_CCM_BASE + 0x64)
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// #define MXC_CCM_CCGR0 (MXC_CCM_BASE + 0x68)
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// #define MXC_CCM_CCGR1 (MXC_CCM_BASE + 0x6C)
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// #define MXC_CCM_CCGR2 (MXC_CCM_BASE + 0x70)
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// #define MXC_CCM_CCGR3 (MXC_CCM_BASE + 0x74)
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// #define MXC_CCM_CCGR4 (MXC_CCM_BASE + 0x78)
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// #define MXC_CCM_CCGR5 (MXC_CCM_BASE + 0x7C)
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// #define MXC_CCM_CCGR6 (MXC_CCM_BASE + 0x80)
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// #define MXC_CCM_CCGR7 (MXC_CCM_BASE + 0x80)
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// #define MXC_CCM_CMEOR (MXC_CCM_BASE + 0x88)
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// /* Define the bits in register CCR */
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// #define MXC_CCM_CCR_RBC_EN (1 << 27)
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// #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21)
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// #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET (21)
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// #define MXC_CCM_CCR_WB_COUNT_MASK (0x7)
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// #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
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// #define MXC_CCM_CCR_COSC_EN (1 << 12)
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// #define MXC_CCM_CCR_OSCNT_MASK (0xFF)
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// #define MXC_CCM_CCR_OSCNT_OFFSET (0)
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// /* Define the bits in register CCDR */
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// #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16)
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// #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17)
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// /* Define the bits in register CSR */
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// #define MXC_CCM_CSR_COSC_READY (1 << 5)
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// #define MXC_CCM_CSR_REF_EN_B (1 << 0)
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// /* Define the bits in register CCSR */
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// #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15)
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// #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14)
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// #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13)
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// #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12)
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// #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11)
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// #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10)
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// #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9)
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// #define MXC_CCM_CCSR_STEP_SEL (1 << 8)
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// #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
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// #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
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// #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
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// /* Define the bits in register CACRR */
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// #define MXC_CCM_CACRR_ARM_PODF_OFFSET (0)
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// #define MXC_CCM_CACRR_ARM_PODF_MASK (0x7)
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// /* Define the bits in register CBCDR */
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// #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27)
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// #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET (27)
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// #define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26)
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// #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
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// #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19)
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// #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET (19)
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// #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16)
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// #define MXC_CCM_CBCDR_AXI_PODF_OFFSET (16)
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||||
// #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
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||||
// #define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10)
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||||
// #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
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||||
// #define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8)
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// #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7)
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||||
// #define MXC_CCM_CBCDR_AXI_SEL (1 << 6)
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// #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3)
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||||
// #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET (3)
|
||||
// #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0)
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||||
// #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET (0)
|
||||
|
||||
// /* Define the bits in register CBCMR */
|
||||
// #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29)
|
||||
// #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET (29)
|
||||
// #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26)
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||||
// #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET (26)
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||||
// #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23)
|
||||
// #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET (23)
|
||||
// #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21)
|
||||
// #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET (21)
|
||||
// #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20)
|
||||
// #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18)
|
||||
// #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET (18)
|
||||
// #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
|
||||
// #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (16)
|
||||
// #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
|
||||
// #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14)
|
||||
// #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12)
|
||||
// #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET (12)
|
||||
// #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
|
||||
// #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
|
||||
// #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8)
|
||||
// #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET (8)
|
||||
// #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4)
|
||||
// #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET (4)
|
||||
// #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1)
|
||||
// #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0)
|
||||
|
||||
// /* Define the bits in register CSCMR1 */
|
||||
// #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
|
||||
// #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET (29)
|
||||
// #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27)
|
||||
// #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET (27)
|
||||
// #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23)
|
||||
// #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET (23)
|
||||
// #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
|
||||
// #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET (20)
|
||||
// #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
|
||||
// #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
|
||||
// #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
|
||||
// #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16)
|
||||
// #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14)
|
||||
// #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET (14)
|
||||
// #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
|
||||
// #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
|
||||
// #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10)
|
||||
// #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (10)
|
||||
// #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK (0x3F)
|
||||
// /* On SoloLite */
|
||||
// #define MXC_CCM_CSCMR1_PERCLK_SEL (1 << 6)
|
||||
|
||||
// /* Define the bits in register CSCMR2 */
|
||||
// #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19)
|
||||
// #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET (19)
|
||||
// #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
|
||||
// #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
|
||||
// #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2)
|
||||
// #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET (2)
|
||||
// /* On SoloLite */
|
||||
// #define MXC_CCM_CSCMR2_EXTAUDIO_CLK_SEL_MASK (0x3 << 19)
|
||||
// #define MXC_CCM_CSCMR2_EXTAUDIO_CLK_SEL_OFFSET 19
|
||||
|
||||
// /* Define the bits in register CSCDR1 */
|
||||
// #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25)
|
||||
// #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET (25)
|
||||
// #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22)
|
||||
// #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET (22)
|
||||
// #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19)
|
||||
// #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET (19)
|
||||
// #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16)
|
||||
// #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET (16)
|
||||
// #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11)
|
||||
// #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET (11)
|
||||
// #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8)
|
||||
// #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
|
||||
// #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6)
|
||||
// #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
|
||||
#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x3F)
|
||||
#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
|
||||
// /* On Sololite */
|
||||
// #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
|
||||
|
||||
// /* Define the bits in register CS1CDR */
|
||||
// #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
|
||||
// #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET (25)
|
||||
// #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16)
|
||||
// #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET (16)
|
||||
// #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9)
|
||||
// #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET (9)
|
||||
// #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
|
||||
// #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
|
||||
// #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
|
||||
// #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
|
||||
// /* On SoloLite */
|
||||
// #define MXC_CCM_CS1CDR_EXTAUDIO_CLK_PODF_MASK (0x7 << 25)
|
||||
// #define MXC_CCM_CS1CDR_EXTAUDIO_CLK_PODF_OFFSET 25
|
||||
// #define MXC_CCM_CS1CDR_EXTAUDIO_CLK_PRED_MASK (0x7 << 9)
|
||||
// #define MXC_CCM_CS1CDR_EXTAUDIO_CLK_PRED_OFFSET 9
|
||||
|
||||
// /* Define the bits in register CS2CDR */
|
||||
// #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
|
||||
// #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET (21)
|
||||
// #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18)
|
||||
// #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET (18)
|
||||
// #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16)
|
||||
// #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET (16)
|
||||
// #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
|
||||
// #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET (12)
|
||||
// #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
|
||||
// #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET (9)
|
||||
// #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
|
||||
// #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
|
||||
// #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
|
||||
// #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
|
||||
|
||||
// /* Define the bits in register CDCDR */
|
||||
// #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29)
|
||||
// #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET (29)
|
||||
// #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28)
|
||||
// #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
|
||||
// #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
|
||||
// #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 19)
|
||||
// #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
|
||||
// #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20)
|
||||
// #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET (20)
|
||||
// #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12)
|
||||
// #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (12)
|
||||
// #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9)
|
||||
// #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
|
||||
// #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7)
|
||||
// #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET (7)
|
||||
// /* On SoloLite */
|
||||
// #define MXC_CCM_CDCDR_MSHC_XMSCKI_PODF_MASK (0x7 << 29)
|
||||
// #define MXC_CCM_CDCDR_MSHC_XMSCKI_PODF_OFFSET 29
|
||||
// #define MXC_CCM_CDCDR_MSHC_XMSCLI_CLK_SEL (0x1 << 28)
|
||||
|
||||
// /* Define the bits in register CHSCCDR */
|
||||
// #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
|
||||
// #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET (15)
|
||||
// #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12)
|
||||
// #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET (12)
|
||||
// #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9)
|
||||
// #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET (9)
|
||||
// #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
|
||||
// #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET (6)
|
||||
// #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3)
|
||||
// #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET (3)
|
||||
// #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
|
||||
// #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET (0)
|
||||
// /* On Sololite */
|
||||
// #define MXC_CCM_CHSCCDR_EPDC_AXI_PRE_CLK_SEL_MASK (0x7 << 15)
|
||||
// #define MXC_CCM_CHSCCDR_EPDC_AXI_PRE_CLK_SEL_OFFSET 15
|
||||
// #define MXC_CCM_CHSCCDR_EPDC_AXI_PODF_MASK (0x7 << 12)
|
||||
// #define MXC_CCM_CHSCCDR_EPDC_AXI_PODF_OFFSET 12
|
||||
// #define MXC_CCM_CHSCCDR_EPDC_AXI_CLK_SEL_MASK (0x7 << 9)
|
||||
// #define MXC_CCM_CHSCCDR_EPDC_AXI_CLK_SEL_OFFSET 9
|
||||
// #define MXC_CCM_CHSCCDR_PXP_AXI_PRE_CLK_SEL_MASK (0x7 << 6)
|
||||
// #define MXC_CCM_CHSCCDR_PXP_AXI_PRE_CLK_SEL_OFFSET 6
|
||||
// #define MXC_CCM_CHSCCDR_PXP_AXI_PODF_MASK (0x7 << 3)
|
||||
// #define MXC_CCM_CHSCCDR_PXP_AXI_PODF_OFFSET 3
|
||||
// #define MXC_CCM_CHSCCDR_PXP_AXI_CLK_SEL_MASK 0x7
|
||||
// #define MXC_CCM_CHSCCDR_PXP_AXI_CLK_SEL_OFFSET 0
|
||||
|
||||
// /* Define the bits in register CSCDR2 */
|
||||
// #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19)
|
||||
// #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET (19)
|
||||
// #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
|
||||
// #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET (15)
|
||||
// #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12)
|
||||
// #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET (12)
|
||||
// #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9)
|
||||
// #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET (9)
|
||||
// #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
|
||||
// #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET (6)
|
||||
// #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3)
|
||||
// #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET (3)
|
||||
// #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK (0x7)
|
||||
// #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET (0)
|
||||
// /* On SoloLite */
|
||||
// #define MXC_CCM_CSCDR2_ECSPI_CLK_SEL (0x1 << 18)
|
||||
// #define MXC_CCM_CSCDR2_EPDC_PIX_PRE_CLK_SEL_MASK (0x7 << 15)
|
||||
// #define MXC_CCM_CSCDR2_EPDC_PIX_PRE_CLK_SEL_OFFSET 15
|
||||
// #define MXC_CCM_CSCDR2_EPDC_PIX_PODF_MASK (0x7 << 12)
|
||||
// #define MXC_CCM_CSCDR2_EPDC_PIX_PODF_OFFSET 12
|
||||
// #define MXC_CCM_CSCDR2_EPDC_PIX_CLK_SEL_MASK (0X7 << 9)
|
||||
// #define MXC_CCM_CSCDR2_EPDC_PIX_CLK_SEL_OFFSET 9
|
||||
// #define MXC_CCM_CSCDR2_LCDIF_PIX_PRE_CLK_SEL_MASK (0x7 << 6)
|
||||
// #define MXC_CCM_CSCDR2_LCDIF_PIX_PRE_CLK_SEL_OFFSET 6
|
||||
// #define MXC_CCM_CSCDR2_LCDIF_PIX_PODF_MASK (0x7 << 3)
|
||||
// #define MXC_CCM_CSCDR2_LCDIF_PIX_PODF_OFFSET 3
|
||||
// #define MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK 0x7
|
||||
// #define MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET 0
|
||||
|
||||
// /* Define the bits in register CSCDR3 */
|
||||
// #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16)
|
||||
// #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET (16)
|
||||
// #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14)
|
||||
// #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET (14)
|
||||
// #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11)
|
||||
// #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET (11)
|
||||
// #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9)
|
||||
// #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET (9)
|
||||
|
||||
// /* Define the bits in register CDHIPR */
|
||||
// #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
|
||||
// #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
|
||||
// #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4)
|
||||
// #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3)
|
||||
// #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2)
|
||||
// #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1)
|
||||
// #define MXC_CCM_CDHIPR_AXI_PODF_BUSY (1)
|
||||
|
||||
// /* Define the bits in register CLPCR */
|
||||
// #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27)
|
||||
// #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26)
|
||||
// #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25)
|
||||
// #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24)
|
||||
// #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23)
|
||||
// #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22)
|
||||
// #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21)
|
||||
// #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19)
|
||||
// #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17)
|
||||
// #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 16)
|
||||
// #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
|
||||
// #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
|
||||
// #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9)
|
||||
// #define MXC_CCM_CLPCR_VSTBY (1 << 8)
|
||||
// #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
|
||||
// #define MXC_CCM_CLPCR_SBYOS (1 << 6)
|
||||
// #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
|
||||
// #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
|
||||
// #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
|
||||
// #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
|
||||
// #define MXC_CCM_CLPCR_LPM_MASK (0x3)
|
||||
// #define MXC_CCM_CLPCR_LPM_OFFSET (0)
|
||||
|
||||
// /* Define the bits in register CISR */
|
||||
// #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26)
|
||||
// #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23)
|
||||
// #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22)
|
||||
// #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21)
|
||||
// #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20)
|
||||
// #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19)
|
||||
// #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17)
|
||||
// #define MXC_CCM_CISR_COSC_READY (1 << 6)
|
||||
// #define MXC_CCM_CISR_LRF_PLL (1)
|
||||
|
||||
// /* Define the bits in register CIMR */
|
||||
// #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26)
|
||||
// #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23)
|
||||
// #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22)
|
||||
// #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21)
|
||||
// #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20)
|
||||
// #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 22)
|
||||
// #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17)
|
||||
// #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6)
|
||||
// #define MXC_CCM_CIMR_MASK_LRF_PLL (1)
|
||||
|
||||
// /* Define the bits in register CCOSR */
|
||||
// #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24)
|
||||
// #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
|
||||
// #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21)
|
||||
// #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16)
|
||||
// #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
|
||||
// #define MXC_CCM_CCOSR_CLKO2_CLKO1_SEL (0x1 << 8)
|
||||
// #define MXC_CCM_CCOSR_CKO1_EN (0x1 << 7)
|
||||
// #define MXC_CCM_CCOSR_CKO1_DIV_MASK (0x7 << 4)
|
||||
// #define MXC_CCM_CCOSR_CKO1_DIV_OFFSET (4)
|
||||
// #define MXC_CCM_CCOSR_CKO1_SEL_MASK (0xF)
|
||||
// #define MXC_CCM_CCOSR_CKO1_SEL_OFFSET (0)
|
||||
|
||||
// /* Define the bits in registers CGPR */
|
||||
// #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
|
||||
// #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
|
||||
// #define MXC_CCM_CGPR_PMIC_DELAY_SCALER (1)
|
||||
// /* On SoloLite */
|
||||
// #define MXC_CCM_CGPR_MEM_IPG_STOP_MASK (0x1 << 1)
|
||||
|
||||
// /* Define the bits in registers CCGRx */
|
||||
// #define MXC_CCM_CCGR_CG_MASK 3
|
||||
|
||||
// #define MXC_CCM_CCGR0_CG15_OFFSET 30
|
||||
// #define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30)
|
||||
// #define MXC_CCM_CCGR0_CG14_OFFSET 28
|
||||
// #define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28)
|
||||
// #define MXC_CCM_CCGR0_CG13_OFFSET 26
|
||||
// #define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26)
|
||||
// #define MXC_CCM_CCGR0_CG12_OFFSET 24
|
||||
// #define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24)
|
||||
// #define MXC_CCM_CCGR0_CG11_OFFSET 22
|
||||
// #define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22)
|
||||
// #define MXC_CCM_CCGR0_CG10_OFFSET 20
|
||||
// #define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20)
|
||||
// #define MXC_CCM_CCGR0_CG9_OFFSET 18
|
||||
// #define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18)
|
||||
// #define MXC_CCM_CCGR0_CG8_OFFSET 16
|
||||
// #define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16)
|
||||
// #define MXC_CCM_CCGR0_CG7_OFFSET 14
|
||||
// #define MXC_CCM_CCGR0_CG6_OFFSET 12
|
||||
// #define MXC_CCM_CCGR0_CG5_OFFSET 10
|
||||
// #define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10)
|
||||
// #define MXC_CCM_CCGR0_CG4_OFFSET 8
|
||||
// #define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8)
|
||||
// #define MXC_CCM_CCGR0_CG3_OFFSET 6
|
||||
// #define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6)
|
||||
// #define MXC_CCM_CCGR0_CG2_OFFSET 4
|
||||
// #define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4)
|
||||
// #define MXC_CCM_CCGR0_CG1_OFFSET 2
|
||||
// #define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2)
|
||||
// #define MXC_CCM_CCGR0_CG0_OFFSET 0
|
||||
// #define MXC_CCM_CCGR0_CG0_MASK 3
|
||||
|
||||
// #define MXC_CCM_CCGR1_CG15_OFFSET 30
|
||||
// #define MXC_CCM_CCGR1_CG14_OFFSET 28
|
||||
// #define MXC_CCM_CCGR1_CG13_OFFSET 26
|
||||
// #define MXC_CCM_CCGR1_CG12_OFFSET 24
|
||||
// #define MXC_CCM_CCGR1_CG11_OFFSET 22
|
||||
// #define MXC_CCM_CCGR1_CG10_OFFSET 20
|
||||
// #define MXC_CCM_CCGR1_CG9_OFFSET 18
|
||||
// #define MXC_CCM_CCGR1_CG8_OFFSET 16
|
||||
// #define MXC_CCM_CCGR1_CG7_OFFSET 14
|
||||
// #define MXC_CCM_CCGR1_CG6_OFFSET 12
|
||||
// #define MXC_CCM_CCGR1_CG5_OFFSET 10
|
||||
// #define MXC_CCM_CCGR1_CG4_OFFSET 8
|
||||
// #define MXC_CCM_CCGR1_CG3_OFFSET 6
|
||||
// #define MXC_CCM_CCGR1_CG2_OFFSET 4
|
||||
// #define MXC_CCM_CCGR1_CG1_OFFSET 2
|
||||
// #define MXC_CCM_CCGR1_CG0_OFFSET 0
|
||||
|
||||
// #define MXC_CCM_CCGR2_CG15_OFFSET 30
|
||||
// #define MXC_CCM_CCGR2_CG14_OFFSET 28
|
||||
// #define MXC_CCM_CCGR2_CG13_OFFSET 26
|
||||
// #define MXC_CCM_CCGR2_CG12_OFFSET 24
|
||||
// #define MXC_CCM_CCGR2_CG11_OFFSET 22
|
||||
// #define MXC_CCM_CCGR2_CG10_OFFSET 20
|
||||
// #define MXC_CCM_CCGR2_CG9_OFFSET 18
|
||||
// #define MXC_CCM_CCGR2_CG8_OFFSET 16
|
||||
// #define MXC_CCM_CCGR2_CG7_OFFSET 14
|
||||
// #define MXC_CCM_CCGR2_CG6_OFFSET 12
|
||||
// #define MXC_CCM_CCGR2_CG5_OFFSET 10
|
||||
// #define MXC_CCM_CCGR2_CG4_OFFSET 8
|
||||
// #define MXC_CCM_CCGR2_CG3_OFFSET 6
|
||||
// #define MXC_CCM_CCGR2_CG2_OFFSET 4
|
||||
// #define MXC_CCM_CCGR2_CG1_OFFSET 2
|
||||
// #define MXC_CCM_CCGR2_CG0_OFFSET 0
|
||||
|
||||
// #define MXC_CCM_CCGR3_CG15_OFFSET 30
|
||||
// #define MXC_CCM_CCGR3_CG14_OFFSET 28
|
||||
// #define MXC_CCM_CCGR3_CG13_OFFSET 26
|
||||
// #define MXC_CCM_CCGR3_CG12_OFFSET 24
|
||||
// #define MXC_CCM_CCGR3_CG11_OFFSET 22
|
||||
// #define MXC_CCM_CCGR3_CG10_OFFSET 20
|
||||
// #define MXC_CCM_CCGR3_CG9_OFFSET 18
|
||||
// #define MXC_CCM_CCGR3_CG8_OFFSET 16
|
||||
// #define MXC_CCM_CCGR3_CG7_OFFSET 14
|
||||
// #define MXC_CCM_CCGR3_CG6_OFFSET 12
|
||||
// #define MXC_CCM_CCGR3_CG5_OFFSET 10
|
||||
// #define MXC_CCM_CCGR3_CG4_OFFSET 8
|
||||
// #define MXC_CCM_CCGR3_CG3_OFFSET 6
|
||||
// #define MXC_CCM_CCGR3_CG2_OFFSET 4
|
||||
// #define MXC_CCM_CCGR3_CG1_OFFSET 2
|
||||
// #define MXC_CCM_CCGR3_CG0_OFFSET 0
|
||||
|
||||
// #define MXC_CCM_CCGR4_CG15_OFFSET 30
|
||||
// #define MXC_CCM_CCGR4_CG14_OFFSET 28
|
||||
// #define MXC_CCM_CCGR4_CG13_OFFSET 26
|
||||
// #define MXC_CCM_CCGR4_CG12_OFFSET 24
|
||||
// #define MXC_CCM_CCGR4_CG11_OFFSET 22
|
||||
// #define MXC_CCM_CCGR4_CG10_OFFSET 20
|
||||
// #define MXC_CCM_CCGR4_CG9_OFFSET 18
|
||||
// #define MXC_CCM_CCGR4_CG8_OFFSET 16
|
||||
// #define MXC_CCM_CCGR4_CG7_OFFSET 14
|
||||
// #define MXC_CCM_CCGR4_CG6_OFFSET 12
|
||||
// #define MXC_CCM_CCGR4_CG5_OFFSET 10
|
||||
// #define MXC_CCM_CCGR4_CG4_OFFSET 8
|
||||
// #define MXC_CCM_CCGR4_CG3_OFFSET 6
|
||||
// #define MXC_CCM_CCGR4_CG2_OFFSET 4
|
||||
// #define MXC_CCM_CCGR4_CG1_OFFSET 2
|
||||
// #define MXC_CCM_CCGR4_CG0_OFFSET 0
|
||||
|
||||
// #define MXC_CCM_CCGR5_CG15_OFFSET 30
|
||||
// #define MXC_CCM_CCGR5_CG14_OFFSET 28
|
||||
// #define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28)
|
||||
// #define MXC_CCM_CCGR5_CG13_OFFSET 26
|
||||
// #define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26)
|
||||
// #define MXC_CCM_CCGR5_CG12_OFFSET 24
|
||||
// #define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24)
|
||||
// #define MXC_CCM_CCGR5_CG11_OFFSET 22
|
||||
// #define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22)
|
||||
// #define MXC_CCM_CCGR5_CG10_OFFSET 20
|
||||
// #define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20)
|
||||
// #define MXC_CCM_CCGR5_CG9_OFFSET 18
|
||||
// #define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18)
|
||||
// #define MXC_CCM_CCGR5_CG8_OFFSET 16
|
||||
// #define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16)
|
||||
// #define MXC_CCM_CCGR5_CG7_OFFSET 14
|
||||
// #define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14)
|
||||
// #define MXC_CCM_CCGR5_CG6_OFFSET 12
|
||||
// #define MXC_CCM_CCGR5_CG6_MASK (0x3 << 12)
|
||||
// #define MXC_CCM_CCGR5_CG5_OFFSET 10
|
||||
// #define MXC_CCM_CCGR5_CG4_OFFSET 8
|
||||
// #define MXC_CCM_CCGR5_CG3_OFFSET 6
|
||||
// #define MXC_CCM_CCGR5_CG2_OFFSET 4
|
||||
// #define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4)
|
||||
// #define MXC_CCM_CCGR5_CG1_OFFSET 2
|
||||
// #define MXC_CCM_CCGR5_CG0_OFFSET 0
|
||||
|
||||
// #define MXC_CCM_CCGR6_CG15_OFFSET 30
|
||||
// #define MXC_CCM_CCGR6_CG14_OFFSET 28
|
||||
// #define MXC_CCM_CCGR6_CG14_MASK (0x3 << 28)
|
||||
// #define MXC_CCM_CCGR6_CG13_OFFSET 26
|
||||
// #define MXC_CCM_CCGR6_CG13_MASK (0x3 << 26)
|
||||
// #define MXC_CCM_CCGR6_CG12_OFFSET 24
|
||||
// #define MXC_CCM_CCGR6_CG12_MASK (0x3 << 24)
|
||||
// #define MXC_CCM_CCGR6_CG11_OFFSET 22
|
||||
// #define MXC_CCM_CCGR6_CG11_MASK (0x3 << 22)
|
||||
// #define MXC_CCM_CCGR6_CG10_OFFSET 20
|
||||
// #define MXC_CCM_CCGR6_CG10_MASK (0x3 << 20)
|
||||
// #define MXC_CCM_CCGR6_CG9_OFFSET 18
|
||||
// #define MXC_CCM_CCGR6_CG9_MASK (0x3 << 18)
|
||||
// #define MXC_CCM_CCGR6_CG8_OFFSET 16
|
||||
// #define MXC_CCM_CCGR6_CG8_MASK (0x3 << 16)
|
||||
// #define MXC_CCM_CCGR6_CG7_OFFSET 14
|
||||
// #define MXC_CCM_CCGR6_CG7_MASK (0x3 << 14)
|
||||
// #define MXC_CCM_CCGR6_CG6_OFFSET 12
|
||||
// #define MXC_CCM_CCGR6_CG6_MASK (0x3 << 12)
|
||||
// #define MXC_CCM_CCGR6_CG5_OFFSET 10
|
||||
// #define MXC_CCM_CCGR6_CG4_OFFSET 8
|
||||
// #define MXC_CCM_CCGR6_CG3_OFFSET 6
|
||||
// #define MXC_CCM_CCGR6_CG2_OFFSET 4
|
||||
// #define MXC_CCM_CCGR6_CG2_MASK (0x3 << 4)
|
||||
// #define MXC_CCM_CCGR6_CG1_OFFSET 2
|
||||
// #define MXC_CCM_CCGR6_CG0_OFFSET 0
|
||||
|
||||
// #define MXC_CCM_CCGR7_CG15_OFFSET 30
|
||||
// #define MXC_CCM_CCGR7_CG14_OFFSET 28
|
||||
// #define MXC_CCM_CCGR7_CG14_MASK (0x3 << 28)
|
||||
// #define MXC_CCM_CCGR7_CG13_OFFSET 26
|
||||
// #define MXC_CCM_CCGR7_CG13_MASK (0x3 << 26)
|
||||
// #define MXC_CCM_CCGR7_CG12_OFFSET 24
|
||||
// #define MXC_CCM_CCGR7_CG12_MASK (0x3 << 24)
|
||||
// #define MXC_CCM_CCGR7_CG11_OFFSET 22
|
||||
// #define MXC_CCM_CCGR7_CG11_MASK (0x3 << 22)
|
||||
// #define MXC_CCM_CCGR7_CG10_OFFSET 20
|
||||
// #define MXC_CCM_CCGR7_CG10_MASK (0x3 << 20)
|
||||
// #define MXC_CCM_CCGR7_CG9_OFFSET 18
|
||||
// #define MXC_CCM_CCGR7_CG9_MASK (0x3 << 18)
|
||||
// #define MXC_CCM_CCGR7_CG8_OFFSET 16
|
||||
// #define MXC_CCM_CCGR7_CG8_MASK (0x3 << 16)
|
||||
// #define MXC_CCM_CCGR7_CG7_OFFSET 14
|
||||
// #define MXC_CCM_CCGR7_CG7_MASK (0x3 << 14)
|
||||
// #define MXC_CCM_CCGR7_CG6_OFFSET 12
|
||||
// #define MXC_CCM_CCGR7_CG6_MASK (0x3 << 12)
|
||||
// #define MXC_CCM_CCGR7_CG5_OFFSET 10
|
||||
// #define MXC_CCM_CCGR7_CG4_OFFSET 8
|
||||
// #define MXC_CCM_CCGR7_CG3_OFFSET 6
|
||||
// #define MXC_CCM_CCGR7_CG2_OFFSET 4
|
||||
// #define MXC_CCM_CCGR7_CG2_MASK (0x3 << 4)
|
||||
// #define MXC_CCM_CCGR7_CG1_OFFSET 2
|
||||
// #define MXC_CCM_CCGR7_CG0_OFFSET 0
|
||||
|
||||
#endif /* __ARCH_ARM_MACH_MX6_CRM_REGS_H__ */
|
||||
+59
@@ -0,0 +1,59 @@
|
||||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file imx_uart.h
|
||||
* @brief support imx6q uart function
|
||||
* @version 3.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2023.09.08
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: imx_uart.h
|
||||
Description: imx6q board uart function
|
||||
Others:
|
||||
History:
|
||||
1. Date: 2023-08-28
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. first version
|
||||
*************************************************/
|
||||
|
||||
#ifndef __IMX_UART_H__
|
||||
#define __IMX_UART_H__
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <irq_numbers.h>
|
||||
|
||||
//! @addtogroup diag_uart
|
||||
//! @{
|
||||
// clang-format off
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
// Constants
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
|
||||
/* UART specific defines */
|
||||
#define IMX6Q_UART_INSTANCE HW_UART2
|
||||
#define UART_BAUD_RATE 115200
|
||||
#define IOMUXC_GPR1_OFFSET 0x4
|
||||
|
||||
#define UART_IRQS(x) ((x) == HW_UART1 ? IMX_INT_UART1 : (x) == HW_UART2 ? IMX_INT_UART2 \
|
||||
: (x) == HW_UART3 ? IMX_INT_UART3 \
|
||||
: (x) == HW_UART4 ? IMX_INT_UART4 \
|
||||
: (x) == HW_UART5 ? IMX_INT_UART5 \
|
||||
: 0xFFFFFFFF)
|
||||
|
||||
// clang-format on
|
||||
#endif //__IMX_UART_H__
|
||||
+164
@@ -0,0 +1,164 @@
|
||||
/*
|
||||
* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
|
||||
* <armlinux@phytec.de>
|
||||
*
|
||||
* Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file iomux_v3.h
|
||||
* @brief support imx6q iomux function define, reference from u-boot-2009-08/include/asm-arm/arch-mx6/iomux_v3.h
|
||||
* @version 3.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2023.09.08
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __MACH_IOMUX_V3_H__
|
||||
#define __MACH_IOMUX_V3_H__
|
||||
|
||||
/*
|
||||
* build IOMUX_PAD structure
|
||||
*
|
||||
* This iomux scheme is based around pads, which are the physical balls
|
||||
* on the processor.
|
||||
*
|
||||
* - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
|
||||
* things like driving strength and pullup/pulldown.
|
||||
* - Each pad can have but not necessarily does have an output routing register
|
||||
* (IOMUXC_SW_MUX_CTL_PAD_x).
|
||||
* - Each pad can have but not necessarily does have an input routing register
|
||||
* (IOMUXC_x_SELECT_INPUT)
|
||||
*
|
||||
* The three register sets do not have a fixed offset to each other,
|
||||
* hence we order this table by pad control registers (which all pads
|
||||
* have) and put the optional i/o routing registers into additional
|
||||
* fields.
|
||||
*
|
||||
* The naming convention for the pad modes is MX35_PAD_<padname>__<padmode>
|
||||
* If <padname> or <padmode> refers to a GPIO, it is named
|
||||
* GPIO_<unit>_<num>
|
||||
*
|
||||
* IOMUX/PAD Bit field definitions
|
||||
*
|
||||
* MUX_CTRL_OFS: 0..11 (12)
|
||||
* PAD_CTRL_OFS: 12..23 (12)
|
||||
* SEL_INPUT_OFS: 24..35 (12)
|
||||
* MUX_MODE + SION: 36..40 (5)
|
||||
* PAD_CTRL + NO_PAD_CTRL: 41..59 (19)
|
||||
* SEL_INP: 60..63 (4)
|
||||
*/
|
||||
// clang-format off
|
||||
#include <stdint.h>
|
||||
|
||||
typedef uint64_t iomux_v3_cfg_t;
|
||||
typedef unsigned int iomux_pin_name_t;
|
||||
|
||||
#define MUX_CTRL_OFS_SHIFT 0
|
||||
#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
|
||||
#define MUX_PAD_CTRL_OFS_SHIFT 12
|
||||
#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_PAD_CTRL_OFS_SHIFT)
|
||||
#define MUX_SEL_INPUT_OFS_SHIFT 24
|
||||
#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_SEL_INPUT_OFS_SHIFT)
|
||||
|
||||
#define MUX_MODE_SHIFT 36
|
||||
#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
|
||||
#define MUX_PAD_CTRL_SHIFT 41
|
||||
#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x7ffff << MUX_PAD_CTRL_SHIFT)
|
||||
#define MUX_SEL_INPUT_SHIFT 60
|
||||
#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
|
||||
|
||||
#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
|
||||
|
||||
#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _sel_input_ofs, _sel_input, _pad_ctrl) \
|
||||
(((iomux_v3_cfg_t)(_mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \
|
||||
((iomux_v3_cfg_t)(_mux_mode) << MUX_MODE_SHIFT) | \
|
||||
((iomux_v3_cfg_t)(_pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \
|
||||
((iomux_v3_cfg_t)(_pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \
|
||||
((iomux_v3_cfg_t)(_sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \
|
||||
((iomux_v3_cfg_t)(_sel_input) << MUX_SEL_INPUT_SHIFT))
|
||||
|
||||
#if defined CONFIG_MX6Q
|
||||
#define MX6X_IOMUX(s) MX6Q_##s
|
||||
#elif defined CONFIG_MX6DL
|
||||
#define MX6X_IOMUX(s) MX6DL_##s
|
||||
#elif defined CONFIG_MX6SL
|
||||
#define MX6X_IOMUX(s) MX6SL_##s
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Use to set PAD control
|
||||
*/
|
||||
#define PAD_CTL_LVE_OFFSET (22)
|
||||
#define PAD_CTL_LVE (1 << 18)
|
||||
#define NO_PAD_CTRL (1 << 17)
|
||||
#define PAD_CTL_HYS (1 << 16)
|
||||
|
||||
#define NO_PAD_I 0
|
||||
#define NO_MUX_I 0
|
||||
#define IOMUX_CONFIG_SION (0x1 << 4)
|
||||
|
||||
#define PAD_CTL_PUS_100K_DOWN (0 << 14)
|
||||
#define PAD_CTL_PUS_47K_UP (1 << 14)
|
||||
#define PAD_CTL_PUS_100K_UP (2 << 14)
|
||||
#define PAD_CTL_PUS_22K_UP (3 << 14)
|
||||
|
||||
#define PAD_CTL_PUE (1 << 13)
|
||||
#define PAD_CTL_PKE (1 << 12)
|
||||
#define PAD_CTL_ODE (1 << 11)
|
||||
|
||||
#define PAD_CTL_SPEED_LOW (1 << 6)
|
||||
#define PAD_CTL_SPEED_MED (2 << 6)
|
||||
#define PAD_CTL_SPEED_HIGH (3 << 6)
|
||||
|
||||
#define PAD_CTL_DSE_DISABLE (0 << 3)
|
||||
#define PAD_CTL_DSE_240ohm (1 << 3)
|
||||
#define PAD_CTL_DSE_120ohm (2 << 3)
|
||||
#define PAD_CTL_DSE_80ohm (3 << 3)
|
||||
#define PAD_CTL_DSE_60ohm (4 << 3)
|
||||
#define PAD_CTL_DSE_48ohm (5 << 3)
|
||||
#define PAD_CTL_DSE_40ohm (6 << 3)
|
||||
#define PAD_CTL_DSE_34ohm (7 << 3)
|
||||
|
||||
#define PAD_CTL_SRE_FAST (1 << 0)
|
||||
#define PAD_CTL_SRE_SLOW (0 << 0)
|
||||
|
||||
#define GPIO_PIN_MASK 0x1f
|
||||
|
||||
#define GPIO_PORT_SHIFT 5
|
||||
#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
|
||||
|
||||
#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
|
||||
// clang-format on
|
||||
|
||||
/*
|
||||
* setups a single pad in the iomuxer
|
||||
*/
|
||||
int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
|
||||
|
||||
/*
|
||||
* Initialise the iomux controller
|
||||
*/
|
||||
void mxc_iomux_v3_init(void *iomux_v3_base);
|
||||
|
||||
#endif /* __MACH_IOMUX_V3_H__*/
|
||||
|
||||
+5609
File diff suppressed because it is too large
Load Diff
+3845
File diff suppressed because it is too large
Load Diff
+72
@@ -0,0 +1,72 @@
|
||||
/*
|
||||
* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
|
||||
* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
|
||||
* <armlinux@phytec.de>
|
||||
*
|
||||
* Copyright (C) 2004-2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*/
|
||||
/**
|
||||
* @file iomux_v3.c
|
||||
* @brief support imx6q iomux function, reference from u-boot-2009-08/cpu/arm_cortexa8/mx6/iomux-v3.c
|
||||
* @version 3.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2023.09.08
|
||||
*/
|
||||
|
||||
#include <iomux_v3.h>
|
||||
|
||||
#include <regs_pins.h>
|
||||
#include <soc_memory_map.h>
|
||||
|
||||
#include "mmio_access.h"
|
||||
|
||||
static void* base;
|
||||
|
||||
void mxc_iomux_v3_init(void* iomux_v3_base)
|
||||
{
|
||||
base = iomux_v3_base;
|
||||
}
|
||||
|
||||
/*
|
||||
* configures a single pad in the iomuxer
|
||||
*/
|
||||
int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
|
||||
{
|
||||
uint32_t mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
|
||||
uint32_t mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
|
||||
uint32_t sel_input_ofs = (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
|
||||
uint32_t sel_input = (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
|
||||
uint32_t pad_ctrl_ofs = (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
|
||||
uint32_t pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
|
||||
|
||||
if (mux_ctrl_ofs)
|
||||
mmio_write((uintptr_t)(base + mux_ctrl_ofs), (uintptr_t)(mux_mode));
|
||||
|
||||
if (sel_input_ofs)
|
||||
mmio_write((uintptr_t)(base + sel_input_ofs), (uintptr_t)(sel_input));
|
||||
|
||||
if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs) {
|
||||
if (pad_ctrl & PAD_CTL_LVE) {
|
||||
/* Set the bit for LVE */
|
||||
pad_ctrl |= (1 << PAD_CTL_LVE_OFFSET);
|
||||
pad_ctrl &= ~(PAD_CTL_LVE);
|
||||
}
|
||||
mmio_write((uintptr_t)(base + pad_ctrl_ofs), (uintptr_t)(pad_ctrl));
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
Reference in New Issue
Block a user