xuos/xiuos
2
0
Fork 11
Code Issues Pull Requests 3 Actions Packages Projects Releases Wiki Activity

rename board name 'xidatong' as 'xidatong-arm32'

Browse Source
This commit is contained in:
Wang_Weigen
2022-06-22 15:52:23 +08:00
parent f5f9dbe59d
commit 42cf1290d1
172 changed files with 19 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Ubiquitous/XiZi/board/xidatong-arm32/third_party_driver/wdt/Kconfig
+13
View File
@@ -0,0 +1,13 @@
if BSP_USING_WDT
config WDT_BUS_NAME
string "watchdog bus name"
default "wdt"
config WDT_DRIVER_NAME
string "watchdog driver name"
default "wdt_drv"
config WDT_DEVICE_NAME
string "watchdog device name"
default "wdt_dev"
endif
Ubiquitous/XiZi/board/xidatong-arm32/third_party_driver/wdt/Makefile
+3
View File
@@ -0,0 +1,3 @@
SRC_FILES := connect_wdt.c fsl_wdog.c
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi/board/xidatong-arm32/third_party_driver/wdt/connect_wdt.c
+182
View File
@@ -0,0 +1,182 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_wdt.c
* @brief support imxrt1052-board watchdog(WDG1) function and register to bus framework
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-05-06
*/
#include <connect_wdt.h>
#include <fsl_wdog.h>
static BusType wdt;
static wdog_config_t wdog_config_t_param;
void WDOG1_IRQHandler(void)
{
WDOG_ClearInterruptStatus(WDOG1, kWDOG_InterruptFlag);
/* User code. User can do urgent case before timeout reset.
* IE. user can backup the ram data or ram log to flash.
* the period is set by config.interruptTimeValue, user need to
* check the period between interrupt and timeout.
*/
}
static uint32 Imxrt1052WdgOpen(void *dev)
{
return EOK;
}
static uint32 Imxrt1052WdgClose(void *dev)
{
WDOG_Deinit(WDOG1);
return EOK;
}
static int Imxrt1052WdgInit(struct WdtHardwareDevice *dev, uint16_t timeout)
{
/*
* wdogConfig->enableWdog = true;
* wdogConfig->workMode.enableWait = true;
* wdogConfig->workMode.enableStop = false;
* wdogConfig->workMode.enableDebug = false;
* wdogConfig->enableInterrupt = false;
* wdogConfig->enablePowerdown = false;
* wdogConfig->resetExtension = flase;
* wdogConfig->timeoutValue = 0xFFU;
* wdogConfig->interruptTimeValue = 0x04u;
*/
WDOG_GetDefaultConfig(&wdog_config_t_param);
wdog_config_t_param.timeoutValue = timeout; /* Timeout value is 1 sec / 6.4 num, 5s means 32. */
WDOG_Init(WDOG1, &wdog_config_t_param);
return EOK;
}
static uint32 Imxrt1052WdgConfigure(void *drv, struct BusConfigureInfo *args)
{
struct WdtDriver *wdt_drv = (struct WdtDriver *)drv;
struct WdtHardwareDevice *wdt_dev = (struct WdtHardwareDevice *)wdt_drv->driver.owner_bus->owner_haldev;
uint16_t timeout;
switch(args->configure_cmd)
{
case OPER_WDT_SET_TIMEOUT:
timeout = *(uint16_t *)(args->private_data);
if (timeout) {
Imxrt1052WdgInit(wdt_dev, timeout);
}
break;
case OPER_WDT_KEEPALIVE:
WDOG_Refresh(WDOG1);
break;
default:
return ERROR;
}
return EOK;
}
static const struct WdtDevDone dev_done =
{
Imxrt1052WdgOpen,
Imxrt1052WdgClose,
NONE,
NONE,
};
/**
* @description: Feed watchdog task function
*/
static void FeedWatchdogTask(void)
{
while (1)
{
/* keep watchdog alive in idle task */
struct BusConfigureInfo cfg;
cfg.configure_cmd = OPER_WDT_KEEPALIVE;
cfg.private_data = NONE;
BusDrvConfigure(wdt->owner_driver, &cfg);
MdelayKTask(500);
}
}
/**
* @description: Watchdog function
* @return success: EOK, failure: other
*/
int StartWatchdog(void)
{
int ret = EOK;
uint16_t timeout = 32; /* timeout time 5s*/
wdt = BusFind(WDT_BUS_NAME);
wdt->owner_driver = BusFindDriver(wdt, WDT_DRIVER_NAME);
/* set watchdog timeout time */
struct BusConfigureInfo cfg;
cfg.configure_cmd = OPER_WDT_SET_TIMEOUT;
cfg.private_data = &timeout;
ret = BusDrvConfigure(wdt->owner_driver, &cfg);
int32 WdtTask = KTaskCreate("WdtTask", (void *)FeedWatchdogTask, NONE, 1024, 20);
StartupKTask(WdtTask);
return EOK;
}
int Imxrt1052HwWdgInit(void)
{
x_err_t ret = EOK;
static struct WdtBus watch_dog_timer_bus;
static struct WdtDriver watch_dog_timer_drv;
static struct WdtHardwareDevice watch_dog_timer_dev;
ret = WdtBusInit(&watch_dog_timer_bus, WDT_BUS_NAME);
if (ret != EOK) {
KPrintf("Watchdog bus init error %d\n", ret);
return ERROR;
}
watch_dog_timer_drv.configure = Imxrt1052WdgConfigure;
ret = WdtDriverInit(&watch_dog_timer_drv, WDT_DRIVER_NAME);
if (ret != EOK) {
KPrintf("Watchdog driver init error %d\n", ret);
return ERROR;
}
ret = WdtDriverAttachToBus(WDT_DRIVER_NAME, WDT_BUS_NAME);
if (ret != EOK) {
KPrintf("Watchdog driver attach error %d\n", ret);
return ERROR;
}
watch_dog_timer_dev.dev_done = &dev_done;
ret = WdtDeviceRegister(&watch_dog_timer_dev, WDT_DEVICE_NAME);
if (ret != EOK) {
KPrintf("Watchdog device register error %d\n", ret);
return ERROR;
}
ret = WdtDeviceAttachToBus(WDT_DEVICE_NAME, WDT_BUS_NAME);
if (ret != EOK) {
KPrintf("Watchdog device register error %d\n", ret);
return ERROR;
}
return ret;
}
Ubiquitous/XiZi/board/xidatong-arm32/third_party_driver/wdt/fsl_wdog.c
+206
View File
@@ -0,0 +1,206 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_wdog.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.wdog01"
#endif
/*******************************************************************************
* Variables
******************************************************************************/
static WDOG_Type *const s_wdogBases[] = WDOG_BASE_PTRS;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Array of WDOG clock name. */
static const clock_ip_name_t s_wdogClock[] = WDOG_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
static const IRQn_Type s_wdogIRQ[] = WDOG_IRQS;
/*******************************************************************************
* Code
******************************************************************************/
static uint32_t WDOG_GetInstance(WDOG_Type *base)
{
uint32_t instance;
/* Find the instance index from base address mappings. */
for (instance = 0; instance < ARRAY_SIZE(s_wdogBases); instance++)
{
if (s_wdogBases[instance] == base)
{
break;
}
}
assert(instance < ARRAY_SIZE(s_wdogBases));
return instance;
}
/*!
* brief Initializes the WDOG configuration structure.
*
* This function initializes the WDOG configuration structure to default values. The default
* values are as follows.
* code
* wdogConfig->enableWdog = true;
* wdogConfig->workMode.enableWait = true;
* wdogConfig->workMode.enableStop = false;
* wdogConfig->workMode.enableDebug = false;
* wdogConfig->enableInterrupt = false;
* wdogConfig->enablePowerdown = false;
* wdogConfig->resetExtension = flase;
* wdogConfig->timeoutValue = 0xFFU;
* wdogConfig->interruptTimeValue = 0x04u;
* endcode
*
* param config Pointer to the WDOG configuration structure.
* see wdog_config_t
*/
void WDOG_GetDefaultConfig(wdog_config_t *config)
{
assert(config);
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->enableWdog = true;
config->workMode.enableWait = false;
config->workMode.enableStop = false;
config->workMode.enableDebug = false;
config->enableInterrupt = false;
config->softwareResetExtension = false;
config->enablePowerDown = false;
config->timeoutValue = 0xffu;
config->interruptTimeValue = 0x04u;
config->enableTimeOutAssert = false;
}
/*!
* brief Initializes the WDOG.
*
* This function initializes the WDOG. When called, the WDOG runs according to the configuration.
*
* This is an example.
* code
* wdog_config_t config;
* WDOG_GetDefaultConfig(&config);
* config.timeoutValue = 0xffU;
* config->interruptTimeValue = 0x04u;
* WDOG_Init(wdog_base,&config);
* endcode
*
* param base WDOG peripheral base address
* param config The configuration of WDOG
*/
void WDOG_Init(WDOG_Type *base, const wdog_config_t *config)
{
assert(config);
uint16_t value = 0u;
value = WDOG_WCR_WDE(config->enableWdog) | WDOG_WCR_WDW(config->workMode.enableWait) |
WDOG_WCR_WDZST(config->workMode.enableStop) | WDOG_WCR_WDBG(config->workMode.enableDebug) |
WDOG_WCR_SRE(config->softwareResetExtension) | WDOG_WCR_WT(config->timeoutValue) |
WDOG_WCR_WDT(config->enableTimeOutAssert) | WDOG_WCR_SRS_MASK | WDOG_WCR_WDA_MASK;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Set configuration */
CLOCK_EnableClock(s_wdogClock[WDOG_GetInstance(base)]);
#endif
base->WICR = WDOG_WICR_WICT(config->interruptTimeValue) | WDOG_WICR_WIE(config->enableInterrupt);
base->WMCR = WDOG_WMCR_PDE(config->enablePowerDown);
base->WCR = value;
if (config->enableInterrupt)
{
EnableIRQ(s_wdogIRQ[WDOG_GetInstance(base)]);
}
}
/*!
* brief Shuts down the WDOG.
*
* This function shuts down the WDOG.
* Watchdog Enable bit is a write one once only bit. It is not
* possible to clear this bit by a software write, once the bit is set.
* This bit(WDE) can be set/reset only in debug mode(exception).
*/
void WDOG_Deinit(WDOG_Type *base)
{
if (base->WCR & WDOG_WCR_WDBG_MASK)
{
WDOG_Disable(base);
}
}
/*!
* brief Gets the WDOG all reset status flags.
*
* This function gets all reset status flags.
*
* code
* uint16_t status;
* status = WDOG_GetStatusFlags (wdog_base);
* endcode
* param base WDOG peripheral base address
* return State of the status flag: asserted (true) or not-asserted (false).see _wdog_status_flags
* - true: a related status flag has been set.
* - false: a related status flag is not set.
*/
uint16_t WDOG_GetStatusFlags(WDOG_Type *base)
{
uint16_t status_flag = 0U;
status_flag |= (base->WCR & WDOG_WCR_WDE_MASK);
status_flag |= (base->WRSR & WDOG_WRSR_POR_MASK);
status_flag |= (base->WRSR & WDOG_WRSR_TOUT_MASK);
status_flag |= (base->WRSR & WDOG_WRSR_SFTW_MASK);
status_flag |= (base->WICR & WDOG_WICR_WTIS_MASK);
return status_flag;
}
/*!
* brief Clears the WDOG flag.
*
* This function clears the WDOG status flag.
*
* This is an example for clearing the interrupt flag.
* code
* WDOG_ClearStatusFlags(wdog_base,KWDOG_InterruptFlag);
* endcode
* param base WDOG peripheral base address
* param mask The status flags to clear.
* The parameter could be any combination of the following values.
* kWDOG_TimeoutFlag
*/
void WDOG_ClearInterruptStatus(WDOG_Type *base, uint16_t mask)
{
if (mask & kWDOG_InterruptFlag)
{
base->WICR |= WDOG_WICR_WTIS_MASK;
}
}
/*!
* brief Refreshes the WDOG timer.
*
* This function feeds the WDOG.
* This function should be called before the WDOG timer is in timeout. Otherwise, a reset is asserted.
*
* param base WDOG peripheral base address
*/
void WDOG_Refresh(WDOG_Type *base)
{
base->WSR = WDOG_REFRESH_KEY & 0xFFFFU;
base->WSR = (WDOG_REFRESH_KEY >> 16U) & 0xFFFFU;
}