Merge branch 'rk3568_dev' of https://gitlink.org.cn/tuyuyang/xiuos into rk3568_dev
This commit is contained in:
lr
@@ -0,0 +1,105 @@
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/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
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*/
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/** @addtogroup RK_HAL_Driver
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* @{
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*/
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/** @addtogroup HAL_BASE
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* @{
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*/
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#ifndef _HAL_BASE_H_
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#define _HAL_BASE_H_
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#include "hal_conf.h"
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#include "hal_driver.h"
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#include "hal_debug.h"
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/***************************** MACRO Definition ******************************/
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/** @defgroup HAL_BASE_Exported_Definition_Group1 Basic Definition
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* @{
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*/
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/** enter markrom usb upgrade */
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#define SYS_UPGRADE_FLAG (0xEF08A53C)
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/** enter loader usb upgrade */
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#define LDR_UPGRADE_FLAG (0x5242C301)
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#define IS_TICKFREQ(f) (((f) == HAL_TICK_FREQ_1KHZ) || ((f) == HAL_TICK_FREQ_100HZ) || ((f) == HAL_TICK_FREQ_10HZ))
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/***************************** Structure Definition **************************/
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typedef enum {
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HAL_TICK_FREQ_10HZ = 100U, /**< 10 ticks per second, so it's 100ms/tick */
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HAL_TICK_FREQ_100HZ = 10U, /**< 100 ticks per second, so it's 10ms/tick */
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HAL_TICK_FREQ_1KHZ = 1U, /**< 1000 ticks per second, so it's 1ms/tick */
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HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
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} eHAL_tickFreq;
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/** @} */
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/***************************** Function Declare ******************************/
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/** @defgroup HAL_BASE_Public_Function_Declare Public Function Declare
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* @{
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*/
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HAL_Status HAL_Init(void);
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HAL_Status HAL_DeInit(void);
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HAL_Status HAL_InitTick(uint32_t tickPriority);
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HAL_Status HAL_IncTick(void);
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uint32_t HAL_GetTick(void);
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HAL_Status HAL_SetTickFreq(eHAL_tickFreq freq);
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eHAL_tickFreq HAL_GetTickFreq(void);
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HAL_Status HAL_DelayUs(uint32_t us);
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HAL_Status HAL_DelayMs(uint32_t ms);
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HAL_Status HAL_CPUDelayUs(uint32_t us);
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HAL_Status HAL_SystemCoreClockUpdate(uint32_t hz, eHAL_systickClkSource clkSource);
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uint64_t HAL_DivU64Rem(uint64_t numerator, uint32_t denominator, uint32_t *pRemainder);
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uint64_t HAL_GetSysTimerCount(void);
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void HAL_CPU_EnterIdle(void);
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#if defined(HAL_CPU_USAGE_ENABLED)
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uint32_t HAL_GetCPUUsage(void);
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#endif
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/** @} */
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/********************* Public Function Definition ***************************/
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/** @defgroup HAL_BASE_Exported_Functions_Group5 Other Functions
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* @{
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*/
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/**
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* @brief uint64_t numerator / uint32_t denominator
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* @param numerator
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* @param denominator
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* @return uint64_t result
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*/
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static inline uint64_t HAL_DivU64(uint64_t numerator, uint32_t denominator)
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{
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return HAL_DivU64Rem(numerator, denominator, NULL);
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}
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/**
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* @brief uint32_t numerator / uint32_t denominator rounded to nearest integer
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* @param numerator
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* @param denominator
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* @return uint32_t result rounded to nearest integer
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*/
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static inline uint32_t HAL_DivRoundClosest(uint32_t numerator, uint32_t denominator)
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{
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return (numerator + (denominator / 2)) / denominator;
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}
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/** @} */
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#endif
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/** @} */
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/** @} */
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@@ -0,0 +1,75 @@
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/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*/
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#ifndef __BSP_H__
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#define __BSP_H__
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#include "hal_base.h"
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/***************************** MACRO Definition ******************************/
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/***************************** Structure Definition **************************/
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#ifdef HAL_PL330_MODULE_ENABLED
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extern struct HAL_PL330_DEV g_pl330Dev0;
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extern struct HAL_PL330_DEV g_pl330Dev1;
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#endif
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#ifdef HAL_SPI_MODULE_ENABLED
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extern const struct HAL_SPI_DEV g_spi0Dev;
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extern const struct HAL_SPI_DEV g_spi1Dev;
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extern const struct HAL_SPI_DEV g_spi2Dev;
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extern const struct HAL_SPI_DEV g_spi3Dev;
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#endif
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#ifdef HAL_UART_MODULE_ENABLED
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extern const struct HAL_UART_DEV g_uart0Dev;
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extern const struct HAL_UART_DEV g_uart1Dev;
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extern const struct HAL_UART_DEV g_uart2Dev;
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extern const struct HAL_UART_DEV g_uart3Dev;
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extern const struct HAL_UART_DEV g_uart4Dev;
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extern const struct HAL_UART_DEV g_uart5Dev;
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extern const struct HAL_UART_DEV g_uart6Dev;
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extern const struct HAL_UART_DEV g_uart7Dev;
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extern const struct HAL_UART_DEV g_uart8Dev;
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extern const struct HAL_UART_DEV g_uart9Dev;
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#endif
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#ifdef HAL_I2C_MODULE_ENABLED
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extern const struct HAL_I2C_DEV g_i2c0Dev;
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extern const struct HAL_I2C_DEV g_i2c1Dev;
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extern const struct HAL_I2C_DEV g_i2c2Dev;
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extern const struct HAL_I2C_DEV g_i2c3Dev;
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extern const struct HAL_I2C_DEV g_i2c4Dev;
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extern const struct HAL_I2C_DEV g_i2c5Dev;
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#endif
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#ifdef HAL_FSPI_MODULE_ENABLED
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extern struct HAL_FSPI_HOST g_fspi0Dev;
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#endif
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#ifdef HAL_CANFD_MODULE_ENABLED
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extern const struct HAL_CANFD_DEV g_can0Dev;
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extern const struct HAL_CANFD_DEV g_can1Dev;
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extern const struct HAL_CANFD_DEV g_can2Dev;
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#endif
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#ifdef HAL_GMAC_MODULE_ENABLED
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extern const struct HAL_GMAC_DEV g_gmac0Dev;
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extern const struct HAL_GMAC_DEV g_gmac1Dev;
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#endif
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#ifdef HAL_PCIE_MODULE_ENABLED
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extern struct HAL_PCIE_DEV g_pcieDev;
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#endif
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#ifdef HAL_PWM_MODULE_ENABLED
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extern const struct HAL_PWM_DEV g_pwm0Dev;
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extern const struct HAL_PWM_DEV g_pwm1Dev;
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extern const struct HAL_PWM_DEV g_pwm2Dev;
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extern const struct HAL_PWM_DEV g_pwm3Dev;
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#endif
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/***************************** Function Declare ******************************/
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void BSP_Init(void);
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#endif
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@@ -0,0 +1,71 @@
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/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
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*/
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#ifndef _HAL_CONF_H_
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#define _HAL_CONF_H_
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/* HAL CPU config */
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#define SOC_RK3568
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#define HAL_AP_CORE
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#define SYS_TIMER TIMER5 /* System timer designation (RK TIMER) */
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/* HAL Driver Config */
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// #define HAL_CACHE_ECC_MODULE_ENABLED
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// #define HAL_CPU_TOPOLOGY_MODULE_ENABLED
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#define HAL_CRU_MODULE_ENABLED
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// #define HAL_DCACHE_MODULE_ENABLED
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// #define HAL_DDR_ECC_MODULE_ENABLED
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// #define HAL_FSPI_MODULE_ENABLED
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// #define HAL_GIC_MODULE_ENABLED
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#define HAL_GMAC_MODULE_ENABLED
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#define HAL_GPIO_MODULE_ENABLED
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// #define HAL_GPIO_IRQ_GROUP_MODULE_ENABLED
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// #define HAL_SPINLOCK_MODULE_ENABLED
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// #define HAL_HWSPINLOCK_MODULE_ENABLED
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// #define HAL_I2C_MODULE_ENABLED
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// #define HAL_IRQ_HANDLER_MODULE_ENABLED
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// #define HAL_MBOX_MODULE_ENABLED
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// #define HAL_PCIE_MODULE_ENABLED
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#define HAL_PINCTRL_MODULE_ENABLED
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// #define HAL_PL330_MODULE_ENABLED
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// #define HAL_PWM_MODULE_ENABLED
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// #define HAL_SARADC_MODULE_ENABLED
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// #define HAL_SMCCC_MODULE_ENABLED
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// #define HAL_SNOR_MODULE_ENABLED
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// #define HAL_SPI_MODULE_ENABLED
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#define HAL_TIMER_MODULE_ENABLED
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// #define HAL_TSADC_MODULE_ENABLED
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// #define HAL_UART_MODULE_ENABLED
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// #define HAL_WDT_MODULE_ENABLED
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// #define HAL_CANFD_MODULE_ENABLED
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/* HAL_DBG SUB CONFIG */
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#define HAL_DBG_USING_LIBC_PRINTF
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#define HAL_DBG_ON
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#define HAL_DBG_INFO_ON
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#define HAL_DBG_WRN_ON
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#define HAL_DBG_ERR_ON
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#define HAL_ASSERT_ON
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#ifdef HAL_SNOR_MODULE_ENABLED
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#define HAL_SNOR_FSPI_HOST
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#endif
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#ifdef HAL_GIC_MODULE_ENABLED
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#define HAL_GIC_AMP_FEATURE_ENABLED
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#define HAL_GIC_PREEMPT_FEATURE_ENABLED
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//#define HAL_GIC_WAIT_LINUX_INIT_ENABLED
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#endif
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#ifdef HAL_GPIO_MODULE_ENABLED
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#define HAL_GPIO_IRQ_DISPATCH_FEATURE_ENABLED
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#endif
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#ifdef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED
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#define HAL_GPIO_IRQ_GROUP_PRIO_LEVEL_MAX (3)
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#endif
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#endif
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@@ -0,0 +1,477 @@
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/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
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*/
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#include "hal_conf.h"
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#ifdef HAL_CRU_MODULE_ENABLED
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/** @addtogroup RK_HAL_Driver
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* @{
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*/
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/** @addtogroup CRU
|
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* @{
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*/
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#ifndef _HAL_CRU_H_
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#define _HAL_CRU_H_
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#include "hal_def.h"
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/*************************** MACRO Definition ****************************/
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/** @defgroup CRU_Exported_Definition_Group1 Basic Definition
|
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* @{
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*/
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#ifdef HAL_CRU_DBG_ON
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#define HAL_CRU_DBG(fmt, arg...) HAL_SYSLOG("[HAL CRU] " fmt, ##arg)
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#else
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#define HAL_CRU_DBG(fmt, arg...) do { if (0) HAL_SYSLOG("[HAL CRU] " fmt, ##arg); } while (0)
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#endif
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#define MHZ 1000000
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#define KHZ 1000
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#ifndef PLL_INPUT_OSC_RATE
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#define PLL_INPUT_OSC_RATE (24 * MHZ)
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#endif
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#define GENVAL_D16(x, h, l) ((uint32_t)(((x) & HAL_GENMASK(h, l)) / 16))
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#define GENVAL_D16_REM(x, h, l) ((uint32_t)(((x) & HAL_GENMASK(h, l)) % 16))
|
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#define WIDTH_TO_MASK(w) ((1 << (w)) - 1)
|
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|
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/*
|
||||
* RESET/GATE fields:
|
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* [31:16]: reserved
|
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* [15:12]: bank
|
||||
* [11:0]: id
|
||||
*/
|
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#define CLK_RESET_GET_REG_OFFSET(x) GENVAL_D16(x, 11, 0)
|
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#define CLK_RESET_GET_BITS_SHIFT(x) GENVAL_D16_REM(x, 11, 0)
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#define CLK_RESET_GET_REG_BANK(x) HAL_GENVAL(x, 15, 12)
|
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|
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#define CLK_GATE_GET_REG_OFFSET(x) CLK_RESET_GET_REG_OFFSET(x)
|
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#define CLK_GATE_GET_BITS_SHIFT(x) CLK_RESET_GET_BITS_SHIFT(x)
|
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#define CLK_GATE_GET_REG_BANK(x) CLK_RESET_GET_REG_BANK(x)
|
||||
|
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/*
|
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* MUX/DIV fields:
|
||||
* [31:24]: width
|
||||
* [23:16]: shift
|
||||
* [15:12]: reserved
|
||||
* [11:8]: bank
|
||||
* [7:0]: reg
|
||||
*/
|
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#define CLK_MUX_GET_REG_OFFSET(x) HAL_GENVAL(x, 7, 0)
|
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#define CLK_MUX_GET_BANK(x) HAL_GENVAL(x, 11, 8)
|
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#define CLK_MUX_GET_BITS_SHIFT(x) HAL_GENVAL(x, 23, 16)
|
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#define CLK_MUX_GET_WIDTH(x) HAL_GENVAL(x, 31, 24)
|
||||
#define CLK_MUX_GET_MASK(x) (WIDTH_TO_MASK(CLK_MUX_GET_WIDTH(x)) << CLK_MUX_GET_BITS_SHIFT(x))
|
||||
|
||||
#define CLK_DIV_GET_REG_OFFSET(x) CLK_MUX_GET_REG_OFFSET(x)
|
||||
#define CLK_DIV_GET_BANK(x) CLK_MUX_GET_BANK(x)
|
||||
#define CLK_DIV_GET_BITS_SHIFT(x) CLK_MUX_GET_BITS_SHIFT(x)
|
||||
#define CLK_DIV_GET_WIDTH(x) CLK_MUX_GET_WIDTH(x)
|
||||
#define CLK_DIV_GET_MASK(x) CLK_MUX_GET_MASK(x)
|
||||
#define CLK_DIV_GET_MAXDIV(x) ((1 << CLK_DIV_GET_WIDTH(x)) - 1)
|
||||
|
||||
/*
|
||||
* v64 mux = v32 | bank(in bit[35:32])
|
||||
* v64 div = v32 | bank(in bit[39:36])
|
||||
*/
|
||||
#ifdef CRU_CLK_USE_CON_BANK
|
||||
#define CLK_GET_MUX(v64) ((uint32_t)(((v64) & 0xFFFFFFFF00000000) >> 32))
|
||||
#define CLK_GET_DIV(v64) ((uint32_t)((v64) & 0x00000000FFFFFFFF))
|
||||
#else
|
||||
#define CLK_GET_MUX(v32) ((uint32_t)((v32) & 0x0F0F00FFU))
|
||||
#define CLK_GET_DIV(v32) ((uint32_t)((((v32) & 0x0000FF00U) >> 8) | \
|
||||
(((v32) & 0xF0F00000U) >> 4)))
|
||||
#endif
|
||||
|
||||
#define RK_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, \
|
||||
_frac) \
|
||||
{ \
|
||||
.rate = _rate##U, .fbDiv = _fbdiv, .postDiv1 = _postdiv1, \
|
||||
.refDiv = _refdiv, .postDiv2 = _postdiv2, .dsmpd = _dsmpd, \
|
||||
.frac = _frac, \
|
||||
}
|
||||
|
||||
#define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \
|
||||
{ \
|
||||
.rate = _rate##U, .p = _p, .m = _m, \
|
||||
.s = _s, .k = _k, \
|
||||
}
|
||||
|
||||
#define CRU_BANK_CFG_FLAGS(reg, sel, gate, soft) \
|
||||
{ \
|
||||
.cruBase = reg, \
|
||||
.selOffset = sel, \
|
||||
.gateOffset = gate, \
|
||||
.softOffset = soft, \
|
||||
}
|
||||
|
||||
struct PLL_CONFIG {
|
||||
uint32_t rate;
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t fbDiv;
|
||||
uint32_t postDiv1;
|
||||
uint32_t refDiv;
|
||||
uint32_t postDiv2;
|
||||
uint32_t dsmpd;
|
||||
uint32_t frac;
|
||||
};
|
||||
struct {
|
||||
uint32_t m;
|
||||
uint32_t p;
|
||||
uint32_t s;
|
||||
uint32_t k;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
struct PLL_SETUP {
|
||||
__IO uint32_t *conOffset0;
|
||||
__IO uint32_t *conOffset1;
|
||||
__IO uint32_t *conOffset2;
|
||||
__IO uint32_t *conOffset3;
|
||||
__IO uint32_t *conOffset6;
|
||||
__IO uint32_t *modeOffset;
|
||||
__I uint32_t *stat0;
|
||||
uint32_t modeShift;
|
||||
uint32_t lockShift;
|
||||
uint32_t modeMask;
|
||||
const struct PLL_CONFIG *rateTable;
|
||||
};
|
||||
|
||||
typedef enum {
|
||||
GLB_SRST_FST = 0xfdb9,
|
||||
GLB_SRST_SND = 0xeca8,
|
||||
} eCRU_GlbSrstType;
|
||||
|
||||
typedef enum {
|
||||
GLB_RST_FST_WDT0 = 0U,
|
||||
GLB_RST_SND_WDT0,
|
||||
GLB_RST_FST_WDT1,
|
||||
GLB_RST_SND_WDT1,
|
||||
GLB_RST_FST_WDT2,
|
||||
GLB_RST_SND_WDT2,
|
||||
} eCRU_WdtRstType;
|
||||
|
||||
struct CRU_BANK_INFO {
|
||||
uint32_t cruBase;
|
||||
uint32_t selOffset;
|
||||
uint32_t gateOffset;
|
||||
uint32_t softOffset;
|
||||
};
|
||||
|
||||
struct HAL_CRU_DEV {
|
||||
const struct CRU_BANK_INFO *banks;
|
||||
uint8_t banksNum;
|
||||
};
|
||||
|
||||
extern const struct HAL_CRU_DEV g_cruDev;
|
||||
|
||||
/***************************** Structure Definition **************************/
|
||||
|
||||
/** @} */
|
||||
/***************************** Function Declare ******************************/
|
||||
/** @defgroup CRU_Private_Function_Declare Private Function Declare
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define _MHZ(n) ((n) * 1000000)
|
||||
#define DIV_NO_REM(pFreq, freq, maxDiv) \
|
||||
((!((pFreq) % (freq))) && ((pFreq) / (freq) <= (maxDiv)))
|
||||
|
||||
int HAL_CRU_FreqGetMux4(uint32_t freq, uint32_t freq0, uint32_t freq1,
|
||||
uint32_t freq2, uint32_t freq3);
|
||||
int HAL_CRU_FreqGetMux3(uint32_t freq, uint32_t freq0, uint32_t freq1,
|
||||
uint32_t freq2);
|
||||
int HAL_CRU_FreqGetMux2(uint32_t freq, uint32_t freq0, uint32_t freq1);
|
||||
|
||||
uint32_t HAL_CRU_MuxGetFreq4(uint32_t muxName, uint32_t freq0, uint32_t freq1,
|
||||
uint32_t freq2, uint32_t freq3);
|
||||
uint32_t HAL_CRU_MuxGetFreq3(uint32_t muxName, uint32_t freq0, uint32_t freq1,
|
||||
uint32_t freq2);
|
||||
uint32_t HAL_CRU_MuxGetFreq2(uint32_t muxName, uint32_t freq0, uint32_t freq1);
|
||||
|
||||
int HAL_CRU_RoundFreqGetMux4(uint32_t freq, uint32_t pFreq0, uint32_t pFreq1,
|
||||
uint32_t pFreq2, uint32_t pFreq3, uint32_t *pFreqOut);
|
||||
int HAL_CRU_RoundFreqGetMux3(uint32_t freq, uint32_t pFreq0, uint32_t pFreq1,
|
||||
uint32_t pFreq2, uint32_t *pFreqOut);
|
||||
int HAL_CRU_RoundFreqGetMux2(uint32_t freq, uint32_t pFreq0, uint32_t pFreq1,
|
||||
uint32_t *pFreqOut);
|
||||
|
||||
/** @} */
|
||||
|
||||
/** @defgroup CRU_Public_Function_Declare Public Function Declare
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get pll freq.
|
||||
* @param pSetup: Contains PLL register parameters
|
||||
* @return pll rate.
|
||||
*/
|
||||
uint32_t HAL_CRU_GetPllFreq(struct PLL_SETUP *pSetup);
|
||||
|
||||
/**
|
||||
* @brief Set pll freq.
|
||||
* @param pSetup: Contains PLL register parameters
|
||||
* @param rate: pll set
|
||||
* @return HAL_Status.
|
||||
*/
|
||||
HAL_Status HAL_CRU_SetPllFreq(struct PLL_SETUP *pSetup, uint32_t rate);
|
||||
|
||||
/**
|
||||
* @brief Set pll power up.
|
||||
* @param pSetup: Contains PLL register parameters
|
||||
* @return HAL_Status.
|
||||
*/
|
||||
HAL_Status HAL_CRU_SetPllPowerUp(struct PLL_SETUP *pSetup);
|
||||
|
||||
/**
|
||||
* @brief Set pll power down.
|
||||
* @param pSetup: Contains PLL register parameters
|
||||
* @return HAL_Status.
|
||||
*/
|
||||
HAL_Status HAL_CRU_SetPllPowerDown(struct PLL_SETUP *pSetup);
|
||||
|
||||
/**
|
||||
* @brief Check if clk is enabled
|
||||
* @param clk: clock to check
|
||||
* @return HAL_Check.
|
||||
*/
|
||||
HAL_Check HAL_CRU_ClkIsEnabled(uint32_t clk);
|
||||
|
||||
/**
|
||||
* @brief Enable clk
|
||||
* @param clk: clock to set
|
||||
* @return HAL_Status.
|
||||
*/
|
||||
HAL_Status HAL_CRU_ClkEnable(uint32_t clk);
|
||||
|
||||
/**
|
||||
* @brief Disable unused clk
|
||||
* @param bank: cru bank id
|
||||
* @param index: gate con offset
|
||||
* @param val: gate value
|
||||
* @return HAL_Status.
|
||||
*/
|
||||
HAL_Status HAL_CRU_ClkDisableUnused(uint32_t bank, uint32_t index, uint32_t val);
|
||||
|
||||
/**
|
||||
* @brief Disable clk
|
||||
* @param clk: clock to set
|
||||
* @return HAL_Status.
|
||||
*/
|
||||
HAL_Status HAL_CRU_ClkDisable(uint32_t clk);
|
||||
|
||||
/**
|
||||
* @brief Check if clk is reset
|
||||
* @param clk: clock to check
|
||||
* @return HAL_Check.
|
||||
*/
|
||||
HAL_Check HAL_CRU_ClkIsReset(uint32_t clk);
|
||||
|
||||
/**
|
||||
* @brief Assert the reset to the clk
|
||||
* @param clk: clock to assert
|
||||
* @return HAL_Status.
|
||||
*/
|
||||
HAL_Status HAL_CRU_ClkResetAssert(uint32_t clk);
|
||||
|
||||
/**
|
||||
* @brief Deassert the reset to the clk
|
||||
* @param clk: clock to deassert
|
||||
* @return HAL_Status.
|
||||
*/
|
||||
HAL_Status HAL_CRU_ClkResetDeassert(uint32_t clk);
|
||||
|
||||
/**
|
||||
* @brief Sync Assert the resets to the clk
|
||||
* @param numClks: num clocks to assert
|
||||
* @param clks: clocks to assert
|
||||
* @return HAL_Status.
|
||||
*/
|
||||
HAL_Status HAL_CRU_ClkResetSyncAssert(int numClks, uint32_t *clks);
|
||||
|
||||
/**
|
||||
* @brief Sync Deassert the resets to the clk
|
||||
* @param numClks: num clocks to assert
|
||||
* @param clks: clocks to deassert
|
||||
* @return HAL_Status.
|
||||
*/
|
||||
HAL_Status HAL_CRU_ClkResetSyncDeassert(int numClks, uint32_t *clks);
|
||||
|
||||
/**
|
||||
* @brief Set frac div
|
||||
* @param fracDivName: frac div id(Contains div offset, shift, mask information)
|
||||
* @param numerator: the numerator to set.
|
||||
* @param denominator: the denominator to set.
|
||||
* @return HAL_Status
|
||||
*/
|
||||
HAL_Status HAL_CRU_ClkSetFracDiv(uint32_t fracDivName,
|
||||
uint32_t numerator,
|
||||
uint32_t denominator);
|
||||
|
||||
/**
|
||||
* @brief Get frac div
|
||||
* @param fracDivName: frac div id(Contains div offset, shift, mask information)
|
||||
* @param numerator: the returned numerator.
|
||||
* @param denominator: the returned denominator.
|
||||
* @return HAL_Status
|
||||
*/
|
||||
HAL_Status HAL_CRU_ClkGetFracDiv(uint32_t fracDivName,
|
||||
uint32_t *numerator,
|
||||
uint32_t *denominator);
|
||||
|
||||
/**
|
||||
* @brief Set integer div
|
||||
* @param divName: div id(Contains div offset, shift, mask information)
|
||||
* @param divValue: div value
|
||||
* @return NONE
|
||||
*/
|
||||
HAL_Status HAL_CRU_ClkSetDiv(uint32_t divName, uint32_t divValue);
|
||||
|
||||
/**
|
||||
* @brief Get integer div
|
||||
* @param divName: div id (Contains div offset, shift, mask information)
|
||||
* @return div value
|
||||
*/
|
||||
uint32_t HAL_CRU_ClkGetDiv(uint32_t divName);
|
||||
|
||||
/**
|
||||
* @brief Set mux
|
||||
* @param muxName: mux id (Contains mux offset, shift, mask information)
|
||||
* @param muxValue: mux value
|
||||
* @return NONE
|
||||
*/
|
||||
HAL_Status HAL_CRU_ClkSetMux(uint32_t muxName, uint32_t muxValue);
|
||||
|
||||
/**
|
||||
* @brief Get mux
|
||||
* @param muxName: mux id (Contains mux offset, shift, mask information)
|
||||
* @return mux value
|
||||
*/
|
||||
uint32_t HAL_CRU_ClkGetMux(uint32_t muxName);
|
||||
|
||||
/**
|
||||
* @brief Get frac div config.
|
||||
* @param rateOut: clk out rate.
|
||||
* @param rate: clk src rate.
|
||||
* @param numerator: the returned numerator.
|
||||
* @param denominator: the returned denominator.
|
||||
* @return HAL_Status.
|
||||
*/
|
||||
HAL_Status HAL_CRU_FracdivGetConfig(uint32_t rateOut, uint32_t rate,
|
||||
uint32_t *numerator,
|
||||
uint32_t *denominator);
|
||||
/**
|
||||
* @brief Get clk freq.
|
||||
* @param clockName: CLOCK_Name id.
|
||||
* @return rate.
|
||||
* @attention these APIs allow direct use in the HAL layer.
|
||||
*/
|
||||
uint32_t HAL_CRU_ClkGetFreq(eCLOCK_Name clockName);
|
||||
|
||||
/**
|
||||
* @brief Set clk freq.
|
||||
* @param clockName: CLOCK_Name id.
|
||||
* @param rate: clk rate.
|
||||
* @return HAL_Status.
|
||||
* @attention these APIs allow direct use in the HAL layer.
|
||||
*/
|
||||
HAL_Status HAL_CRU_ClkSetFreq(eCLOCK_Name clockName, uint32_t rate);
|
||||
|
||||
/**
|
||||
* @brief vop dclk enable.
|
||||
* @param gateId: gate id
|
||||
* @return HAL_Status.
|
||||
* @attention these APIs allow direct use in the HAL layer.
|
||||
*/
|
||||
HAL_Status HAL_CRU_VopDclkEnable(uint32_t gateId);
|
||||
|
||||
/**
|
||||
* @brief vop dclk disable.
|
||||
* @param gateId: gate id
|
||||
* @return HAL_Status.
|
||||
* @attention these APIs allow direct use in the HAL layer.
|
||||
*/
|
||||
HAL_Status HAL_CRU_VopDclkDisable(uint32_t gateId);
|
||||
|
||||
/**
|
||||
* @brief Get Np5 best div.
|
||||
* @param clockName: clk id.
|
||||
* @param rate: clk rate.
|
||||
* @param pRate: clk parent rate
|
||||
* @param bestdiv: the returned bestdiv.
|
||||
* @return HAL_Status.
|
||||
*/
|
||||
HAL_Status HAL_CRU_ClkNp5BestDiv(eCLOCK_Name clockName, uint32_t rate, uint32_t pRate, uint32_t *bestdiv);
|
||||
|
||||
/**
|
||||
* @brief assert CRU global software reset.
|
||||
* @param type: global software reset type.
|
||||
* @return HAL_INVAL if the SoC does not support.
|
||||
*/
|
||||
HAL_Status HAL_CRU_SetGlbSrst(eCRU_GlbSrstType type);
|
||||
|
||||
/**
|
||||
* @brief wdt glbrst enable.
|
||||
* @param wdtType: wdt reset type.
|
||||
* @return HAL_OK.
|
||||
* @attention these APIs allow direct use in the HAL layer.
|
||||
*/
|
||||
HAL_Status HAL_CRU_WdtGlbRstEnable(eCRU_WdtRstType wdtType);
|
||||
|
||||
/**
|
||||
* @brief pll output freq Compensation.
|
||||
* @param clockName: CLOCK_Name id.
|
||||
* @param ppm: Efforts to compensate.
|
||||
* @return HAL_OK.
|
||||
* @attention these APIs allow direct use in the HAL layer.
|
||||
*/
|
||||
HAL_Status HAL_CRU_PllCompensation(eCLOCK_Name clockName, int ppm);
|
||||
|
||||
/**
|
||||
* @brief CRU suspend.
|
||||
* @return HAL_Status.
|
||||
* @attention these APIs allow direct use in the HAL layer.
|
||||
*/
|
||||
HAL_Status HAL_CRU_Suspend(void);
|
||||
|
||||
/**
|
||||
* @brief CRU resume.
|
||||
* @return HAL_Status.
|
||||
* @attention these APIs allow direct use in the HAL layer.
|
||||
*/
|
||||
HAL_Status HAL_CRU_Resume(void);
|
||||
|
||||
#ifdef HAL_CRU_AS_FEATURE_ENABLED
|
||||
/**
|
||||
* @brief it is for AS init.
|
||||
*/
|
||||
void HAL_CRU_AsInit(void);
|
||||
|
||||
/**
|
||||
* @brief it is for AS enable.
|
||||
* @param ch: channel
|
||||
* @param en: 1 is enable, 0 is disable.
|
||||
*/
|
||||
void HAL_CRU_AsEnable(uint8_t ch, uint8_t en);
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* HAL_CRU_MODULE_ENABLED */
|
||||
@@ -0,0 +1,94 @@
|
||||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (c) 2018-2021 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#ifndef _HAL_DEBUG_H_
|
||||
#define _HAL_DEBUG_H_
|
||||
|
||||
/** @addtogroup RK_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DEBUG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/***************************** MACRO Definition ******************************/
|
||||
|
||||
/* Run only for debugging, please refer to how-to-use for the definition of the specification. */
|
||||
//#define HAL_DBG_USING_RTT_SERIAL
|
||||
//#define HAL_DBG_USING_LIBC_PRINTF
|
||||
//#define HAL_DBG_USING_HAL_PRINTF
|
||||
#ifdef HAL_DBG_USING_RTT_SERIAL
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#define HAL_SYSLOG rt_kprintf
|
||||
#elif defined(HAL_DBG_USING_LIBC_PRINTF)
|
||||
#define HAL_SYSLOG printf
|
||||
#elif defined(HAL_DBG_USING_HAL_PRINTF)
|
||||
#define HAL_SYSLOG HAL_DBG_Printf
|
||||
#ifndef HAL_PRINTF_BUF_SIZE
|
||||
#define HAL_PRINTF_BUF_SIZE 128
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/** @defgroup DEBUG_Exported_Definition_Group1 Basic Definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef HAL_SYSLOG
|
||||
#define HAL_SYSLOG HAL_DBG_Printf
|
||||
#endif
|
||||
|
||||
#if defined(HAL_DBG_ON) && defined(HAL_DBG_INFO_ON)
|
||||
#define HAL_DBG(fmt, arg...) HAL_SYSLOG("[HAL INFO] " fmt, ##arg)
|
||||
#else
|
||||
#define HAL_DBG(fmt, arg...) do { if (0) HAL_SYSLOG("[HAL INFO] " fmt, ##arg); } while (0)
|
||||
#endif
|
||||
|
||||
#if defined(HAL_DBG_ON) && defined(HAL_DBG_WRN_ON)
|
||||
#define HAL_DBG_WRN(fmt, arg...) HAL_SYSLOG("[HAL WARNING] " fmt, ##arg)
|
||||
#else
|
||||
#define HAL_DBG_WRN(fmt, arg...) do { if (0) HAL_SYSLOG("[HAL WARNING] " fmt, ##arg); } while (0)
|
||||
#endif
|
||||
|
||||
#if defined(HAL_DBG_ON) && defined(HAL_DBG_ERR_ON)
|
||||
#define HAL_DBG_ERR(fmt, arg...) HAL_SYSLOG("[HAL ERROR] " fmt, ##arg)
|
||||
#else
|
||||
#define HAL_DBG_ERR(fmt, arg...) do { if (0) HAL_SYSLOG("[HAL ERROR] " fmt, ##arg); } while (0)
|
||||
#endif
|
||||
|
||||
#if defined(HAL_DBG_ON) && defined(HAL_ASSERT_ON)
|
||||
#define HAL_ASSERT(expr) \
|
||||
do { \
|
||||
if (!(expr)) \
|
||||
HAL_AssertFailed((const char *)__FILE__, __LINE__); \
|
||||
} while (0)
|
||||
#else
|
||||
#define HAL_ASSERT(expr)
|
||||
#endif
|
||||
|
||||
/***************************** Structure Definition **************************/
|
||||
|
||||
/** @} */
|
||||
/***************************** Function Declare ******************************/
|
||||
/** @defgroup DEBUG_Public_Function_Declare Public Function Declare
|
||||
* @{
|
||||
*/
|
||||
|
||||
void HAL_AssertFailed(const char *file, uint32_t line);
|
||||
HAL_Status HAL_DBG_HEX(char *s, void *buf, uint32_t width, uint32_t len);
|
||||
#ifdef __GNUC__
|
||||
__attribute__((__format__(printf, 1, 2)))
|
||||
#endif
|
||||
int32_t HAL_DBG_Printf(const char *format, ...);
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/** @} */
|
||||
@@ -0,0 +1,205 @@
|
||||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
/** @addtogroup RK_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_DEF
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _HAL_DEF_H_
|
||||
#define _HAL_DEF_H_
|
||||
|
||||
#include "libserial.h"
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <stdarg.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "soc.h"
|
||||
#include "hal_list.h"
|
||||
|
||||
/***************************** MACRO Definition ******************************/
|
||||
/** @defgroup HAL_DEF_Exported_Definition_Group1 Basic Definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SET_BIT(REG, BIT) ((*(volatile uint32_t *)&(REG)) |= (BIT)) /**< Set 1 to the register specific bit field */
|
||||
#define CLEAR_BIT(REG, MASK) ((*(volatile uint32_t *)&(REG)) &= ~(MASK)) /**< Clear the specific bits filed from the register */
|
||||
#define READ_BIT(REG, MASK) ((*(volatile const uint32_t *)&(REG)) & (MASK)) /**< Read the value of a specific bits field from the register */
|
||||
#define CLEAR_REG(REG) ((*(volatile uint32_t *)&(REG)) = (0x0)) /**< Write 0 to the register */
|
||||
#define WRITE_REG(REG, VAL) ((*(volatile uint32_t *)&(REG)) = (VAL)) /**< Write the register */
|
||||
#define READ_REG(REG) ((*(volatile const uint32_t *)&(REG))) /**< Read the register */
|
||||
#define MODIFY_REG(REG, CLEARMASK, SETMASK) \
|
||||
WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) /**< Clear and set the value of a specific bits field from the register */
|
||||
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
|
||||
|
||||
#if defined(__GNUC__) || defined(__CC_ARM)
|
||||
#define MASK_TO_WE(msk) (__builtin_constant_p(msk) ? ((msk) > 0xFFFFU ? 0 : ((msk) << 16)) : ((msk) << 16))
|
||||
#else
|
||||
#define MASK_TO_WE(msk) ((msk) << 16)
|
||||
#endif
|
||||
#define VAL_MASK_WE(msk, val) ((MASK_TO_WE(msk)) | (val))
|
||||
#define WRITE_REG_MASK_WE(reg, msk, val) WRITE_REG(reg, (VAL_MASK_WE(msk, val)))
|
||||
|
||||
/* Misc OPS Marco */
|
||||
#define HAL_MAX_DELAY 0xFFFFFFFFU
|
||||
|
||||
#define RESET 0
|
||||
#define HAL_IS_BIT_SET(REG, MASK) (((*(volatile uint32_t *)&(REG)) & (MASK)) != RESET) /**< Check if the the specific bits filed from the register is valid */
|
||||
#define HAL_IS_BIT_CLR(REG, MASK) (((*(volatile uint32_t *)&(REG)) & (MASK)) == RESET) /**< Check if the the specific bits filed from the register is isvalid */
|
||||
|
||||
#define HAL_BIT(nr) (1UL << (nr))
|
||||
#define HAL_ARRAY_SIZE(a) (sizeof((a)) / sizeof((a)[0]))
|
||||
#define HAL_MAX(x, y) ((x) > (y) ? (x) : (y))
|
||||
#define HAL_MIN(x, y) ((x) < (y) ? (x) : (y))
|
||||
|
||||
#define HAL_DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y))
|
||||
|
||||
#define HAL_IS_ALIGNED(x, a) (((x) & (a - 1)) == 0)
|
||||
#ifdef CACHE_LINE_SIZE
|
||||
#define HAL_IS_CACHELINE_ALIGNED(x) HAL_IS_ALIGNED((uint32_t)(x), CACHE_LINE_SIZE)
|
||||
#else
|
||||
#define HAL_IS_CACHELINE_ALIGNED(x) HAL_IS_ALIGNED((uint32_t)(x), 4)
|
||||
#endif
|
||||
|
||||
/* Compiller Macro */
|
||||
#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM) || defined(__ICCARM__)
|
||||
#define HAL_UNUSED __attribute__((__unused__))
|
||||
#else
|
||||
#define HAL_UNUSED
|
||||
#endif
|
||||
|
||||
#ifdef CACHE_LINE_SIZE
|
||||
#define HAL_CACHELINE_ALIGNED __ALIGNED(CACHE_LINE_SIZE)
|
||||
#else
|
||||
#define HAL_CACHELINE_ALIGNED
|
||||
#endif
|
||||
|
||||
#ifdef HAL_SRAM_SECTION_ENABLED
|
||||
#define HAL_SECTION_SRAM_CODE __attribute__((section(".sram_code")))
|
||||
#define HAL_SECTION_SRAM_RODATA __attribute__((section(".sram_rodata")))
|
||||
#define HAL_SECTION_SRAM_DATA __attribute__((section(".sram_data")))
|
||||
#define HAL_SECTION_SRAM_BSS __attribute__((section(".sram_bss")))
|
||||
#else
|
||||
#define HAL_SECTION_SRAM_CODE
|
||||
#define HAL_SECTION_SRAM_RODATA
|
||||
#define HAL_SECTION_SRAM_DATA
|
||||
#define HAL_SECTION_SRAM_BSS
|
||||
#endif
|
||||
|
||||
#ifdef HAL_PSRAM_SECTION_ENABLED
|
||||
#define HAL_SECTION_PSRAM_CODE __attribute__((section(".psram_code")))
|
||||
#define HAL_SECTION_PSRAM_RODATA __attribute__((section(".psram_rodata")))
|
||||
#define HAL_SECTION_PSRAM_DATA __attribute__((section(".psram_data")))
|
||||
#define HAL_SECTION_PSRAM_BSS __attribute__((section(".psram_bss")))
|
||||
#else
|
||||
#define HAL_SECTION_PSRAM_CODE
|
||||
#define HAL_SECTION_PSRAM_RODATA
|
||||
#define HAL_SECTION_PSRAM_DATA
|
||||
#define HAL_SECTION_PSRAM_BSS
|
||||
#endif
|
||||
|
||||
#ifdef HAL_XIP_SECTION_ENABLED
|
||||
#define HAL_SECTION_XIP_CODE __attribute__((section(".xip_code")))
|
||||
#define HAL_SECTION_XIP_RODATA __attribute__((section(".xip_rodata")))
|
||||
#else
|
||||
#define HAL_SECTION_XIP_CODE
|
||||
#define HAL_SECTION_XIP_RODATA
|
||||
#endif
|
||||
|
||||
#define HAL_GENMASK(h, l) (((~0U) << (l)) & (~0U >> (32 - 1 - (h))))
|
||||
#define HAL_GENVAL(x, h, l) ((uint32_t)(((x) & HAL_GENMASK(h, l)) >> (l)))
|
||||
#define HAL_GENMASK_ULL(h, l) (((~0ULL) << (l)) & (~0ULL >> (64 - 1 - (h))))
|
||||
#define HAL_GENVAL_ULL(x, h, l) ((uint64_t)(((x) & HAL_GENMASK_ULL(h, l)) >> (l)))
|
||||
|
||||
/** MCU systick clock source */
|
||||
typedef enum {
|
||||
HAL_SYSTICK_CLKSRC_CORE,
|
||||
HAL_SYSTICK_CLKSRC_EXT
|
||||
} eHAL_systickClkSource;
|
||||
|
||||
/** Check if is MCU systick clock source */
|
||||
#define IS_SYSTICK_SOURCE(s) (((s) == HAL_SYSTICK_CLKSRC_CORE) || ((s) == HAL_SYSTICK_CLKSRC_EXT))
|
||||
|
||||
/***************************** Structure Definition **************************/
|
||||
/** HAL boolean type definition */
|
||||
typedef enum {
|
||||
HAL_FALSE = 0x00U,
|
||||
HAL_TRUE = 0x01U
|
||||
} HAL_Check;
|
||||
|
||||
/** HAL error code definition */
|
||||
typedef enum {
|
||||
HAL_OK = 0x00U,
|
||||
HAL_ERROR = (-1),
|
||||
HAL_BUSY = (-16),
|
||||
HAL_NODEV = (-19),
|
||||
HAL_INVAL = (-22),
|
||||
HAL_NOSYS = (-38),
|
||||
HAL_TIMEOUT = (-110)
|
||||
} HAL_Status;
|
||||
|
||||
/** HAL functional status definition */
|
||||
typedef enum {
|
||||
HAL_DISABLE = 0x00U,
|
||||
HAL_ENABLE = 0x01U
|
||||
} HAL_FuncStatus;
|
||||
|
||||
/** HAL lock structures definition */
|
||||
typedef enum {
|
||||
HAL_UNLOCKED = 0x00U,
|
||||
HAL_LOCKED = 0x01U
|
||||
} HAL_LockStatus;
|
||||
|
||||
/** RK GPIO bank definition */
|
||||
typedef enum {
|
||||
#ifdef GPIO0
|
||||
GPIO_BANK0 = 0,
|
||||
#endif
|
||||
#ifdef GPIO1
|
||||
GPIO_BANK1 = 1,
|
||||
#endif
|
||||
#ifdef GPIO2
|
||||
GPIO_BANK2 = 2,
|
||||
#endif
|
||||
#ifdef GPIO3
|
||||
GPIO_BANK3 = 3,
|
||||
#endif
|
||||
#ifdef GPIO4
|
||||
GPIO_BANK4 = 4,
|
||||
#endif
|
||||
#ifdef GPIO0_EXP
|
||||
GPIO_BANK0_EXP = 5,
|
||||
#endif
|
||||
#ifdef GPIO1_EXP
|
||||
GPIO_BANK1_EXP = 6,
|
||||
#endif
|
||||
#ifdef GPIO2_EXP
|
||||
GPIO_BANK2_EXP = 7,
|
||||
#endif
|
||||
#ifdef GPIO3_EXP
|
||||
GPIO_BANK3_EXP = 8,
|
||||
#endif
|
||||
#ifdef GPIO4_EXP
|
||||
GPIO_BANK4_EXP = 9,
|
||||
#endif
|
||||
GPIO_BANK_NUM
|
||||
} eGPIO_bankId;
|
||||
|
||||
/** HAL function type definition */
|
||||
typedef void (*pFunc)(void);
|
||||
|
||||
/** @} */
|
||||
/***************************** Function Declare ******************************/
|
||||
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/** @} */
|
||||
@@ -0,0 +1,282 @@
|
||||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (c) 2018-2021 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#ifndef _HAL_DRIVER_H_
|
||||
#define _HAL_DRIVER_H_
|
||||
|
||||
#include "hal_pm.h"
|
||||
|
||||
#ifdef HAL_ACDCDIG_MODULE_ENABLED
|
||||
#include "hal_acdcdig.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_ACODEC_MODULE_ENABLED
|
||||
#include "hal_acodec.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_ARCHTIMER_MODULE_ENABLED
|
||||
#include "hal_archtimer.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_AUDIOPWM_MODULE_ENABLED
|
||||
#include "hal_audiopwm.h"
|
||||
#endif
|
||||
|
||||
// #include "hal_cache.h"
|
||||
|
||||
#ifdef HAL_BUFMGR_MODULE_ENABLED
|
||||
#include "hal_bufmgr.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_CANFD_MODULE_ENABLED
|
||||
#include "hal_canfd.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_CKCAL_MODULE_ENABLED
|
||||
#include "hal_ckcal.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_CACHE_ECC_MODULE_ENABLED
|
||||
#include "hal_cache_ecc.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_CPU_TOPOLOGY_MODULE_ENABLED
|
||||
#include "hal_cpu_topology.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_CRU_MODULE_ENABLED
|
||||
#include "hal_cru.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_CRYPTO_MODULE_ENABLED
|
||||
#include "hal_crypto.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_DSI_MODULE_ENABLED
|
||||
#include "hal_display.h"
|
||||
#include "hal_dsi.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_DEMO_MODULE_ENABLED
|
||||
#include "hal_demo.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_DDR_ECC_MODULE_ENABLED
|
||||
#include "hal_ddr_ecc.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_DSP_MODULE_ENABLED
|
||||
#include "hal_dsp.h"
|
||||
#endif
|
||||
|
||||
// #include "hal_dma.h"
|
||||
|
||||
#ifdef HAL_DWDMA_MODULE_ENABLED
|
||||
#include "hal_dwdma.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_EFUSE_MODULE_ENABLED
|
||||
#include "hal_efuse.h"
|
||||
#endif
|
||||
|
||||
#if defined(HAL_GMAC_MODULE_ENABLED) || defined(HAL_GMAC1000_MODULE_ENABLED)
|
||||
#include "hal_gmac.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
#include "hal_gpio.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED
|
||||
#include "hal_gpio_irq_group.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_PINCTRL_MODULE_ENABLED
|
||||
#include "hal_pinctrl.h"
|
||||
#endif
|
||||
|
||||
#if defined(HAL_HCD_MODULE_ENABLED) || defined(HAL_PCD_MODULE_ENABLED)
|
||||
#include "hal_usb_core.h"
|
||||
#include "hal_usb_phy.h"
|
||||
#endif
|
||||
|
||||
#if defined(HAL_EHCI_MODULE_ENABLED) || defined(HAL_OHCI_MODULE_ENABLED)
|
||||
#include "hal_usbh.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_HCD_MODULE_ENABLED
|
||||
#include "hal_hcd.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_HWSPINLOCK_MODULE_ENABLED
|
||||
#include "hal_hwspinlock.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_HYPERPSRAM_MODULE_ENABLED
|
||||
#include "hal_hyperpsram.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
#include "hal_i2c.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_I2S_MODULE_ENABLED
|
||||
#include "hal_i2s.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_I2STDM_MODULE_ENABLED
|
||||
#include "hal_i2stdm.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_INTC_MODULE_ENABLED
|
||||
#include "hal_intc.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_INTMUX_MODULE_ENABLED
|
||||
#include "hal_intmux.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_IRQ_HANDLER_MODULE_ENABLED
|
||||
#include "hal_irq_handler.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_GIC_MODULE_ENABLED
|
||||
#include "hal_gic.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_MBOX_MODULE_ENABLED
|
||||
#include "hal_mbox.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_NVIC_MODULE_ENABLED
|
||||
#include "hal_nvic.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
#include "hal_pcd.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_PCIE_MODULE_ENABLED
|
||||
#include "hal_pci_core.h"
|
||||
#include "hal_pcie_dma.h"
|
||||
#include "hal_pcie.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_PDM_MODULE_ENABLED
|
||||
#include "hal_pdm.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_PL330_MODULE_ENABLED
|
||||
#include "hal_pl330.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_PMU_MODULE_ENABLED
|
||||
#include "hal_pd.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_PVTM_MODULE_ENABLED
|
||||
#include "hal_pvtm.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_PWM_MODULE_ENABLED
|
||||
#include "hal_pwm.h"
|
||||
#endif
|
||||
|
||||
// #include "hal_pwr.h"
|
||||
|
||||
#ifdef HAL_RISCVIC_MODULE_ENABLED
|
||||
#include "hal_riscvic.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_SDIO_MODULE_ENABLED
|
||||
#include "hal_sdio.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_SNOR_MODULE_ENABLED
|
||||
#include "hal_spi_mem.h"
|
||||
#include "hal_snor.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_SFC_MODULE_ENABLED
|
||||
#include "hal_sfc.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_SPINAND_MODULE_ENABLED
|
||||
#include "hal_spi_mem.h"
|
||||
#include "hal_spinand.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_SPINLOCK_MODULE_ENABLED
|
||||
#include "hal_spinlock.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_SYSTICK_MODULE_ENABLED
|
||||
#include "hal_systick.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_FSPI_MODULE_ENABLED
|
||||
#include "hal_spi_mem.h"
|
||||
#include "hal_fspi.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_QPIPSRAM_MODULE_ENABLED
|
||||
#include "hal_spi_mem.h"
|
||||
#include "hal_qpipsram.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_TOUCHKEY_MODULE_ENABLED
|
||||
#include "hal_touchkey.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_TSADC_MODULE_ENABLED
|
||||
#include "hal_tsadc.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_SARADC_MODULE_ENABLED
|
||||
#include "hal_saradc.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_SMCCC_MODULE_ENABLED
|
||||
#include "hal_smccc.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_KEYCTRL_MODULE_ENABLED
|
||||
#include "hal_keyctrl.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_SPI_MODULE_ENABLED
|
||||
#include "hal_spi.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_SPI2APB_MODULE_ENABLED
|
||||
#include "hal_spi2apb.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_TIMER_MODULE_ENABLED
|
||||
#include "hal_timer.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
#include "hal_uart.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_VAD_MODULE_ENABLED
|
||||
#include "hal_vad.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_VICAP_MODULE_ENABLED
|
||||
#include "hal_vicap.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_VOP_MODULE_ENABLED
|
||||
#include "hal_display.h"
|
||||
#include "hal_vop.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_WDT_MODULE_ENABLED
|
||||
#include "hal_wdt.h"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,350 @@
|
||||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#include "hal_conf.h"
|
||||
|
||||
#if (defined(HAL_GMAC_MODULE_ENABLED) || defined(HAL_GMAC1000_MODULE_ENABLED))
|
||||
|
||||
/** @addtogroup RK_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GMAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __HAL_GMAC_H
|
||||
#define __HAL_GMAC_H
|
||||
|
||||
#include "hal_def.h"
|
||||
#include "hal_base.h"
|
||||
|
||||
/***************************** MACRO Definition ******************************/
|
||||
/** @defgroup GMAC_Exported_Definition_Group1 Basic Definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* GMAC PHY indicates what features are supported by the interface. */
|
||||
#define HAL_GMAC_PHY_SUPPORTED_10baseT_Half (1 << 0)
|
||||
#define HAL_GMAC_PHY_SUPPORTED_10baseT_Full (1 << 1)
|
||||
#define HAL_GMAC_PHY_SUPPORTED_100baseT_Half (1 << 2)
|
||||
#define HAL_GMAC_PHY_SUPPORTED_100baseT_Full (1 << 3)
|
||||
#define HAL_GMAC_PHY_SUPPORTED_1000baseT_Half (1 << 4)
|
||||
#define HAL_GMAC_PHY_SUPPORTED_1000baseT_Full (1 << 5)
|
||||
#define HAL_GMAC_PHY_SUPPORTED_Autoneg (1 << 6)
|
||||
#define HAL_GMAC_PHY_SUPPORTED_TP (1 << 7)
|
||||
#define HAL_GMAC_PHY_SUPPORTED_AUI (1 << 8)
|
||||
#define HAL_GMAC_PHY_SUPPORTED_MII (1 << 9)
|
||||
#define HAL_GMAC_PHY_SUPPORTED_FIBRE (1 << 10)
|
||||
#define HAL_GMAC_PHY_SUPPORTED_BNC (1 << 11)
|
||||
#define HAL_GMAC_PHY_SUPPORTED_10000baseT_Full (1 << 12)
|
||||
#define HAL_GMAC_PHY_SUPPORTED_Pause (1 << 13)
|
||||
#define HAL_GMAC_PHY_SUPPORTED_Asym_Pause (1 << 14)
|
||||
#define HAL_GMAC_PHY_SUPPORTED_2500baseX_Full (1 << 15)
|
||||
#define HAL_GMAC_PHY_SUPPORTED_Backplane (1 << 16)
|
||||
#define HAL_GMAC_PHY_SUPPORTED_1000baseKX_Full (1 << 17)
|
||||
#define HAL_GMAC_PHY_SUPPORTED_10000baseKX4_Full (1 << 18)
|
||||
#define HAL_GMAC_PHY_SUPPORTED_10000baseKR_Full (1 << 19)
|
||||
#define HAL_GMAC_PHY_SUPPORTED_10000baseR_FEC (1 << 20)
|
||||
#define HAL_GMAC_PHY_SUPPORTED_1000baseX_Half (1 << 21)
|
||||
#define HAL_GMAC_PHY_SUPPORTED_1000baseX_Full (1 << 22)
|
||||
|
||||
#define HAL_GMAC_PHY_DEFAULT_FEATURES (HAL_GMAC_PHY_SUPPORTED_Autoneg | \
|
||||
HAL_GMAC_PHY_SUPPORTED_TP | \
|
||||
HAL_GMAC_PHY_SUPPORTED_MII)
|
||||
|
||||
#define HAL_GMAC_PHY_10BT_FEATURES (HAL_GMAC_PHY_SUPPORTED_10baseT_Half | \
|
||||
HAL_GMAC_PHY_SUPPORTED_10baseT_Full)
|
||||
|
||||
#define HAL_GMAC_PHY_100BT_FEATURES (HAL_GMAC_PHY_SUPPORTED_100baseT_Half | \
|
||||
HAL_GMAC_PHY_SUPPORTED_100baseT_Full)
|
||||
|
||||
#define HAL_GMAC_PHY_1000BT_FEATURES (HAL_GMAC_PHY_SUPPORTED_1000baseT_Half | \
|
||||
HAL_GMAC_PHY_SUPPORTED_1000baseT_Full)
|
||||
|
||||
#define HAL_GMAC_PHY_BASIC_FEATURES (HAL_GMAC_PHY_10BT_FEATURES | \
|
||||
HAL_GMAC_PHY_100BT_FEATURES | \
|
||||
HAL_GMAC_PHY_DEFAULT_FEATURES)
|
||||
|
||||
#define HAL_GMAC_PHY_GBIT_FEATURES (HAL_GMAC_PHY_BASIC_FEATURES | \
|
||||
HAL_GMAC_PHY_1000BT_FEATURES)
|
||||
|
||||
/* GMAC flow ctrl Definition */
|
||||
#define HAL_GMAC_FLOW_OFF 0
|
||||
#define HAL_GMAC_FLOW_RX 1
|
||||
#define HAL_GMAC_FLOW_TX 2
|
||||
#define HAL_GMAC_FLOW_AUTO (HAL_GMAC_FLOW_TX | HAL_GMAC_FLOW_RX)
|
||||
|
||||
/* GMAC descriptions and buffers Definition */
|
||||
#define HAL_GMAC_ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1))
|
||||
#define HAL_GMAC_DESCRIPTOR_WORDS 4
|
||||
#define HAL_GMAC_DESCRIPTOR_SIZE (HAL_GMAC_DESCRIPTOR_WORDS * 4)
|
||||
#define HAL_GMAC_BUFFER_ALIGN 64
|
||||
#define HAL_GMAC_MAX_FRAME_SIZE 1518
|
||||
#define HAL_GMAC_MAX_PACKET_SIZE HAL_GMAC_ALIGN(HAL_GMAC_MAX_FRAME_SIZE, HAL_GMAC_BUFFER_ALIGN)
|
||||
|
||||
/***************************** Structure Definition **************************/
|
||||
struct GMAC_HANDLE;
|
||||
|
||||
/**
|
||||
* @brief GMAC PHY Speed
|
||||
*/
|
||||
typedef enum {
|
||||
PHY_SPEED_10M = 10,
|
||||
PHY_SPEED_100M = 100,
|
||||
PHY_SPEED_1000M = 1000,
|
||||
} eGMAC_PHY_SPEED;
|
||||
|
||||
/**
|
||||
* @brief GMAC PHY Duplex
|
||||
*/
|
||||
typedef enum {
|
||||
PHY_DUPLEX_HALF = 0,
|
||||
PHY_DUPLEX_FULL = 1,
|
||||
} eGMAC_PHY_DUPLEX;
|
||||
|
||||
/**
|
||||
* @brief GMAC PHY Auto Negrotetion
|
||||
*/
|
||||
typedef enum {
|
||||
PHY_AUTONEG_DISABLE = 0,
|
||||
PHY_AUTONEG_ENABLE = 1,
|
||||
} eGMAC_PHY_NEGROTETION;
|
||||
|
||||
/**
|
||||
* @brief GMAC PHY Interface Mode
|
||||
*/
|
||||
typedef enum {
|
||||
PHY_INTERFACE_MODE_MII,
|
||||
PHY_INTERFACE_MODE_RMII,
|
||||
PHY_INTERFACE_MODE_RGMII,
|
||||
PHY_INTERFACE_MODE_NONE,
|
||||
} eGMAC_PHY_Interface;
|
||||
|
||||
/**
|
||||
* @brief GMAC DMA IRQ Status
|
||||
*/
|
||||
typedef enum {
|
||||
DMA_UNKNOWN = 0x0,
|
||||
DMA_HANLE_RX = 0x1,
|
||||
DMA_HANLE_TX = 0x2,
|
||||
DMA_TX_ERROR = 0x10,
|
||||
DMA_RX_ERROR = 0x20,
|
||||
} eGMAC_IRQ_Status;
|
||||
|
||||
/**
|
||||
* @brief GMAC PHY OPS Structure Definition
|
||||
*/
|
||||
struct GMAC_PHY_OPS {
|
||||
HAL_Status (*init)(struct GMAC_HANDLE *pGMAC); /**< Will be called during HAL_GMAC_PHYInit(). */
|
||||
HAL_Status (*config)(struct GMAC_HANDLE *pGMAC); /**< Called to configure the PHY, and modify the PHY,
|
||||
based on the results. Should be called after HAL_GMAC_PHYInit(). */
|
||||
HAL_Status (*startup)(struct GMAC_HANDLE *pGMAC); /**< Called when starting up the PHY */
|
||||
HAL_Status (*shutdown)(struct GMAC_HANDLE *pGMAC); /**< Called when bringing down the PHY */
|
||||
HAL_Status (*reset)(struct GMAC_HANDLE *pGMAC); /**< Called when hardware reset */
|
||||
HAL_Status (*softreset)(struct GMAC_HANDLE *pGMAC);/**< Called when soft reset */
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief GMAC PHY Config Structure Definition
|
||||
*/
|
||||
struct GMAC_PHY_Config {
|
||||
eGMAC_PHY_Interface interface;/**< Ethernet interface mode. */
|
||||
int16_t phyAddress; /**< Ethernet PHY address,
|
||||
This parameter must be a number between Min = 0 and Max = 31 */
|
||||
eGMAC_PHY_NEGROTETION neg; /**< Selects or disable the AutoNegotiation mode for the external PHY,
|
||||
The AutoNegotiation allows an automatic setting of the Speed
|
||||
(10/100/1000 Mbps) and the mode (half/full-duplex). */
|
||||
eGMAC_PHY_SPEED speed; /**< Sets the Ethernet speed: 10/100/1000 Mbps
|
||||
while disable AutoNegotiation. */
|
||||
eGMAC_PHY_DUPLEX duplexMode; /**< Selects the Ethernet duplex mode: Half-Duplex or
|
||||
Full-Duplex mode while disable AutoNegotiation. */
|
||||
eGMAC_PHY_SPEED maxSpeed; /**< Sets the Ethernet max speed: 10/100/1000 Mbps. */
|
||||
uint32_t features; /**< Sets the Ethernet PHY features. */
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief GMAC PHY Status Structure Definition
|
||||
*/
|
||||
struct GMAC_PHY_STATUS {
|
||||
eGMAC_PHY_Interface interface; /**< Ethernet interface mode. */
|
||||
|
||||
/* forced speed & duplex (no autoneg)
|
||||
* partner speed & duplex & pause (autoneg)
|
||||
*/
|
||||
eGMAC_PHY_SPEED speed; /**< Ethernet speed. */
|
||||
eGMAC_PHY_DUPLEX duplex; /**< Ethernet duplex. */
|
||||
eGMAC_PHY_SPEED maxSpeed; /**< Ethernet max speed. */
|
||||
eGMAC_PHY_NEGROTETION neg; /**< Ethernet AutoNegotiation or not. */
|
||||
|
||||
/* The most recently read link state */
|
||||
int link; /**< Ethernet current link. */
|
||||
int oldLink; /**< Store the Ethernet last link. */
|
||||
|
||||
uint32_t features; /**< Ethernet PHY actual features. */
|
||||
uint32_t advertising; /**< Ethernet PHY advertising features. */
|
||||
uint32_t supported; /**< Ethernet PHY supported features. */
|
||||
|
||||
int16_t addr; /**< Ethernet PHY address. */
|
||||
int16_t pause; /**< Ethernet PHY address. */
|
||||
uint32_t phyID; /**< Ethernet PHY ID. */
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief GMAC Link Config Structure Definition
|
||||
*/
|
||||
struct GMAC_Link {
|
||||
uint32_t speedMask;
|
||||
uint32_t speed10;
|
||||
uint32_t speed100;
|
||||
uint32_t speed1000;
|
||||
uint32_t duplex;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief GMAC DMA Descriptors Data Structure Definition
|
||||
*/
|
||||
struct GMAC_Desc {
|
||||
uint64_t des0; /**< DMA Descriptors first word */
|
||||
uint64_t des1; /**< DMA Descriptors second word */
|
||||
uint64_t des2; /**< DMA Descriptors third word */
|
||||
uint64_t des3; /**< DMA Descriptors four word */
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief GMAC DMA Transfer Status Structure Definition
|
||||
*/
|
||||
struct GMAC_DMAStats {
|
||||
uint32_t txUndeflowIRQ;
|
||||
uint32_t txProcessStoppedIRQ;
|
||||
uint32_t txJabberIRQ;
|
||||
uint32_t rxOverflowIRQ;
|
||||
uint32_t rxBufUnavIRQ;
|
||||
uint32_t rxProcessStoppedIRQ;
|
||||
uint32_t rxWatchdogIRQ;
|
||||
uint32_t txEarlyIRQ;
|
||||
uint32_t fatalBusErrorIRQ;
|
||||
uint32_t normalIRQN;
|
||||
uint32_t rxNormalIRQN;
|
||||
uint32_t txNormallIRQN;
|
||||
|
||||
uint32_t rxEarlyIRQ;
|
||||
uint32_t thresHold;
|
||||
uint32_t txPktN;
|
||||
uint32_t rxPktN;
|
||||
uint32_t txBytesN;
|
||||
uint32_t rxBytesN;
|
||||
uint32_t txErrors;
|
||||
uint32_t rxErrors;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief GMAC device information Structure Definition
|
||||
*/
|
||||
struct GMAC_DEVICE_INFO {
|
||||
uint32_t miiAddrShift;
|
||||
uint32_t miiAddrMask;
|
||||
uint32_t miiRegShift;
|
||||
uint32_t miiRegMask;
|
||||
uint32_t clkCsrShift;
|
||||
uint32_t clkCsrMask;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief GMAC Handle Structure Definition
|
||||
*/
|
||||
struct GMAC_HANDLE {
|
||||
struct GMAC_REG *pReg; /**< Register base address */
|
||||
uint32_t clkCSR; /**< clock csr value, div for MDC clock */
|
||||
|
||||
struct GMAC_DEVICE_INFO mac; /**< MAC information */
|
||||
|
||||
struct GMAC_PHY_OPS phyOps; /**< phy ops callback function */
|
||||
struct GMAC_PHY_Config phyConfig; /**< phy config provied by user */
|
||||
struct GMAC_PHY_STATUS phyStatus; /**< phy status */
|
||||
|
||||
struct GMAC_Link link; /**< GMAC link config */
|
||||
struct GMAC_DMAStats extraStatus; /**< GMAC DMA transfer status */
|
||||
|
||||
struct GMAC_Desc *rxDescs; /**< First Rx descriptor pointer */
|
||||
struct GMAC_Desc *txDescs; /**< First Tx descriptor pointer */
|
||||
uint8_t *txBuf; /**< First Tx buffer pointer */
|
||||
uint8_t *rxBuf; /**< First Tx buffer pointer */
|
||||
uint32_t txDescIdx; /**< Current Tx descriptor index */
|
||||
uint32_t rxDescIdx; /**< Current Rx descriptor pointer */
|
||||
uint32_t txSize; /**< Tx descriptor size*/
|
||||
uint32_t rxSize; /**< Rx descriptor size */
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief GMAC HW Information Definition
|
||||
*/
|
||||
struct HAL_GMAC_DEV {
|
||||
struct GMAC_REG *pReg;
|
||||
eCLOCK_Name clkID;
|
||||
uint32_t clkGateID;
|
||||
eCLOCK_Name pclkID;
|
||||
uint32_t pclkGateID;
|
||||
IRQn_Type irqNum;
|
||||
ePM_RUNTIME_ID runtimeID;
|
||||
};
|
||||
|
||||
/** @} */
|
||||
|
||||
/***************************** Function Declare ******************************/
|
||||
/** @defgroup GMAC_Public_Function_Declare Public Function Declare
|
||||
* @{
|
||||
*/
|
||||
HAL_Status HAL_GMAC_Init(struct GMAC_HANDLE *pGMAC, struct GMAC_REG *pReg,
|
||||
uint32_t freq, eGMAC_PHY_Interface interface,
|
||||
bool extClk);
|
||||
HAL_Status HAL_GMAC_DeInit(struct GMAC_HANDLE *pGMAC);
|
||||
HAL_Status HAL_GMAC_Start(struct GMAC_HANDLE *pGMAC, uint8_t *addr);
|
||||
HAL_Status HAL_GMAC_Stop(struct GMAC_HANDLE *pGMAC);
|
||||
void HAL_GMAC_EnableDmaIRQ(struct GMAC_HANDLE *pGMAC);
|
||||
void HAL_GMAC_DisableDmaIRQ(struct GMAC_HANDLE *pGMAC);
|
||||
HAL_Status HAL_GMAC_DMATxDescInit(struct GMAC_HANDLE *pGMAC,
|
||||
struct GMAC_Desc *txDescs,
|
||||
uint8_t *txBuff, uint32_t txBuffCount);
|
||||
HAL_Status HAL_GMAC_DMARxDescInit(struct GMAC_HANDLE *pGMAC,
|
||||
struct GMAC_Desc *rxDescs,
|
||||
uint8_t *rxBuff, uint32_t rxBuffCount);
|
||||
eGMAC_IRQ_Status HAL_GMAC_IRQHandler(struct GMAC_HANDLE *pGMAC);
|
||||
HAL_Status HAL_GMAC_AdjustLink(struct GMAC_HANDLE *pGMAC, int32_t txDelay,
|
||||
int32_t rxDelay);
|
||||
uint32_t HAL_GMAC_GetTXIndex(struct GMAC_HANDLE *pGMAC);
|
||||
uint32_t HAL_GMAC_GetRXIndex(struct GMAC_HANDLE *pGMAC);
|
||||
uint8_t *HAL_GMAC_GetTXBuffer(struct GMAC_HANDLE *pGMAC);
|
||||
uint8_t *HAL_GMAC_GetRXBuffer(struct GMAC_HANDLE *pGMAC);
|
||||
HAL_Status HAL_GMAC_Send(struct GMAC_HANDLE *pGMAC,
|
||||
void *packet, uint32_t length);
|
||||
uint8_t *HAL_GMAC_Recv(struct GMAC_HANDLE *pGMAC, int32_t *length);
|
||||
void HAL_GMAC_CleanRX(struct GMAC_HANDLE *pGMAC);
|
||||
void HAL_GMAC_WriteHWAddr(struct GMAC_HANDLE *pGMAC, uint8_t *enetAddr);
|
||||
HAL_Status HAL_GMAC_PHYInit(struct GMAC_HANDLE *pGMAC,
|
||||
struct GMAC_PHY_Config *config);
|
||||
HAL_Status HAL_GMAC_PHYStartup(struct GMAC_HANDLE *pGMAC);
|
||||
HAL_Status HAL_GMAC_PHYUpdateLink(struct GMAC_HANDLE *pGMAC);
|
||||
HAL_Status HAL_GMAC_PHYParseLink(struct GMAC_HANDLE *pGMAC);
|
||||
int32_t HAL_GMAC_MDIORead(struct GMAC_HANDLE *pGMAC, int32_t mdioAddr,
|
||||
int32_t mdioReg);
|
||||
HAL_Status HAL_GMAC_MDIOWrite(struct GMAC_HANDLE *pGMAC, int32_t mdioAddr,
|
||||
int32_t mdioReg, uint16_t mdioVal);
|
||||
void HAL_GMAC_SetToRGMII(struct GMAC_HANDLE *pGMAC,
|
||||
int32_t txDelay, int32_t rxDelay);
|
||||
void HAL_GMAC_SetToRMII(struct GMAC_HANDLE *pGMAC);
|
||||
void HAL_GMAC_SetRGMIISpeed(struct GMAC_HANDLE *pGMAC, int32_t speed);
|
||||
void HAL_GMAC_SetRMIISpeed(struct GMAC_HANDLE *pGMAC, int32_t speed);
|
||||
void HAL_GMAC_SetExtclkSrc(struct GMAC_HANDLE *pGMAC, bool extClk);
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* HAL_GMAC_MODULE_ENABLED */
|
||||
@@ -0,0 +1,170 @@
|
||||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#include "hal_conf.h"
|
||||
|
||||
/** @addtogroup RK_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __HAL_GPIO_H
|
||||
#define __HAL_GPIO_H
|
||||
|
||||
#include "hal_def.h"
|
||||
#include "hal_pinctrl.h"
|
||||
|
||||
/***************************** MACRO Definition ******************************/
|
||||
/** @defgroup GPIO_Exported_Definition_Group1 Basic Definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef GPIO_VER_ID
|
||||
#define GPIO_VER_ID (0U)
|
||||
#endif
|
||||
|
||||
#define PIN_NUMBER_PER_BANK (32)
|
||||
|
||||
#define GPIO_PIN_SHIFT (0) /**< Bits 0-4: GPIO Pin number: 0 - 31 */
|
||||
#define GPIO_PIN_MASK (0x1f << GPIO_PIN_SHIFT)
|
||||
#define GPIO_BANK_SHIFT (5) /**< Bits 5-7: GPIO Port number: 0 - 7 */
|
||||
#define GPIO_BANK_MASK (0x7 << GPIO_BANK_SHIFT)
|
||||
|
||||
#define BANK_PIN(BANK, PIN) ((((BANK) << GPIO_BANK_SHIFT) & GPIO_BANK_MASK) + (((PIN) << GPIO_PIN_SHIFT) & GPIO_PIN_MASK))
|
||||
|
||||
/***************************** Structure Definition **************************/
|
||||
/** GPIO pin level definition */
|
||||
typedef enum {
|
||||
GPIO_LOW,
|
||||
GPIO_HIGH
|
||||
} eGPIO_pinLevel;
|
||||
|
||||
/** GPIO pin direction definition */
|
||||
typedef enum {
|
||||
GPIO_IN,
|
||||
GPIO_OUT
|
||||
} eGPIO_pinDirection;
|
||||
|
||||
/** GPIO pin debounce definition */
|
||||
typedef enum {
|
||||
GPIO_DEBOUNCE_DIS,
|
||||
GPIO_DEBOUNCE_EN
|
||||
} eGPIO_pinDebounce;
|
||||
|
||||
/** GPIO pin interrupt enable definition */
|
||||
typedef enum {
|
||||
GPIO_INT_DISABLE,
|
||||
GPIO_INT_ENABLE
|
||||
} eGPIO_intEnable;
|
||||
|
||||
/** GPIO pin interrupt type definition */
|
||||
typedef enum {
|
||||
GPIO_INT_TYPE_NONE = 0x00000000,
|
||||
GPIO_INT_TYPE_EDGE_RISING = 0x00000001,
|
||||
GPIO_INT_TYPE_EDGE_FALLING = 0x00000002,
|
||||
GPIO_INT_TYPE_EDGE_BOTH = (GPIO_INT_TYPE_EDGE_FALLING | GPIO_INT_TYPE_EDGE_RISING),
|
||||
GPIO_INT_TYPE_LEVEL_HIGH = 0x00000004,
|
||||
GPIO_INT_TYPE_LEVEL_LOW = 0x00000008,
|
||||
GPIO_INT_TYPE_LEVEL_MASK = (GPIO_INT_TYPE_LEVEL_LOW | GPIO_INT_TYPE_LEVEL_HIGH),
|
||||
GPIO_INT_TYPE_SENSE_MASK = 0x0000000f,
|
||||
GPIO_INT_TYPE_DEFAULT = GPIO_INT_TYPE_SENSE_MASK,
|
||||
} eGPIO_intType;
|
||||
|
||||
/** GPIO pin interrupt mode definition */
|
||||
typedef enum {
|
||||
GPIO_INT_MODE_EDGE_RISING,
|
||||
GPIO_INT_MODE_EDGE_FALLING,
|
||||
GPIO_INT_MODE_EDGE_RISING_FALLING,
|
||||
GPIO_INT_MODE_LEVEL_HIGH,
|
||||
GPIO_INT_MODE_LEVEL_LOW,
|
||||
GPIO_INT_MODE_INVALID
|
||||
} eGPIO_intMode;
|
||||
|
||||
/** GPIO pin virtual model definition */
|
||||
typedef enum {
|
||||
GPIO_VIRTUAL_MODEL_OS_A,
|
||||
GPIO_VIRTUAL_MODEL_OS_B,
|
||||
GPIO_VIRTUAL_MODEL_OS_C,
|
||||
GPIO_VIRTUAL_MODEL_OS_D,
|
||||
} eGPIO_VirtualModel;
|
||||
|
||||
#define IS_GPIO_PIN_DIR(ACTION) (((ACTION) == GPIO_IN) || ((ACTION) == GPIO_OUT))
|
||||
#define IS_GPIO_PIN_LEVEL(ACTION) (((ACTION) == GPIO_LOW) || ((ACTION) == GPIO_HIGH))
|
||||
|
||||
#define IS_GPIO_PIN(PIN) ((PIN) != 0x00000000U)
|
||||
#define IS_GPIO_HIGH_PIN(PIN) IS_GPIO_PIN(((PIN) & 0xFFFF0000U))
|
||||
|
||||
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_PIN_A0) || \
|
||||
((PIN) == GPIO_PIN_A1) || \
|
||||
((PIN) == GPIO_PIN_A2) || \
|
||||
((PIN) == GPIO_PIN_A3) || \
|
||||
((PIN) == GPIO_PIN_A4) || \
|
||||
((PIN) == GPIO_PIN_A5) || \
|
||||
((PIN) == GPIO_PIN_A6) || \
|
||||
((PIN) == GPIO_PIN_A7) || \
|
||||
((PIN) == GPIO_PIN_B0) || \
|
||||
((PIN) == GPIO_PIN_B1) || \
|
||||
((PIN) == GPIO_PIN_B2) || \
|
||||
((PIN) == GPIO_PIN_B3) || \
|
||||
((PIN) == GPIO_PIN_B4) || \
|
||||
((PIN) == GPIO_PIN_B5) || \
|
||||
((PIN) == GPIO_PIN_B6) || \
|
||||
((PIN) == GPIO_PIN_B7) || \
|
||||
((PIN) == GPIO_PIN_C0) || \
|
||||
((PIN) == GPIO_PIN_C1) || \
|
||||
((PIN) == GPIO_PIN_C2) || \
|
||||
((PIN) == GPIO_PIN_C3) || \
|
||||
((PIN) == GPIO_PIN_C4) || \
|
||||
((PIN) == GPIO_PIN_C5) || \
|
||||
((PIN) == GPIO_PIN_C6) || \
|
||||
((PIN) == GPIO_PIN_C7) || \
|
||||
((PIN) == GPIO_PIN_D0) || \
|
||||
((PIN) == GPIO_PIN_D1) || \
|
||||
((PIN) == GPIO_PIN_D2) || \
|
||||
((PIN) == GPIO_PIN_D3) || \
|
||||
((PIN) == GPIO_PIN_D4) || \
|
||||
((PIN) == GPIO_PIN_D5) || \
|
||||
((PIN) == GPIO_PIN_D6) || \
|
||||
((PIN) == GPIO_PIN_D7))
|
||||
|
||||
/** @} */
|
||||
/***************************** Function Declare ******************************/
|
||||
/** @defgroup GPIO_Exported_Definition_Group2 Public Functions Declare.
|
||||
* @{
|
||||
*/
|
||||
eGPIO_pinDirection HAL_GPIO_GetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin);
|
||||
eGPIO_pinLevel HAL_GPIO_GetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin);
|
||||
eGPIO_pinLevel HAL_GPIO_GetPinData(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin);
|
||||
uint32_t HAL_GPIO_GetBankLevel(struct GPIO_REG *pGPIO);
|
||||
|
||||
HAL_Status HAL_GPIO_SetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinLevel level);
|
||||
HAL_Status HAL_GPIO_SetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinDirection direction);
|
||||
HAL_Status HAL_GPIO_SetIntType(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_intType mode);
|
||||
|
||||
HAL_Status HAL_GPIO_SetPinsLevel(struct GPIO_REG *pGPIO, uint32_t mPins, eGPIO_pinLevel level);
|
||||
HAL_Status HAL_GPIO_SetPinsDirection(struct GPIO_REG *pGPIO, uint32_t mPins, eGPIO_pinDirection direction);
|
||||
|
||||
void HAL_GPIO_EnableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin);
|
||||
void HAL_GPIO_DisableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin);
|
||||
void HAL_GPIO_IRQHandler(struct GPIO_REG *pGPIO, eGPIO_bankId bank);
|
||||
|
||||
#ifdef HAL_GPIO_VIRTUAL_MODEL_FEATURE_ENABLED
|
||||
HAL_Status HAL_GPIO_EnableVirtualModel(struct GPIO_REG *pGPIO);
|
||||
HAL_Status HAL_GPIO_DisableVirtualModel(struct GPIO_REG *pGPIO);
|
||||
HAL_Status HAL_GPIO_SetVirtualModel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_VirtualModel vmodel);
|
||||
#endif
|
||||
|
||||
/* The parameter pin for this function is special, it's 0~31. */
|
||||
void HAL_GPIO_IRQDispatch(eGPIO_bankId bank, uint32_t pin);
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/** @} */
|
||||
@@ -0,0 +1,181 @@
|
||||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#ifndef _HAL_LIST_H_
|
||||
#define _HAL_LIST_H_
|
||||
|
||||
/***************************** Structure Definition **************************/
|
||||
|
||||
/** double list struct */
|
||||
struct HAL_LIST_NODE {
|
||||
struct HAL_LIST_NODE *next;
|
||||
struct HAL_LIST_NODE *prev;
|
||||
};
|
||||
|
||||
typedef struct HAL_LIST_NODE HAL_LIST;
|
||||
|
||||
/***************************** Function Declare ******************************/
|
||||
/**
|
||||
* @brief cast a member of a structure out to the containing structure
|
||||
* @param ptr: the pointer to the member.
|
||||
* @param type: the type of the container struct this is embedded in.
|
||||
* @param member: the name of the member within the struct.
|
||||
*/
|
||||
#define HAL_CONTAINER_OF(ptr, type, member) \
|
||||
((type *)((char *)(ptr) - (unsigned long)(&((type *)0)->member)))
|
||||
|
||||
/**
|
||||
* @brief initialize a list object
|
||||
* @param object: object itself.
|
||||
*/
|
||||
#define HAL_LIST_OBJECT_INIT(object) { &(object), &(object) }
|
||||
|
||||
#define HAL_LIST_HEAD_INIT(name) { &(name), &(name) }
|
||||
|
||||
/**
|
||||
* @brief initialize a list head
|
||||
* @param name: list name..
|
||||
*/
|
||||
#define HAL_LIST_HEAD(name) \
|
||||
struct HAL_LIST_NODE name = HAL_LIST_HEAD_INIT(name)
|
||||
|
||||
/**
|
||||
* @brief initialize a list
|
||||
* @param l: list to be initialized
|
||||
*/
|
||||
static inline void HAL_LIST_Init(HAL_LIST *l)
|
||||
{
|
||||
l->next = l->prev = l;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief insert a node after a list
|
||||
* @param l: list to insert it
|
||||
* @param n: new node to be inserted
|
||||
*/
|
||||
static inline void HAL_LIST_InsertAfter(HAL_LIST *l, HAL_LIST *n)
|
||||
{
|
||||
l->next->prev = n;
|
||||
n->next = l->next;
|
||||
|
||||
l->next = n;
|
||||
n->prev = l;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief insert a node before a list
|
||||
* @param n: new node to be inserted
|
||||
* @param l: list to insert it
|
||||
*/
|
||||
static inline void HAL_LIST_InsertBefore(HAL_LIST *l, HAL_LIST *n)
|
||||
{
|
||||
l->prev->next = n;
|
||||
n->prev = l->prev;
|
||||
|
||||
l->prev = n;
|
||||
n->next = l;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief remove node from list.
|
||||
* @param n: the node to remove from the list.
|
||||
*/
|
||||
static inline void HAL_LIST_Remove(HAL_LIST *n)
|
||||
{
|
||||
n->next->prev = n->prev;
|
||||
n->prev->next = n->next;
|
||||
|
||||
n->next = n->prev = n;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief tests whether a list is empty
|
||||
* @param l: the list to test.
|
||||
*/
|
||||
static inline int HAL_LIST_IsEmpty(const HAL_LIST *l)
|
||||
{
|
||||
return l->next == l;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get the list length
|
||||
* @param l: the list to get.
|
||||
*/
|
||||
static inline uint32_t HAL_LIST_Len(const HAL_LIST *l)
|
||||
{
|
||||
uint32_t len = 0;
|
||||
const HAL_LIST *p = l;
|
||||
|
||||
while (p->next != l) {
|
||||
p = p->next;
|
||||
len++;
|
||||
}
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get the struct for this entry
|
||||
* @param node: the entry point
|
||||
* @param type: the type of structure
|
||||
* @param member: the name of list in structure
|
||||
*/
|
||||
#define HAL_LIST_ENTRY(node, type, member) \
|
||||
HAL_CONTAINER_OF(node, type, member)
|
||||
|
||||
/**
|
||||
* @brief iterate over a list
|
||||
* @param pos: the rt_list_t * to use as a loop cursor.
|
||||
* @param head: the head for your list.
|
||||
*/
|
||||
#define HAL_LIST_FOR_EACH(pos, head) \
|
||||
for (pos = (head)->next; pos != (head); pos = pos->next)
|
||||
|
||||
/**
|
||||
* @brief iterate over a list safe against removal of list entry
|
||||
* @param pos: the rt_list_t * to use as a loop cursor.
|
||||
* @param n: another rt_list_t * to use as temporary storage
|
||||
* @param head: the head for your list.
|
||||
*/
|
||||
#define HAL_LIST_FOR_EACH_SAFE(pos, n, head) \
|
||||
for (pos = (head)->next, n = pos->next; pos != (head); \
|
||||
pos = n, n = pos->next)
|
||||
|
||||
/**
|
||||
* @brief iterate over list of given type
|
||||
* @param pos: the type * to use as a loop cursor.
|
||||
* @param head: the head for your list.
|
||||
* @param member: the name of the list_struct within the struct.
|
||||
*/
|
||||
#define HAL_LIST_FOR_EACH_ENTRY(pos, head, member) \
|
||||
for (pos = HAL_LIST_ENTRY((head)->next, __typeof__(*pos), member); \
|
||||
&pos->member != (head); \
|
||||
pos = HAL_LIST_ENTRY(pos->member.next, __typeof__(*pos), member))
|
||||
|
||||
/**
|
||||
* @brief iterate over list of given type safe against removal of list entry
|
||||
* @param pos: the type * to use as a loop cursor.
|
||||
* @param n: another type * to use as temporary storage
|
||||
* @param head: the head for your list.
|
||||
* @param member: the name of the list_struct within the struct.
|
||||
*/
|
||||
#define HAL_LIST_FOR_EACH_ENTRY_SAFE(pos, n, head, member) \
|
||||
for (pos = HAL_LIST_ENTRY((head)->next, __typeof__(*pos), member), \
|
||||
n = HAL_LIST_ENTRY(pos->member.next, __typeof__(*pos), member); \
|
||||
&pos->member != (head); \
|
||||
pos = n, n = HAL_LIST_ENTRY(n->member.next, __typeof__(*n), member))
|
||||
|
||||
/**
|
||||
* @brief get the first element from a list
|
||||
* @param ptr: the list head to take the element from.
|
||||
* @param type: the type of the struct this is embedded in.
|
||||
* @param member: the name of the list_struct within the struct.
|
||||
*
|
||||
* Note, that list is expected to be not empty.
|
||||
*/
|
||||
#define HAL_LIST_FIRST_ENTRY(ptr, type, member) \
|
||||
HAL_LIST_ENTRY((ptr)->next, type, member)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,746 @@
|
||||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#include "hal_conf.h"
|
||||
|
||||
/** @addtogroup RK_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PINCTRL
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __HAL_PINCTRL_H__
|
||||
#define __HAL_PINCTRL_H__
|
||||
|
||||
#include "hal_def.h"
|
||||
|
||||
/***************************** MACRO Definition ******************************/
|
||||
/** @defgroup PINCTRL_Exported_Definition_Group1 Basic Definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** PINCTRL IOFUNC Select definition */
|
||||
typedef enum {
|
||||
IOFUNC_SEL_M0,
|
||||
IOFUNC_SEL_M1,
|
||||
IOFUNC_SEL_M2,
|
||||
} eIOFUNC_SEL;
|
||||
|
||||
typedef enum {
|
||||
#if defined(GPIO0)
|
||||
GPIO0_A0 = 0,
|
||||
GPIO0_A1,
|
||||
GPIO0_A2,
|
||||
GPIO0_A3,
|
||||
GPIO0_A4,
|
||||
GPIO0_A5,
|
||||
GPIO0_A6,
|
||||
GPIO0_A7,
|
||||
GPIO0_B0 = 8,
|
||||
GPIO0_B1,
|
||||
GPIO0_B2,
|
||||
GPIO0_B3,
|
||||
GPIO0_B4,
|
||||
GPIO0_B5,
|
||||
GPIO0_B6,
|
||||
GPIO0_B7,
|
||||
GPIO0_C0 = 16,
|
||||
GPIO0_C1,
|
||||
GPIO0_C2,
|
||||
GPIO0_C3,
|
||||
GPIO0_C4,
|
||||
GPIO0_C5,
|
||||
GPIO0_C6,
|
||||
GPIO0_C7,
|
||||
GPIO0_D0 = 24,
|
||||
GPIO0_D1,
|
||||
GPIO0_D2,
|
||||
GPIO0_D3,
|
||||
GPIO0_D4,
|
||||
GPIO0_D5,
|
||||
GPIO0_D6,
|
||||
GPIO0_D7,
|
||||
#endif
|
||||
#if defined(GPIO1)
|
||||
GPIO1_A0 = 32,
|
||||
GPIO1_A1,
|
||||
GPIO1_A2,
|
||||
GPIO1_A3,
|
||||
GPIO1_A4,
|
||||
GPIO1_A5,
|
||||
GPIO1_A6,
|
||||
GPIO1_A7,
|
||||
GPIO1_B0 = 40,
|
||||
GPIO1_B1,
|
||||
GPIO1_B2,
|
||||
GPIO1_B3,
|
||||
GPIO1_B4,
|
||||
GPIO1_B5,
|
||||
GPIO1_B6,
|
||||
GPIO1_B7,
|
||||
GPIO1_C0 = 48,
|
||||
GPIO1_C1,
|
||||
GPIO1_C2,
|
||||
GPIO1_C3,
|
||||
GPIO1_C4,
|
||||
GPIO1_C5,
|
||||
GPIO1_C6,
|
||||
GPIO1_C7,
|
||||
GPIO1_D0 = 56,
|
||||
GPIO1_D1,
|
||||
GPIO1_D2,
|
||||
GPIO1_D3,
|
||||
GPIO1_D4,
|
||||
GPIO1_D5,
|
||||
GPIO1_D6,
|
||||
GPIO1_D7,
|
||||
#endif
|
||||
#if defined(GPIO2)
|
||||
GPIO2_A0 = 64,
|
||||
GPIO2_A1,
|
||||
GPIO2_A2,
|
||||
GPIO2_A3,
|
||||
GPIO2_A4,
|
||||
GPIO2_A5,
|
||||
GPIO2_A6,
|
||||
GPIO2_A7,
|
||||
GPIO2_B0 = 72,
|
||||
GPIO2_B1,
|
||||
GPIO2_B2,
|
||||
GPIO2_B3,
|
||||
GPIO2_B4,
|
||||
GPIO2_B5,
|
||||
GPIO2_B6,
|
||||
GPIO2_B7,
|
||||
GPIO2_C0 = 80,
|
||||
GPIO2_C1,
|
||||
GPIO2_C2,
|
||||
GPIO2_C3,
|
||||
GPIO2_C4,
|
||||
GPIO2_C5,
|
||||
GPIO2_C6,
|
||||
GPIO2_C7,
|
||||
GPIO2_D0 = 88,
|
||||
GPIO2_D1,
|
||||
GPIO2_D2,
|
||||
GPIO2_D3,
|
||||
GPIO2_D4,
|
||||
GPIO2_D5,
|
||||
GPIO2_D6,
|
||||
GPIO2_D7,
|
||||
#endif
|
||||
#if defined(GPIO3)
|
||||
GPIO3_A0 = 96,
|
||||
GPIO3_A1,
|
||||
GPIO3_A2,
|
||||
GPIO3_A3,
|
||||
GPIO3_A4,
|
||||
GPIO3_A5,
|
||||
GPIO3_A6,
|
||||
GPIO3_A7,
|
||||
GPIO3_B0 = 104,
|
||||
GPIO3_B1,
|
||||
GPIO3_B2,
|
||||
GPIO3_B3,
|
||||
GPIO3_B4,
|
||||
GPIO3_B5,
|
||||
GPIO3_B6,
|
||||
GPIO3_B7,
|
||||
GPIO3_C0 = 112,
|
||||
GPIO3_C1,
|
||||
GPIO3_C2,
|
||||
GPIO3_C3,
|
||||
GPIO3_C4,
|
||||
GPIO3_C5,
|
||||
GPIO3_C6,
|
||||
GPIO3_C7,
|
||||
GPIO3_D0 = 120,
|
||||
GPIO3_D1,
|
||||
GPIO3_D2,
|
||||
GPIO3_D3,
|
||||
GPIO3_D4,
|
||||
GPIO3_D5,
|
||||
GPIO3_D6,
|
||||
GPIO3_D7,
|
||||
#endif
|
||||
#if defined(GPIO4)
|
||||
GPIO4_A0 = 128,
|
||||
GPIO4_A1,
|
||||
GPIO4_A2,
|
||||
GPIO4_A3,
|
||||
GPIO4_A4,
|
||||
GPIO4_A5,
|
||||
GPIO4_A6,
|
||||
GPIO4_A7,
|
||||
GPIO4_B0 = 136,
|
||||
GPIO4_B1,
|
||||
GPIO4_B2,
|
||||
GPIO4_B3,
|
||||
GPIO4_B4,
|
||||
GPIO4_B5,
|
||||
GPIO4_B6,
|
||||
GPIO4_B7,
|
||||
GPIO4_C0 = 144,
|
||||
GPIO4_C1,
|
||||
GPIO4_C2,
|
||||
GPIO4_C3,
|
||||
GPIO4_C4,
|
||||
GPIO4_C5,
|
||||
GPIO4_C6,
|
||||
GPIO4_C7,
|
||||
GPIO4_D0 = 152,
|
||||
GPIO4_D1,
|
||||
GPIO4_D2,
|
||||
GPIO4_D3,
|
||||
GPIO4_D4,
|
||||
GPIO4_D5,
|
||||
GPIO4_D6,
|
||||
GPIO4_D7,
|
||||
#endif
|
||||
#if defined(GPIO0_EXP)
|
||||
GPIO0_EXP_A0 = 160,
|
||||
GPIO0_EXP_A1,
|
||||
GPIO0_EXP_A2,
|
||||
GPIO0_EXP_A3,
|
||||
GPIO0_EXP_A4,
|
||||
GPIO0_EXP_A5,
|
||||
GPIO0_EXP_A6,
|
||||
GPIO0_EXP_A7,
|
||||
GPIO0_EXP_B0 = 168,
|
||||
GPIO0_EXP_B1,
|
||||
GPIO0_EXP_B2,
|
||||
GPIO0_EXP_B3,
|
||||
GPIO0_EXP_B4,
|
||||
GPIO0_EXP_B5,
|
||||
GPIO0_EXP_B6,
|
||||
GPIO0_EXP_B7,
|
||||
GPIO0_EXP_C0 = 176,
|
||||
GPIO0_EXP_C1,
|
||||
GPIO0_EXP_C2,
|
||||
GPIO0_EXP_C3,
|
||||
GPIO0_EXP_C4,
|
||||
GPIO0_EXP_C5,
|
||||
GPIO0_EXP_C6,
|
||||
GPIO0_EXP_C7,
|
||||
GPIO0_EXP_D0 = 184,
|
||||
GPIO0_EXP_D1,
|
||||
GPIO0_EXP_D2,
|
||||
GPIO0_EXP_D3,
|
||||
GPIO0_EXP_D4,
|
||||
GPIO0_EXP_D5,
|
||||
GPIO0_EXP_D6,
|
||||
GPIO0_EXP_D7,
|
||||
#endif
|
||||
#if defined(GPIO1_EXP)
|
||||
GPIO1_EXP_A0 = 192,
|
||||
GPIO1_EXP_A1,
|
||||
GPIO1_EXP_A2,
|
||||
GPIO1_EXP_A3,
|
||||
GPIO1_EXP_A4,
|
||||
GPIO1_EXP_A5,
|
||||
GPIO1_EXP_A6,
|
||||
GPIO1_EXP_A7,
|
||||
GPIO1_EXP_B0 = 200,
|
||||
GPIO1_EXP_B1,
|
||||
GPIO1_EXP_B2,
|
||||
GPIO1_EXP_B3,
|
||||
GPIO1_EXP_B4,
|
||||
GPIO1_EXP_B5,
|
||||
GPIO1_EXP_B6,
|
||||
GPIO1_EXP_B7,
|
||||
GPIO1_EXP_C0 = 208,
|
||||
GPIO1_EXP_C1,
|
||||
GPIO1_EXP_C2,
|
||||
GPIO1_EXP_C3,
|
||||
GPIO1_EXP_C4,
|
||||
GPIO1_EXP_C5,
|
||||
GPIO1_EXP_C6,
|
||||
GPIO1_EXP_C7,
|
||||
GPIO1_EXP_D0 = 216,
|
||||
GPIO1_EXP_D1,
|
||||
GPIO1_EXP_D2,
|
||||
GPIO1_EXP_D3,
|
||||
GPIO1_EXP_D4,
|
||||
GPIO1_EXP_D5,
|
||||
GPIO1_EXP_D6,
|
||||
GPIO1_EXP_D7,
|
||||
#endif
|
||||
#if defined(GPIO2_EXP)
|
||||
GPIO2_EXP_A0 = 224,
|
||||
GPIO2_EXP_A1,
|
||||
GPIO2_EXP_A2,
|
||||
GPIO2_EXP_A3,
|
||||
GPIO2_EXP_A4,
|
||||
GPIO2_EXP_A5,
|
||||
GPIO2_EXP_A6,
|
||||
GPIO2_EXP_A7,
|
||||
GPIO2_EXP_B0 = 232,
|
||||
GPIO2_EXP_B1,
|
||||
GPIO2_EXP_B2,
|
||||
GPIO2_EXP_B3,
|
||||
GPIO2_EXP_B4,
|
||||
GPIO2_EXP_B5,
|
||||
GPIO2_EXP_B6,
|
||||
GPIO2_EXP_B7,
|
||||
GPIO2_EXP_C0 = 240,
|
||||
GPIO2_EXP_C1,
|
||||
GPIO2_EXP_C2,
|
||||
GPIO2_EXP_C3,
|
||||
GPIO2_EXP_C4,
|
||||
GPIO2_EXP_C5,
|
||||
GPIO2_EXP_C6,
|
||||
GPIO2_EXP_C7,
|
||||
GPIO2_EXP_D0 = 248,
|
||||
GPIO2_EXP_D1,
|
||||
GPIO2_EXP_D2,
|
||||
GPIO2_EXP_D3,
|
||||
GPIO2_EXP_D4,
|
||||
GPIO2_EXP_D5,
|
||||
GPIO2_EXP_D6,
|
||||
GPIO2_EXP_D7,
|
||||
#endif
|
||||
#if defined(GPIO3_EXP)
|
||||
GPIO3_EXP_A0 = 256,
|
||||
GPIO3_EXP_A1,
|
||||
GPIO3_EXP_A2,
|
||||
GPIO3_EXP_A3,
|
||||
GPIO3_EXP_A4,
|
||||
GPIO3_EXP_A5,
|
||||
GPIO3_EXP_A6,
|
||||
GPIO3_EXP_A7,
|
||||
GPIO3_EXP_B0 = 264,
|
||||
GPIO3_EXP_B1,
|
||||
GPIO3_EXP_B2,
|
||||
GPIO3_EXP_B3,
|
||||
GPIO3_EXP_B4,
|
||||
GPIO3_EXP_B5,
|
||||
GPIO3_EXP_B6,
|
||||
GPIO3_EXP_B7,
|
||||
GPIO3_EXP_C0 = 272,
|
||||
GPIO3_EXP_C1,
|
||||
GPIO3_EXP_C2,
|
||||
GPIO3_EXP_C3,
|
||||
GPIO3_EXP_C4,
|
||||
GPIO3_EXP_C5,
|
||||
GPIO3_EXP_C6,
|
||||
GPIO3_EXP_C7,
|
||||
GPIO3_EXP_D0 = 280,
|
||||
GPIO3_EXP_D1,
|
||||
GPIO3_EXP_D2,
|
||||
GPIO3_EXP_D3,
|
||||
GPIO3_EXP_D4,
|
||||
GPIO3_EXP_D5,
|
||||
GPIO3_EXP_D6,
|
||||
GPIO3_EXP_D7,
|
||||
#endif
|
||||
#if defined(GPIO4_EXP)
|
||||
GPIO4_EXP_A0 = 288,
|
||||
GPIO4_EXP_A1,
|
||||
GPIO4_EXP_A2,
|
||||
GPIO4_EXP_A3,
|
||||
GPIO4_EXP_A4,
|
||||
GPIO4_EXP_A5,
|
||||
GPIO4_EXP_A6,
|
||||
GPIO4_EXP_A7,
|
||||
GPIO4_EXP_B0 = 296,
|
||||
GPIO4_EXP_B1,
|
||||
GPIO4_EXP_B2,
|
||||
GPIO4_EXP_B3,
|
||||
GPIO4_EXP_B4,
|
||||
GPIO4_EXP_B5,
|
||||
GPIO4_EXP_B6,
|
||||
GPIO4_EXP_B7,
|
||||
GPIO4_EXP_C0 = 304,
|
||||
GPIO4_EXP_C1,
|
||||
GPIO4_EXP_C2,
|
||||
GPIO4_EXP_C3,
|
||||
GPIO4_EXP_C4,
|
||||
GPIO4_EXP_C5,
|
||||
GPIO4_EXP_C6,
|
||||
GPIO4_EXP_C7,
|
||||
GPIO4_EXP_D0 = 312,
|
||||
GPIO4_EXP_D1,
|
||||
GPIO4_EXP_D2,
|
||||
GPIO4_EXP_D3,
|
||||
GPIO4_EXP_D4,
|
||||
GPIO4_EXP_D5,
|
||||
GPIO4_EXP_D6,
|
||||
GPIO4_EXP_D7,
|
||||
#endif
|
||||
GPIO_NUM_MAX
|
||||
} ePINCTRL_PIN;
|
||||
|
||||
/** PINCTRL IOMUX definition */
|
||||
typedef enum {
|
||||
PINCTRL_IOMUX_FUNC0,
|
||||
PINCTRL_IOMUX_FUNC1,
|
||||
PINCTRL_IOMUX_FUNC2,
|
||||
PINCTRL_IOMUX_FUNC3,
|
||||
PINCTRL_IOMUX_FUNC4,
|
||||
PINCTRL_IOMUX_FUNC5,
|
||||
PINCTRL_IOMUX_FUNC6,
|
||||
PINCTRL_IOMUX_FUNC7,
|
||||
PINCTRL_IOMUX_FUNC8,
|
||||
PINCTRL_IOMUX_FUNC9,
|
||||
PINCTRL_IOMUX_FUNC10,
|
||||
PINCTRL_IOMUX_FUNC11,
|
||||
PINCTRL_IOMUX_FUNC12,
|
||||
PINCTRL_IOMUX_FUNC13,
|
||||
PINCTRL_IOMUX_FUNC14,
|
||||
PINCTRL_IOMUX_FUNC15
|
||||
} ePINCTRL_iomuxFunc;
|
||||
|
||||
/** PINCTRL PULL definition */
|
||||
typedef enum {
|
||||
PINCTRL_PULL_OD,
|
||||
PINCTRL_PULL_UP,
|
||||
PINCTRL_PULL_DOWN,
|
||||
PINCTRL_PULL_KEEP
|
||||
} ePINCTRL_pullMode;
|
||||
|
||||
/** PINCTRL Drive Strength definition */
|
||||
typedef enum {
|
||||
PINCTRL_DRIVE_LEVEL0,
|
||||
PINCTRL_DRIVE_LEVEL1,
|
||||
PINCTRL_DRIVE_LEVEL2,
|
||||
PINCTRL_DRIVE_LEVEL3,
|
||||
PINCTRL_DRIVE_LEVEL4,
|
||||
PINCTRL_DRIVE_LEVEL5,
|
||||
PINCTRL_DRIVE_LEVEL6,
|
||||
PINCTRL_DRIVE_LEVEL7
|
||||
} ePINCTRL_driveLevel;
|
||||
|
||||
/** PINCTRL Slew Rate definition */
|
||||
typedef enum {
|
||||
PINCTRL_SLEWRATE_SLOW,
|
||||
PINCTRL_SLEWRATE_FAST
|
||||
} ePINCTRL_slewRate;
|
||||
|
||||
/** PINCTRL Schmitt enable definition */
|
||||
typedef enum {
|
||||
PINCTRL_SCHMITT_DIS,
|
||||
PINCTRL_SCHMITT_EN
|
||||
} ePINCTRL_schmitt;
|
||||
|
||||
#define FLAG_MUX HAL_BIT(31)
|
||||
#define FLAG_PUL HAL_BIT(30)
|
||||
#define FLAG_DRV HAL_BIT(29)
|
||||
#define FLAG_SRT HAL_BIT(28)
|
||||
#define FLAG_SMT HAL_BIT(27)
|
||||
#define SHIFT_MUX (0)
|
||||
#define SHIFT_PUL (4)
|
||||
#define SHIFT_DRV (8)
|
||||
#define SHIFT_SRT (16)
|
||||
#define SHIFT_SMT (18)
|
||||
#define MASK_MUX (0xFU << SHIFT_MUX)
|
||||
#define MASK_PUL (0xFU << SHIFT_PUL)
|
||||
#define MASK_DRV (0xFFU << SHIFT_DRV)
|
||||
#define MASK_SRT (0x3U << SHIFT_SRT)
|
||||
#define MASK_SMT (0x3U << SHIFT_SMT)
|
||||
|
||||
/** @brief PIN Configuration Mode
|
||||
* Elements values convention: gggg g000 0000 ttrr dddd dddd pppp xxxx
|
||||
* - ggggg : Flag to set Mux/Pull/Drive/Slewrate/Schmitt
|
||||
* - tt : Schmitt value
|
||||
* - rr : Slewrate value
|
||||
* - dddddddd : Drive value
|
||||
* - pppp : Pull value
|
||||
* - xxxx : Mux mode value
|
||||
*/
|
||||
typedef enum {
|
||||
PIN_CONFIG_MUX_FUNC0 = (0x0 << SHIFT_MUX | FLAG_MUX),
|
||||
PIN_CONFIG_MUX_FUNC1 = (0x1 << SHIFT_MUX | FLAG_MUX),
|
||||
PIN_CONFIG_MUX_FUNC2 = (0x2 << SHIFT_MUX | FLAG_MUX),
|
||||
PIN_CONFIG_MUX_FUNC3 = (0x3 << SHIFT_MUX | FLAG_MUX),
|
||||
PIN_CONFIG_MUX_FUNC4 = (0x4 << SHIFT_MUX | FLAG_MUX),
|
||||
PIN_CONFIG_MUX_FUNC5 = (0x5 << SHIFT_MUX | FLAG_MUX),
|
||||
PIN_CONFIG_MUX_FUNC6 = (0x6 << SHIFT_MUX | FLAG_MUX),
|
||||
PIN_CONFIG_MUX_FUNC7 = (0x7 << SHIFT_MUX | FLAG_MUX),
|
||||
PIN_CONFIG_MUX_FUNC8 = (0x8 << SHIFT_MUX | FLAG_MUX),
|
||||
PIN_CONFIG_MUX_FUNC9 = (0x9 << SHIFT_MUX | FLAG_MUX),
|
||||
PIN_CONFIG_MUX_FUNC10 = (0xa << SHIFT_MUX | FLAG_MUX),
|
||||
PIN_CONFIG_MUX_FUNC11 = (0xb << SHIFT_MUX | FLAG_MUX),
|
||||
PIN_CONFIG_MUX_FUNC12 = (0xc << SHIFT_MUX | FLAG_MUX),
|
||||
PIN_CONFIG_MUX_FUNC13 = (0xd << SHIFT_MUX | FLAG_MUX),
|
||||
PIN_CONFIG_MUX_FUNC14 = (0xe << SHIFT_MUX | FLAG_MUX),
|
||||
PIN_CONFIG_MUX_FUNC15 = (0xf << SHIFT_MUX | FLAG_MUX),
|
||||
PIN_CONFIG_MUX_DEFAULT = PIN_CONFIG_MUX_FUNC0,
|
||||
|
||||
#if defined(SOC_SWALLOW)
|
||||
PIN_CONFIG_PUL_NORMAL = (0x1 << SHIFT_PUL | FLAG_PUL),
|
||||
PIN_CONFIG_PUL_DEFAULT = (0x0 << SHIFT_PUL | FLAG_PUL),
|
||||
PIN_CONFIG_PUL_UP = PIN_CONFIG_PUL_DEFAULT,
|
||||
PIN_CONFIG_PUL_DOWN = PIN_CONFIG_PUL_DEFAULT,
|
||||
PIN_CONFIG_PUL_KEEP = PIN_CONFIG_PUL_DEFAULT,
|
||||
#elif defined(SOC_RK3588)
|
||||
PIN_CONFIG_PUL_NORMAL = (0x0 << SHIFT_PUL | FLAG_PUL),
|
||||
PIN_CONFIG_PUL_DOWN = (0x1 << SHIFT_PUL | FLAG_PUL),
|
||||
PIN_CONFIG_PUL_KEEP = (0x2 << SHIFT_PUL | FLAG_PUL),
|
||||
PIN_CONFIG_PUL_UP = (0x3 << SHIFT_PUL | FLAG_PUL),
|
||||
PIN_CONFIG_PUL_DEFAULT = PIN_CONFIG_PUL_NORMAL,
|
||||
#else
|
||||
PIN_CONFIG_PUL_NORMAL = (0x0 << SHIFT_PUL | FLAG_PUL),
|
||||
PIN_CONFIG_PUL_UP = (0x1 << SHIFT_PUL | FLAG_PUL),
|
||||
PIN_CONFIG_PUL_DOWN = (0x2 << SHIFT_PUL | FLAG_PUL),
|
||||
PIN_CONFIG_PUL_KEEP = (0x3 << SHIFT_PUL | FLAG_PUL),
|
||||
PIN_CONFIG_PUL_DEFAULT = PIN_CONFIG_PUL_NORMAL,
|
||||
#endif
|
||||
|
||||
#if defined(SOC_RK3568) || defined(SOC_RV1106) || defined(SOC_RK3562)
|
||||
PIN_CONFIG_DRV_LEVEL0 = (0x1 << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL1 = (0x3 << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL2 = (0x7 << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL3 = (0xf << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL4 = (0x1f << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL5 = (0x3f << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL_DEFAULT = PIN_CONFIG_DRV_LEVEL2,
|
||||
#elif defined(SOC_RK3588)
|
||||
PIN_CONFIG_DRV_LEVEL0 = (0x0 << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL1 = (0x2 << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL2 = (0x1 << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL3 = (0x3 << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL_DEFAULT = PIN_CONFIG_DRV_LEVEL2,
|
||||
#else
|
||||
PIN_CONFIG_DRV_LEVEL0 = (0x0 << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL1 = (0x1 << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL2 = (0x2 << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL3 = (0x3 << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL4 = (0x4 << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL5 = (0x5 << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL6 = (0x6 << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL7 = (0x7 << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL_DEFAULT = PIN_CONFIG_DRV_LEVEL2,
|
||||
#endif
|
||||
|
||||
#if defined(SOC_RV1106)
|
||||
PIN_CONFIG_SRT_SLOW = (0x0 << SHIFT_SRT | FLAG_SRT),
|
||||
PIN_CONFIG_SRT_FAST = (0x3 << SHIFT_SRT | FLAG_SRT),
|
||||
PIN_CONFIG_SRT_DEFAULT = PIN_CONFIG_SRT_FAST,
|
||||
#elif defined(SOC_RK3562)
|
||||
PIN_CONFIG_SRT_LEVEL0 = (0x0 << SHIFT_SRT | FLAG_SRT),
|
||||
PIN_CONFIG_SRT_LEVEL1 = (0x1 << SHIFT_SRT | FLAG_SRT),
|
||||
PIN_CONFIG_SRT_LEVEL2 = (0x2 << SHIFT_SRT | FLAG_SRT),
|
||||
PIN_CONFIG_SRT_LEVEL3 = (0x3 << SHIFT_SRT | FLAG_SRT),
|
||||
PIN_CONFIG_SRT_DEFAULT = PIN_CONFIG_SRT_LEVEL3,
|
||||
#else
|
||||
PIN_CONFIG_SRT_SLOW = (0x0 << SHIFT_SRT | FLAG_SRT),
|
||||
PIN_CONFIG_SRT_FAST = (0x1 << SHIFT_SRT | FLAG_SRT),
|
||||
PIN_CONFIG_SRT_DEFAULT = PIN_CONFIG_SRT_SLOW,
|
||||
#endif
|
||||
|
||||
#if defined(SOC_RK3562)
|
||||
PIN_CONFIG_SMT_DISABLE_ALL = (0x0 << SHIFT_SMT | FLAG_SMT),
|
||||
PIN_CONFIG_SMT_DISABLE_IE = (0x1 << SHIFT_SMT | FLAG_SMT),
|
||||
PIN_CONFIG_SMT_ENABLE_ALL = (0x2 << SHIFT_SMT | FLAG_SMT),
|
||||
PIN_CONFIG_SMT_DEFAULT = PIN_CONFIG_SMT_DISABLE_IE,
|
||||
#else
|
||||
PIN_CONFIG_SMT_DISABLE = (0x0 << SHIFT_SMT | FLAG_SMT),
|
||||
PIN_CONFIG_SMT_ENABLE = (0x1 << SHIFT_SMT | FLAG_SMT),
|
||||
PIN_CONFIG_SMT_DEFAULT = PIN_CONFIG_SMT_DISABLE,
|
||||
#endif
|
||||
|
||||
PIN_CONFIG_MAX = 0xFFFFFFFFU,
|
||||
} ePINCTRL_configParam;
|
||||
|
||||
typedef enum {
|
||||
GRF_MUX_INFO = 0,
|
||||
GRF_PUL_INFO,
|
||||
GRF_DRV_INFO,
|
||||
GRF_SRT_INFO,
|
||||
GRF_SMT_INFO,
|
||||
GRF_INFO_NUM
|
||||
} ePIN_GRF_INFO_ID;
|
||||
|
||||
#define PIN_BANK_CFG_FLAGS(chn, cnt, reg, \
|
||||
offset0, bpp0, ppr0, \
|
||||
offset1, bpp1, ppr1, \
|
||||
offset2, bpp2, ppr2, \
|
||||
offset3, bpp3, ppr3, \
|
||||
offset4, bpp4, ppr4) \
|
||||
{ \
|
||||
.channel = chn, \
|
||||
.pinCount = cnt, \
|
||||
.grfBase = reg, \
|
||||
.GRFInfo[GRF_MUX_INFO] = { .offset = offset0, .bitsPerPin = bpp0, .pinsPerReg = ppr0 }, \
|
||||
.GRFInfo[GRF_PUL_INFO] = { .offset = offset1, .bitsPerPin = bpp1, .pinsPerReg = ppr1 }, \
|
||||
.GRFInfo[GRF_DRV_INFO] = { .offset = offset2, .bitsPerPin = bpp2, .pinsPerReg = ppr2 }, \
|
||||
.GRFInfo[GRF_SRT_INFO] = { .offset = offset3, .bitsPerPin = bpp3, .pinsPerReg = ppr3 }, \
|
||||
.GRFInfo[GRF_SMT_INFO] = { .offset = offset4, .bitsPerPin = bpp4, .pinsPerReg = ppr4 }, \
|
||||
}
|
||||
|
||||
/** @defgroup ePINCTRL_GPIO_PINS Pins Definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
GPIO_PIN_A0 = 0x00000001U, /*!< Pin 0 selected */
|
||||
GPIO_PIN_A1 = 0x00000002U, /*!< Pin 1 selected */
|
||||
GPIO_PIN_A2 = 0x00000004U, /*!< Pin 2 selected */
|
||||
GPIO_PIN_A3 = 0x00000008U, /*!< Pin 3 selected */
|
||||
GPIO_PIN_A4 = 0x00000010U, /*!< Pin 4 selected */
|
||||
GPIO_PIN_A5 = 0x00000020U, /*!< Pin 5 selected */
|
||||
GPIO_PIN_A6 = 0x00000040U, /*!< Pin 6 selected */
|
||||
GPIO_PIN_A7 = 0x00000080U, /*!< Pin 7 selected */
|
||||
GPIO_PIN_B0 = 0x00000100U, /*!< Pin 8 selected */
|
||||
GPIO_PIN_B1 = 0x00000200U, /*!< Pin 9 selected */
|
||||
GPIO_PIN_B2 = 0x00000400U, /*!< Pin 10 selected */
|
||||
GPIO_PIN_B3 = 0x00000800U, /*!< Pin 11 selected */
|
||||
GPIO_PIN_B4 = 0x00001000U, /*!< Pin 12 selected */
|
||||
GPIO_PIN_B5 = 0x00002000U, /*!< Pin 13 selected */
|
||||
GPIO_PIN_B6 = 0x00004000U, /*!< Pin 14 selected */
|
||||
GPIO_PIN_B7 = 0x00008000U, /*!< Pin 15 selected */
|
||||
GPIO_PIN_C0 = 0x00010000U, /*!< Pin 16 selected */
|
||||
GPIO_PIN_C1 = 0x00020000U, /*!< Pin 17 selected */
|
||||
GPIO_PIN_C2 = 0x00040000U, /*!< Pin 18 selected */
|
||||
GPIO_PIN_C3 = 0x00080000U, /*!< Pin 19 selected */
|
||||
GPIO_PIN_C4 = 0x00100000U, /*!< Pin 20 selected */
|
||||
GPIO_PIN_C5 = 0x00200000U, /*!< Pin 21 selected */
|
||||
GPIO_PIN_C6 = 0x00400000U, /*!< Pin 22 selected */
|
||||
GPIO_PIN_C7 = 0x00800000U, /*!< Pin 23 selected */
|
||||
GPIO_PIN_D0 = 0x01000000U, /*!< Pin 24 selected */
|
||||
GPIO_PIN_D1 = 0x02000000U, /*!< Pin 25 selected */
|
||||
GPIO_PIN_D2 = 0x04000000U, /*!< Pin 26 selected */
|
||||
GPIO_PIN_D3 = 0x08000000U, /*!< Pin 27 selected */
|
||||
GPIO_PIN_D4 = 0x10000000U, /*!< Pin 28 selected */
|
||||
GPIO_PIN_D5 = 0x20000000U, /*!< Pin 29 selected */
|
||||
GPIO_PIN_D6 = 0x40000000U, /*!< Pin 30 selected */
|
||||
GPIO_PIN_D7 = 0x80000000U, /*!< Pin 31 selected */
|
||||
} ePINCTRL_GPIO_PINS;
|
||||
|
||||
#define GPIO_PIN_ALL (0xFFFFFFFFU) /*!< All pins selected */
|
||||
|
||||
/** @} */
|
||||
|
||||
#define ROUTE_VAL(v, s, m) (((v) << (s)) | (m) << ((s) + 16))
|
||||
|
||||
/***************************** Structure Definition **************************/
|
||||
|
||||
struct PINCTRL_GRF_INFO {
|
||||
uint16_t offset;
|
||||
uint8_t bitsPerPin;
|
||||
uint8_t pinsPerReg;
|
||||
};
|
||||
|
||||
struct PINCTRL_MUX_RECAL_DATA {
|
||||
uint32_t reg;
|
||||
uint8_t bank;
|
||||
uint8_t pin;
|
||||
uint8_t bit;
|
||||
uint8_t mask;
|
||||
};
|
||||
|
||||
struct PINCTRL_MUX_ROUTE_DATA {
|
||||
uint32_t routeReg;
|
||||
uint32_t routeVal;
|
||||
uint32_t pin;
|
||||
uint8_t bank;
|
||||
uint8_t func;
|
||||
};
|
||||
|
||||
struct PINCTRL_BANK_INFO {
|
||||
struct PINCTRL_GRF_INFO GRFInfo[GRF_INFO_NUM];
|
||||
uint32_t grfBase;
|
||||
uint8_t pinCount;
|
||||
uint8_t channel;
|
||||
};
|
||||
|
||||
struct HAL_PINCTRL_DEV {
|
||||
const struct PINCTRL_BANK_INFO *banks;
|
||||
const struct PINCTRL_MUX_RECAL_DATA *muxRecalData;
|
||||
const struct PINCTRL_MUX_ROUTE_DATA *muxRouteData;
|
||||
uint8_t banksNum;
|
||||
uint8_t muxRecalDataNum;
|
||||
uint8_t muxRouteDataNum;
|
||||
};
|
||||
|
||||
/** @brief Rockchip pinctrl device struct define
|
||||
* Define a struct for pinctrl, including banks info, bank number,
|
||||
* and grf info about iomux offset, iomux bit info, drive/pull/
|
||||
* slewrate/schmitt offset and bit info.
|
||||
*/
|
||||
extern const struct HAL_PINCTRL_DEV g_pinDev;
|
||||
|
||||
/** @} */
|
||||
|
||||
/***************************** Function Declare ******************************/
|
||||
/** @defgroup PINCTRL_Public_Function_Declare Public Function Declare
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_Status HAL_PINCTRL_Suspend(void);
|
||||
HAL_Status HAL_PINCTRL_Resume(void);
|
||||
|
||||
HAL_Status HAL_PINCTRL_Init(void);
|
||||
HAL_Status HAL_PINCTRL_DeInit(void);
|
||||
|
||||
HAL_Status HAL_PINCTRL_SetParam(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param);
|
||||
HAL_Status HAL_PINCTRL_SetIOMUX(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param);
|
||||
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForCIF(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForEMMC(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForFLASH(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForFSPI(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForLCDC(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForMIPICSI(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForRGMII(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForGMAC0(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForGMAC1(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForSDIO(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForSDMMC0(eIOFUNC_SEL mode);
|
||||
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForCAN0(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForCAN1(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForCAN2(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForCAN3(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForCAN4(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForCAN5(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForI2C0(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForI2C1(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForI2C2(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForI2C3(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForI2C4(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForI2C5(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForI2S0(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForI2S1(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForI2S2(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForPWM0(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForPWM1(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForPWM2(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForPWM3(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForPWM4(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForPWM5(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForPWM6(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForPWM7(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForPWM8(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForPWM9(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForPWM10(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForPWM11(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForSPI0(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForSPI1(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForSPI2(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForSPI3(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForSPI4(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForSPI5(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForUART0(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForUART1(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForUART2(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForUART3(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForUART4(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForUART5(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForUART6(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForUART7(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForUART8(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForUART9(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForUART10(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForUART11(eIOFUNC_SEL mode);
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* __HAL_PINCTRL_H__ */
|
||||
|
||||
/** @} */
|
||||
|
||||
/** @} */
|
||||
@@ -0,0 +1,200 @@
|
||||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#include "hal_conf.h"
|
||||
|
||||
/** @addtogroup RK_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PM
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _HAL_PM_H_
|
||||
#define _HAL_PM_H_
|
||||
|
||||
#include "hal_def.h"
|
||||
|
||||
/***************************** MACRO Definition ******************************/
|
||||
/** @defgroup DEMO_Exported_Definition_Group1 Basic Definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PM_RUNTIME_TYPE_MUTI_SFT (3)
|
||||
#define PM_RUNTIME_PER_TYPE_NUM (8)
|
||||
|
||||
#define PM_RUNTIME_TYPE_TO_FIRST_ID(type) ((type) << PM_RUNTIME_TYPE_MUTI_SFT)
|
||||
#define PM_RUNTIME_ID_TO_TYPE(id) ((id) >> PM_RUNTIME_TYPE_MUTI_SFT)
|
||||
#define PM_RUNTIME_ID_TO_TYPE_OFFSET(id) ((id) % PM_RUNTIME_PER_TYPE_NUM)
|
||||
#define PM_RUNTIME_ID_TYPE_BIT_MSK(id) HAL_BIT(((id) % PM_RUNTIME_PER_TYPE_NUM))
|
||||
|
||||
#define PM_DISPLAY_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_DISPLAY])
|
||||
#define PM_UART_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_UART])
|
||||
#define PM_I2C_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_I2C])
|
||||
#define PM_INTF_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_INTF])
|
||||
#define PM_HS_INTF_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_HS_INTF])
|
||||
#define PM_SPI_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_SPI])
|
||||
#define PM_CIF_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_CIF])
|
||||
|
||||
/* suspend config id */
|
||||
#define PM_SLEEP_MODE_CONFIG 0x01
|
||||
#define PM_SLEEP_WAKEUP_SOURCE 0x02
|
||||
|
||||
enum {
|
||||
PM_RUNTIME_TYPE_INTF = 0, /**< normal interface */
|
||||
PM_RUNTIME_TYPE_DISPLAY,
|
||||
PM_RUNTIME_TYPE_AUDIO,
|
||||
PM_RUNTIME_TYPE_HS_INTF, /**< high speed interface */
|
||||
PM_RUNTIME_TYPE_STORAGE,
|
||||
PM_RUNTIME_TYPE_UART,
|
||||
PM_RUNTIME_TYPE_I2C,
|
||||
PM_RUNTIME_TYPE_SPI,
|
||||
PM_RUNTIME_TYPE_CIF,
|
||||
PM_RUNTIME_TYPE_DEVICE,
|
||||
PM_RUNTIME_TYPE_END,
|
||||
};
|
||||
|
||||
typedef enum {
|
||||
PM_RUNTIME_IDLE_ONLY = 0,
|
||||
PM_RUNTIME_IDLE_NORMAL,
|
||||
PM_RUNTIME_IDLE_DEEP,
|
||||
PM_RUNTIME_IDLE_DEEP1,
|
||||
PM_RUNTIME_IDLE_DEEP2,
|
||||
} ePM_RUNTIME_idleMode;
|
||||
|
||||
typedef enum {
|
||||
PM_RUNTIME_ID_INTF_INVLD = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_INTF), /**< the id = 0, is means invalid */
|
||||
PM_RUNTIME_ID_SPI_APB,
|
||||
PM_RUNTIME_ID_VOP = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_DISPLAY),
|
||||
PM_RUNTIME_ID_MIPI,
|
||||
|
||||
PM_RUNTIME_ID_I2S = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_AUDIO),
|
||||
PM_RUNTIME_ID_I2S1,
|
||||
PM_RUNTIME_ID_I2S2,
|
||||
PM_RUNTIME_ID_ADC,
|
||||
PM_RUNTIME_ID_DMA,
|
||||
|
||||
PM_RUNTIME_ID_USB = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_HS_INTF),
|
||||
PM_RUNTIME_ID_SDIO,
|
||||
|
||||
PM_RUNTIME_ID_UART0 = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_UART),
|
||||
PM_RUNTIME_ID_UART1,
|
||||
PM_RUNTIME_ID_UART2,
|
||||
PM_RUNTIME_ID_UART3,
|
||||
PM_RUNTIME_ID_UART4,
|
||||
PM_RUNTIME_ID_UART5,
|
||||
PM_RUNTIME_ID_UART6,
|
||||
PM_RUNTIME_ID_UART7,
|
||||
PM_RUNTIME_ID_UART8,
|
||||
PM_RUNTIME_ID_UART9,
|
||||
|
||||
PM_RUNTIME_ID_I2C0 = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_I2C),
|
||||
PM_RUNTIME_ID_I2C1,
|
||||
PM_RUNTIME_ID_I2C2,
|
||||
PM_RUNTIME_ID_I2C3,
|
||||
PM_RUNTIME_ID_I2C4,
|
||||
PM_RUNTIME_ID_I2C5,
|
||||
|
||||
PM_RUNTIME_ID_SPI = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_SPI),
|
||||
PM_RUNTIME_ID_CIF = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_CIF),
|
||||
|
||||
PM_RUNTIME_ID_END,
|
||||
} ePM_RUNTIME_ID;
|
||||
|
||||
/***************************** Structure Definition **************************/
|
||||
struct PM_RUNTIME_INFO {
|
||||
uint8_t bits[PM_RUNTIME_TYPE_END];
|
||||
};
|
||||
|
||||
#ifdef HAL_PM_SLEEP_MODULE_ENABLED
|
||||
struct PM_SUSPEND_INFO {
|
||||
union {
|
||||
struct {
|
||||
uint32_t uartChannel : 4; /*!< bit: 0.. 3 uart debug channel num */
|
||||
uint32_t uartValid : 1; /*!< bit: 4 uart channel valid flag */
|
||||
uint32_t _reserved : 27; /*!< bit: 5..31 Reserved */
|
||||
} flag;
|
||||
uint32_t suspendFlag;
|
||||
};
|
||||
};
|
||||
|
||||
struct SLEEP_CONFIG_DATA {
|
||||
uint32_t suspendMode;
|
||||
uint32_t suspendWkupSrc;
|
||||
};
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
/***************************** Function Declare ******************************/
|
||||
/** @defgroup PM_Public_Function_Declare Public Function Declare
|
||||
* @{
|
||||
*/
|
||||
#ifdef HAL_PM_SLEEP_MODULE_ENABLED
|
||||
/**
|
||||
* @brief it is the enterpoint for suspend invoked by a os's powermanager implement.
|
||||
* @param suspendInfo: suspend information for controlling
|
||||
* @return HAL_Status
|
||||
*/
|
||||
int HAL_SYS_Suspend(struct PM_SUSPEND_INFO *suspendInfo);
|
||||
struct SLEEP_CONFIG_DATA *HAL_SYS_GetSuspendConfig(void);
|
||||
HAL_Status HAL_SYS_SuspendConfig(uint32_t id, uint32_t data);
|
||||
#endif
|
||||
|
||||
#ifdef HAL_PM_CPU_SLEEP_MODULE_ENABLED
|
||||
void HAL_CPU_ArchSuspend(uint32_t *ptr);
|
||||
void HAL_CPU_ArchResume(void);
|
||||
void HAL_CPU_DoResume(void);
|
||||
|
||||
void HAL_NVIC_SuspendSave(void);
|
||||
void HAL_NVIC_ResumeRestore(void);
|
||||
|
||||
void HAL_SCB_SuspendSave(void);
|
||||
void HAL_SCB_ResumeRestore(void);
|
||||
|
||||
int HAL_CPU_SuspendEnter(uint32_t flag, int (*suspend)(uint32_t));
|
||||
void HAL_CPU_SuspendSave(uint32_t *ptr, uint32_t ptrsz, uint32_t sp, uint32_t *ptrSave);
|
||||
#endif
|
||||
|
||||
#ifdef HAL_PM_RUNTIME_MODULE_ENABLED
|
||||
HAL_Status HAL_PM_RuntimeRequest(ePM_RUNTIME_ID runtimeId);
|
||||
HAL_Status HAL_PM_RuntimeRelease(ePM_RUNTIME_ID runtimeId);
|
||||
const struct PM_RUNTIME_INFO *HAL_PM_RuntimeGetData(void);
|
||||
|
||||
/**
|
||||
* @brief it is for runtime power manager.
|
||||
* @param idleMode: the soc pm mode will be config
|
||||
* @return the mask bits indicate request source.
|
||||
*/
|
||||
uint32_t HAL_PM_RuntimeEnter(ePM_RUNTIME_idleMode idleMode);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief it is for statting a pm timer .
|
||||
* @param timeoutCount: the next timeout count
|
||||
* @param needTimeout: if ture, need to start a timer.
|
||||
* @return HAL_Status.
|
||||
*/
|
||||
HAL_Status HAL_PM_TimerStart(uint64_t timeoutCount, bool needTimeout);
|
||||
|
||||
/**
|
||||
* @brief it is for stopping a pm timer .
|
||||
* @return HAL_Status.
|
||||
*/
|
||||
HAL_Status HAL_PM_TimerStop(void);
|
||||
|
||||
/**
|
||||
* @brief it is for getting the sleep time.
|
||||
* @return the sleep time.
|
||||
*/
|
||||
uint64_t HAL_PM_GetTimerCount(void);
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/** @} */
|
||||
@@ -0,0 +1,64 @@
|
||||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#include "hal_conf.h"
|
||||
|
||||
#ifdef HAL_TIMER_MODULE_ENABLED
|
||||
|
||||
/** @addtogroup RK_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMER
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _HAL_TIMER_H_
|
||||
#define _HAL_TIMER_H_
|
||||
|
||||
#include "hal_def.h"
|
||||
|
||||
/***************************** MACRO Definition ******************************/
|
||||
|
||||
/** @defgroup TIMER_Exported_Definition_Group1 Basic Definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum {
|
||||
TIMER_FREE_RUNNING = 0,
|
||||
TIMER_USER_DEFINED,
|
||||
TIMER_MODE_MAX
|
||||
} eTIMER_MODE;
|
||||
|
||||
/***************************** Structure Definition **************************/
|
||||
|
||||
/** @} */
|
||||
/***************************** Function Declare ******************************/
|
||||
/** @defgroup TIMER_Public_Function_Declare Public Function Declare
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_Status HAL_TIMER_Stop(struct TIMER_REG *pReg);
|
||||
HAL_Status HAL_TIMER_Start(struct TIMER_REG *pReg);
|
||||
HAL_Status HAL_TIMER_Stop_IT(struct TIMER_REG *pReg);
|
||||
HAL_Status HAL_TIMER_Start_IT(struct TIMER_REG *pReg);
|
||||
HAL_Status HAL_TIMER_SetCount(struct TIMER_REG *pReg, uint64_t usTick);
|
||||
uint64_t HAL_TIMER_GetCount(struct TIMER_REG *pReg);
|
||||
HAL_Status HAL_TIMER0_Handler(void);
|
||||
HAL_Status HAL_TIMER1_Handler(void);
|
||||
HAL_Status HAL_TIMER_Init(struct TIMER_REG *pReg, eTIMER_MODE mode);
|
||||
HAL_Status HAL_TIMER_SysTimerInit(struct TIMER_REG *pReg);
|
||||
HAL_Status HAL_TIMER_DeInit(struct TIMER_REG *pReg);
|
||||
HAL_Status HAL_TIMER_ClrInt(struct TIMER_REG *pReg);
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* HAL_TIMER_MODULE_ENABLED */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,444 @@
|
||||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#ifndef __SOC_H
|
||||
#define __SOC_H
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "hal_conf.h"
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< brief Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< brief Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< brief Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< brief Defines 'read / write' permissions */
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ DMA REQ =============== */
|
||||
/* ================================================================================ */
|
||||
typedef enum {
|
||||
DMA_REQ_UART0_TX = 0,
|
||||
DMA_REQ_UART0_RX = 1,
|
||||
DMA_REQ_UART1_TX = 2,
|
||||
DMA_REQ_UART1_RX = 3,
|
||||
DMA_REQ_UART2_TX = 4,
|
||||
DMA_REQ_UART2_RX = 5,
|
||||
DMA_REQ_UART3_TX = 6,
|
||||
DMA_REQ_UART3_RX = 7,
|
||||
DMA_REQ_UART4_TX = 8,
|
||||
DMA_REQ_UART4_RX = 9,
|
||||
DMA_REQ_UART5_TX = 10,
|
||||
DMA_REQ_UART5_RX = 11,
|
||||
DMA_REQ_UART6_TX = 12,
|
||||
DMA_REQ_UART6_RX = 13,
|
||||
DMA_REQ_UART7_TX = 14,
|
||||
DMA_REQ_UART7_RX = 15,
|
||||
DMA_REQ_UART8_TX = 16,
|
||||
DMA_REQ_UART8_RX = 17,
|
||||
DMA_REQ_UART9_TX = 18,
|
||||
DMA_REQ_UART9_RX = 19,
|
||||
DMA_REQ_SPI0_TX = 20,
|
||||
DMA_REQ_SPI0_RX = 21,
|
||||
DMA_REQ_SPI1_TX = 22,
|
||||
DMA_REQ_SPI1_RX = 23,
|
||||
DMA_REQ_SPI2_TX = 24,
|
||||
DMA_REQ_SPI2_RX = 25,
|
||||
DMA_REQ_SPI3_TX = 26,
|
||||
DMA_REQ_SPI3_RX = 27,
|
||||
} DMA_REQ_Type;
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ IRQ ================ */
|
||||
/* ================================================================================ */
|
||||
#ifdef HAL_MCU_CORE
|
||||
#define INTMUX_IRQ_START_NUM 32
|
||||
#define INTMUX_OUT_IRQ_START_NUM 0
|
||||
#define INTMUX_NUM_INT_PER_OUT 64
|
||||
#define INTMUX_NUM_GROUP_PER_CON 8
|
||||
#define INTMUX_NUM_GROUP_PER_OUT 8
|
||||
#define INTMUX_NUM_INT_PER_GROUP 8
|
||||
#define NUM_EXT_INTERRUPTS 320
|
||||
|
||||
typedef enum
|
||||
{
|
||||
/****** Platform Exceptions Numbers ***************************************************/
|
||||
NUM_INTERRUPTS = 0,
|
||||
DMAC0_ABORT_IRQn = 45, /*!< DMAC0 Abort Interrupt */
|
||||
DMAC0_IRQn = 46, /*!< DMAC0 Interrupt */
|
||||
DMAC1_ABORT_IRQn = 47, /*!< DMAC1 Abort Interrupt */
|
||||
DMAC1_IRQn = 48, /*!< DMAC1 Interrupt */
|
||||
GPIO0_IRQn = 65, /*!< GPIO0 Interrupt */
|
||||
GPIO1_IRQn = 66, /*!< GPIO1 Interrupt */
|
||||
GPIO2_IRQn = 67, /*!< GPIO2 Interrupt */
|
||||
GPIO3_IRQn = 68, /*!< GPIO3 Interrupt */
|
||||
GPIO4_IRQn = 69, /*!< GPIO4 Interrupt */
|
||||
I2C0_IRQn = 78, /*!< I2C0 Interrupt */
|
||||
I2C1_IRQn = 79, /*!< I2C1 Interrupt */
|
||||
I2C2_IRQn = 80, /*!< I2C2 Interrupt */
|
||||
I2C3_IRQn = 81, /*!< I2C3 Interrupt */
|
||||
I2C4_IRQn = 82, /*!< I2C4 Interrupt */
|
||||
I2C5_IRQn = 83, /*!< I2C5 Interrupt */
|
||||
PWM_PMU_IRQn = 114, /*!< PWM_PMU Interrupt */
|
||||
PWM1_IRQn = 115, /*!< PWM1 Interrupt */
|
||||
PWM2_IRQn = 116, /*!< PWM2 Interrupt */
|
||||
PWM3_IRQn = 117, /*!< PWM3 Interrupt */
|
||||
PWM_PMU_PWR_IRQn = 118, /*!< PWM_PMU PWR Interrupt */
|
||||
PWM1_PWR_IRQn = 119, /*!< PWM1 PWR Interrupt */
|
||||
PWM2_PWR_IRQn = 120, /*!< PWM2 PWR Interrupt */
|
||||
PWM3_PWR_IRQn = 121, /*!< PWM3 PWR Interrupt */
|
||||
SARADC_IRQn = 125, /*!< SARADC Interrupt */
|
||||
FSPI0_IRQn = 133, /*!< FSPI Interrupt */
|
||||
SPI0_IRQn = 135, /*!< SPI0 Interrupt */
|
||||
SPI1_IRQn = 136, /*!< SPI1 Interrupt */
|
||||
SPI2_IRQn = 137, /*!< SPI2 Interrupt */
|
||||
SPI3_IRQn = 138, /*!< SPI3 Interrupt */
|
||||
TIMER0_IRQn = 141, /*!< TIMER0 Interrupt */
|
||||
TIMER1_IRQn = 142, /*!< TIMER1 Interrupt */
|
||||
TIMER2_IRQn = 143, /*!< TIMER2 Interrupt */
|
||||
TIMER3_IRQn = 144, /*!< TIMER3 Interrupt */
|
||||
TIMER4_IRQn = 145, /*!< TIMER4 Interrupt */
|
||||
TIMER5_IRQn = 146, /*!< TIMER5 Interrupt */
|
||||
UART0_IRQn = 148, /*!< UART0 Interrupt */
|
||||
UART1_IRQn = 149, /*!< UART1 Interrupt */
|
||||
UART2_IRQn = 150, /*!< UART2 Interrupt */
|
||||
UART3_IRQn = 151, /*!< UART3 Interrupt */
|
||||
UART4_IRQn = 152, /*!< UART4 Interrupt */
|
||||
UART5_IRQn = 153, /*!< UART5 Interrupt */
|
||||
UART6_IRQn = 154, /*!< UART6 Interrupt */
|
||||
UART7_IRQn = 155, /*!< UART7 Interrupt */
|
||||
UART8_IRQn = 156, /*!< UART8 Interrupt */
|
||||
UART9_IRQn = 157, /*!< UART9 Interrupt */
|
||||
WDT0_IRQn = 181, /*!< WDT0 Interrupt */
|
||||
MBOX0_CH0_B2A_IRQn = 215, /*!< MBOX0 CH0 B2A Interrupt */
|
||||
MBOX0_CH1_B2A_IRQn = 216, /*!< MBOX0 CH1 B2A Interrupt */
|
||||
MBOX0_CH2_B2A_IRQn = 217, /*!< MBOX0 CH2 B2A Interrupt */
|
||||
MBOX0_CH3_B2A_IRQn = 218, /*!< MBOX0 CH3 B2A Interrupt */
|
||||
MBOX0_CH0_A2B_IRQn = 219, /*!< MBOX0 CH0 A2B Interrupt */
|
||||
MBOX0_CH1_A2B_IRQn = 220, /*!< MBOX0 CH1 A2B Interrupt */
|
||||
MBOX0_CH2_A2B_IRQn = 221, /*!< MBOX0 CH2 A2B Interrupt */
|
||||
MBOX0_CH3_A2B_IRQn = 222, /*!< MBOX0 CH3 A2B Interrupt */
|
||||
TOTAL_INTERRUPTS = (INTMUX_IRQ_START_NUM + NUM_INTERRUPTS + NUM_EXT_INTERRUPTS),
|
||||
} IRQn_Type;
|
||||
#else
|
||||
typedef enum
|
||||
{
|
||||
/* When IPI_SGIs are used in AMP mode, you need to pay attention to whether it conflicts
|
||||
* with SMP mode. Especially in the case of Linux OS as The Master Core.
|
||||
* IPI_SGI 0~7 for non-secure and IPI_SGI 8~15 for secure.
|
||||
*/
|
||||
IPI_SGI0 = 0,
|
||||
IPI_SGI1 = 1,
|
||||
IPI_SGI2 = 2,
|
||||
IPI_SGI3 = 3,
|
||||
IPI_SGI4 = 4,
|
||||
IPI_SGI5 = 5,
|
||||
IPI_SGI6 = 6,
|
||||
IPI_SGI7 = 7,
|
||||
IPI_SGI8 = 8,
|
||||
IPI_SGI9 = 9,
|
||||
IPI_SGI10 = 10,
|
||||
IPI_SGI11 = 11,
|
||||
IPI_SGI12 = 12,
|
||||
IPI_SGI13 = 13,
|
||||
IPI_SGI14 = 14,
|
||||
IPI_SGI15 = 15,
|
||||
|
||||
CNTHP_IRQn = 26,
|
||||
CNTV_IRQn = 27,
|
||||
CNTPS_IRQn = 29,
|
||||
CNTPNS_IRQn = 30,
|
||||
|
||||
/****** Platform Exceptions Numbers ***************************************************/
|
||||
CAN0_IRQn = 33, /*!< CAN0 Interrupt */
|
||||
CAN1_IRQn = 34, /*!< CAN1 Interrupt */
|
||||
CAN2_IRQn = 35, /*!< CAN2 Interrupt */
|
||||
DMAC0_ABORT_IRQn = 45, /*!< DMAC0 Abort Interrupt */
|
||||
DMAC0_IRQn = 46, /*!< DMAC0 Interrupt */
|
||||
DMAC1_ABORT_IRQn = 47, /*!< DMAC1 Abort Interrupt */
|
||||
DMAC1_IRQn = 48, /*!< DMAC1 Interrupt */
|
||||
GMAC0_IRQn = 59, /*!< GMAC0 Interrupt */
|
||||
GMAC1_IRQn = 64, /*!< GMAC1 Interrupt */
|
||||
GPIO0_IRQn = 65, /*!< GPIO0 Interrupt */
|
||||
GPIO1_IRQn = 66, /*!< GPIO1 Interrupt */
|
||||
GPIO2_IRQn = 67, /*!< GPIO2 Interrupt */
|
||||
GPIO3_IRQn = 68, /*!< GPIO3 Interrupt */
|
||||
GPIO4_IRQn = 69, /*!< GPIO4 Interrupt */
|
||||
I2C0_IRQn = 78, /*!< I2C0 Interrupt */
|
||||
I2C1_IRQn = 79, /*!< I2C1 Interrupt */
|
||||
I2C2_IRQn = 80, /*!< I2C2 Interrupt */
|
||||
I2C3_IRQn = 81, /*!< I2C3 Interrupt */
|
||||
I2C4_IRQn = 82, /*!< I2C4 Interrupt */
|
||||
I2C5_IRQn = 83, /*!< I2C5 Interrupt */
|
||||
PWM_PMU_IRQn = 114, /*!< PWM_PMU Interrupt */
|
||||
PWM1_IRQn = 115, /*!< PWM1 Interrupt */
|
||||
PWM2_IRQn = 116, /*!< PWM2 Interrupt */
|
||||
PWM3_IRQn = 117, /*!< PWM3 Interrupt */
|
||||
PWM_PMU_PWR_IRQn = 118, /*!< PWM_PMU PWR Interrupt */
|
||||
PWM1_PWR_IRQn = 119, /*!< PWM1 PWR Interrupt */
|
||||
PWM2_PWR_IRQn = 120, /*!< PWM2 PWR Interrupt */
|
||||
PWM3_PWR_IRQn = 121, /*!< PWM3 PWR Interrupt */
|
||||
SARADC_IRQn = 125, /*!< SARADC Interrupt */
|
||||
FSPI0_IRQn = 133, /*!< FSPI Interrupt */
|
||||
SPI0_IRQn = 135, /*!< SPI0 Interrupt */
|
||||
SPI1_IRQn = 136, /*!< SPI1 Interrupt */
|
||||
SPI2_IRQn = 137, /*!< SPI2 Interrupt */
|
||||
SPI3_IRQn = 138, /*!< SPI3 Interrupt */
|
||||
TIMER0_IRQn = 141, /*!< TIMER0 Interrupt */
|
||||
TIMER1_IRQn = 142, /*!< TIMER1 Interrupt */
|
||||
TIMER2_IRQn = 143, /*!< TIMER2 Interrupt */
|
||||
TIMER3_IRQn = 144, /*!< TIMER3 Interrupt */
|
||||
TIMER4_IRQn = 145, /*!< TIMER4 Interrupt */
|
||||
TIMER5_IRQn = 146, /*!< TIMER5 Interrupt */
|
||||
UART0_IRQn = 148, /*!< UART0 Interrupt */
|
||||
UART1_IRQn = 149, /*!< UART1 Interrupt */
|
||||
UART2_IRQn = 150, /*!< UART2 Interrupt */
|
||||
UART3_IRQn = 151, /*!< UART3 Interrupt */
|
||||
UART4_IRQn = 152, /*!< UART4 Interrupt */
|
||||
UART5_IRQn = 153, /*!< UART5 Interrupt */
|
||||
UART6_IRQn = 154, /*!< UART6 Interrupt */
|
||||
UART7_IRQn = 155, /*!< UART7 Interrupt */
|
||||
UART8_IRQn = 156, /*!< UART8 Interrupt */
|
||||
UART9_IRQn = 157, /*!< UART9 Interrupt */
|
||||
WDT0_IRQn = 181, /*!< WDT0 Interrupt */
|
||||
PCIE30x2_LEGACY_IRQn = 194, /*!< PCIe3x2_legacy Interrupt */
|
||||
DDR_ECC_CE_IRQn = 205, /*!< DDR ECC correctable fault Interrupt */
|
||||
DDR_ECC_UE_IRQn = 207, /*!< DDR ECC uncorrectable fault Interrupt */
|
||||
MBOX0_CH0_B2A_IRQn = 215, /*!< MBOX0 CH0 B2A Interrupt */
|
||||
MBOX0_CH1_B2A_IRQn = 216, /*!< MBOX0 CH1 B2A Interrupt */
|
||||
MBOX0_CH2_B2A_IRQn = 217, /*!< MBOX0 CH2 B2A Interrupt */
|
||||
MBOX0_CH3_B2A_IRQn = 218, /*!< MBOX0 CH3 B2A Interrupt */
|
||||
MBOX0_CH0_A2B_IRQn = 219, /*!< MBOX0 CH0 A2B Interrupt */
|
||||
MBOX0_CH1_A2B_IRQn = 220, /*!< MBOX0 CH1 A2B Interrupt */
|
||||
MBOX0_CH2_A2B_IRQn = 221, /*!< MBOX0 CH2 A2B Interrupt */
|
||||
MBOX0_CH3_A2B_IRQn = 222, /*!< MBOX0 CH3 A2B Interrupt */
|
||||
NFAULT0_IRQn = 272, /*!< DSU L3 CACHE ECC FAULT Interrupt */
|
||||
NFAULT1_IRQn = 273, /*!< CPU0 L1-L2 CACHE ECC FAULT Interrupt */
|
||||
NFAULT2_IRQn = 274, /*!< CPU1 L1-L2 CACHE ECC FAULT Interrupt */
|
||||
NFAULT3_IRQn = 275, /*!< CPU2 L1-L2 CACHE ECC FAULT Interrupt */
|
||||
NFAULT4_IRQn = 276, /*!< CPU3 L1-L2 CACHE ECC FAULT Interrupt */
|
||||
NERR0_IRQn = 277, /*!< DSU L3 CACHE ECC ERROR Interrupt */
|
||||
NERR1_IRQn = 278, /*!< CPU0 L1-L2 CACHE ECC ERROR Interrupt */
|
||||
NERR2_IRQn = 279, /*!< CPU1 L1-L2 CACHE ECC ERROR Interrupt */
|
||||
NERR3_IRQn = 280, /*!< CPU2 L1-L2 CACHE ECC ERROR Interrupt */
|
||||
NERR4_IRQn = 281, /*!< CPU3 L1-L2 CACHE ECC ERROR Interrupt */
|
||||
RSVD0_IRQn = 283, /*!< RSVD0 Interrupt */
|
||||
RPMSG_01_IRQn = 285, /*!< RPMSG 0->1 Interrupt */
|
||||
RPMSG_02_IRQn = 286, /*!< RPMSG 0->2 Interrupt */
|
||||
RPMSG_03_IRQn = 287, /*!< RPMSG 0->3 Interrupt */
|
||||
RPMSG_10_IRQn = 288, /*!< RPMSG 1->0 Interrupt */
|
||||
RPMSG_12_IRQn = 289, /*!< RPMSG 1->2 Interrupt */
|
||||
RPMSG_13_IRQn = 290, /*!< RPMSG 1->3 Interrupt */
|
||||
RPMSG_20_IRQn = 291, /*!< RPMSG 2->0 Interrupt */
|
||||
RPMSG_21_IRQn = 292, /*!< RPMSG 2->1 Interrupt */
|
||||
RPMSG_23_IRQn = 293, /*!< RPMSG 2->3 Interrupt */
|
||||
RPMSG_30_IRQn = 294, /*!< RPMSG 3->0 Interrupt */
|
||||
RPMSG_31_IRQn = 295, /*!< RPMSG 3->1 Interrupt */
|
||||
RPMSG_32_IRQn = 296, /*!< RPMSG 3->2 Interrupt */
|
||||
NUM_INTERRUPTS = 352,
|
||||
} IRQn_Type;
|
||||
#endif
|
||||
|
||||
#define RSVD_IRQn(_N) (RSVD0_IRQn + (_N))
|
||||
|
||||
#define AMP_CPUOFF_REQ_IRQ(cpu) RSVD_IRQn(11 + (cpu)) /* gic irq: 294 */
|
||||
#define GIC_TOUCH_REQ_IRQ(cpu) (AMP_CPUOFF_REQ_IRQ(4) + cpu) /* gic irq: 298 */
|
||||
|
||||
#define GPIO_IRQ_GROUP_DIRQ_BASE RSVD_IRQn(37) /* gic irq: 320 */
|
||||
#define GPIO_IRQ_GROUP_DIRQ_NUM (NUM_INTERRUPTS - GPIO_IRQ_GROUP_DIRQ_BASE)
|
||||
|
||||
#define GPIO_IRQ_GROUP_GPIO0_HWIRQ GPIO0_IRQn
|
||||
#define GPIO_IRQ_GROUP_GPION_HWIRQ GPIO4_IRQn
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ Processor and Core Peripheral Section ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
#if defined(HAL_AP_CORE) && defined(HAL_MCU_CORE)
|
||||
#error "HAL_AP_CORE and HAL_MCU_CORE only one of them can be enabled"
|
||||
#endif
|
||||
|
||||
#if !defined(HAL_AP_CORE) && !defined(HAL_MCU_CORE)
|
||||
#error "Please define HAL_AP_CORE or HAL_MCU_CORE on hal_conf.h"
|
||||
#endif
|
||||
|
||||
#ifdef HAL_AP_CORE
|
||||
#define __CORTEX_A 55U /* Cortex-A55 Core */
|
||||
#define __FPU_PRESENT 1U /* FPU present */
|
||||
#define __TIM_PRESENT 1U /* Generic Timer */
|
||||
|
||||
#define CACHE_LINE_SHIFT (6U)
|
||||
#define CACHE_LINE_SIZE (0x1U << CACHE_LINE_SHIFT)
|
||||
|
||||
#else
|
||||
#define __RISC_V
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
// #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||
// #ifdef __CORTEX_A
|
||||
// #include "core_ca.h"
|
||||
// #endif
|
||||
#include "system_rk3568.h"
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#include "rk3568.h"
|
||||
|
||||
/****************************************************************************************/
|
||||
/* */
|
||||
/* Module Address Section */
|
||||
/* */
|
||||
/****************************************************************************************/
|
||||
/* Memory Base */
|
||||
#define PCIE3X2_DBI_BASE 0xF6000000 /* PCIe dbi base address */
|
||||
#define GIC_DISTRIBUTOR_BASE 0xFD400000 /* GICD base address */
|
||||
#define GIC_REDISTRIBUTOR_BASE 0xFD460000 /* GICR base address */
|
||||
#define PCIE3PHY_GRF_BASE 0xFDCB8000 /* S-PHY_GRF base address */
|
||||
#define PCIE3X2_APB_BASE 0xFE280000 /* PCIe apb base address */
|
||||
|
||||
/****************************************************************************************/
|
||||
/* */
|
||||
/* Register Bitmap Section */
|
||||
/* */
|
||||
/****************************************************************************************/
|
||||
/********************************** CPU Topology ****************************************/
|
||||
#define MPIDR_MT_MASK ((1U) << 24)
|
||||
#define MPIDR_AFFLVL_MASK (0xFFU)
|
||||
#define MPIDR_AFF0_SHIFT (0U)
|
||||
#define MPIDR_AFF1_SHIFT (8U)
|
||||
#define MPIDR_AFF2_SHIFT (16U)
|
||||
#define MPIDR_AFF3_SHIFT (32U)
|
||||
#define MPIDR_AFFINITY_MASK (0xFFFFFFU)
|
||||
#define PLATFORM_CLUSTER0_CORE_COUNT (4)
|
||||
#define PLATFORM_CLUSTER1_CORE_COUNT (0)
|
||||
#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT
|
||||
#define CPU_GET_AFFINITY(cpuId, clusterId) ((cpuId) << MPIDR_AFF1_SHIFT)
|
||||
|
||||
/********************************** CACHE ECC ****************************************/
|
||||
#ifndef __ASSEMBLY__
|
||||
/** @addtogroup CACHE_ECC_Exported_Definition_Group1
|
||||
* @{
|
||||
*/
|
||||
/** the fault value will be injected */
|
||||
typedef enum {
|
||||
CACHE_ECC_INJECT_UC = 0x80000002, /**< Uncontainable Error generation */
|
||||
CACHE_ECC_INJECT_DE_UER = 0x8000000a, /**< for l1~l2, generate a exception */
|
||||
} eCACHE_ECC_InjectFault;
|
||||
/** @} */
|
||||
#endif
|
||||
/******************************************CRU*******************************************/
|
||||
#define PLL_INPUT_OSC_RATE (24 * 1000 * 1000)
|
||||
|
||||
#define CRU_SRST_CON_CNT 29
|
||||
#define CRU_GATE_CON_CNT 35
|
||||
#define CRU_CLK_DIV_CON_CNT 84
|
||||
#define CRU_CLK_SEL_CON_CNT 84
|
||||
|
||||
#define CLK(mux, div) \
|
||||
(((mux) & 0x0F0F00FFU) | (((div) & 0xFFU) << 8) | (((div) & 0x0F0F0000U) << 4))
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
typedef enum CLOCK_Name {
|
||||
CLK_INVALID = 0U,
|
||||
PLL_APLL,
|
||||
PLL_CPLL,
|
||||
PLL_GPLL,
|
||||
PLL_NPLL,
|
||||
PLL_VPLL,
|
||||
PLL_PPLL,
|
||||
PLL_HPLL,
|
||||
CLK_WDT,
|
||||
CLK_UART0,
|
||||
CLK_I2C = CLK(CLK_I2C_SEL, 0U),
|
||||
CLK_PWM1 = CLK(CLK_PWM1_SEL, 0U),
|
||||
CLK_PWM2 = CLK(CLK_PWM2_SEL, 0U),
|
||||
CLK_PWM3 = CLK(CLK_PWM3_SEL, 0U),
|
||||
CLK_SPI0 = CLK(CLK_SPI0_SEL, 0U),
|
||||
CLK_SPI1 = CLK(CLK_SPI1_SEL, 0U),
|
||||
CLK_SPI2 = CLK(CLK_SPI2_SEL, 0U),
|
||||
CLK_SPI3 = CLK(CLK_SPI3_SEL, 0U),
|
||||
CLK_UART1_SRC = CLK(CLK_UART1_SRC_SEL, CLK_UART1_SRC_DIV),
|
||||
CLK_UART1_FRAC = CLK(0U, CLK_UART1_FRAC_DIV),
|
||||
CLK_UART1 = CLK(SCLK_UART1_SEL, 0U),
|
||||
CLK_UART2_SRC = CLK(CLK_UART2_SRC_SEL, CLK_UART2_SRC_DIV),
|
||||
CLK_UART2_FRAC = CLK(0U, CLK_UART2_FRAC_DIV),
|
||||
CLK_UART2 = CLK(SCLK_UART2_SEL, 0U),
|
||||
CLK_UART3_SRC = CLK(CLK_UART3_SRC_SEL, CLK_UART3_SRC_DIV),
|
||||
CLK_UART3_FRAC = CLK(0U, CLK_UART3_FRAC_DIV),
|
||||
CLK_UART3 = CLK(SCLK_UART3_SEL, 0U),
|
||||
CLK_UART4_SRC = CLK(CLK_UART4_SRC_SEL, CLK_UART4_SRC_DIV),
|
||||
CLK_UART4_FRAC = CLK(0U, CLK_UART4_FRAC_DIV),
|
||||
CLK_UART4 = CLK(SCLK_UART4_SEL, 0U),
|
||||
CLK_UART5_SRC = CLK(CLK_UART5_SRC_SEL, CLK_UART5_SRC_DIV),
|
||||
CLK_UART5_FRAC = CLK(0U, CLK_UART5_FRAC_DIV),
|
||||
CLK_UART5 = CLK(SCLK_UART5_SEL, 0U),
|
||||
CLK_UART6_SRC = CLK(CLK_UART6_SRC_SEL, CLK_UART6_SRC_DIV),
|
||||
CLK_UART6_FRAC = CLK(0U, CLK_UART6_FRAC_DIV),
|
||||
CLK_UART6 = CLK(SCLK_UART6_SEL, 0U),
|
||||
CLK_UART7_SRC = CLK(CLK_UART7_SRC_SEL, CLK_UART7_SRC_DIV),
|
||||
CLK_UART7_FRAC = CLK(0U, CLK_UART7_FRAC_DIV),
|
||||
CLK_UART7 = CLK(SCLK_UART7_SEL, 0U),
|
||||
CLK_UART8_SRC = CLK(CLK_UART8_SRC_SEL, CLK_UART8_SRC_DIV),
|
||||
CLK_UART8_FRAC = CLK(0U, CLK_UART8_FRAC_DIV),
|
||||
CLK_UART8 = CLK(SCLK_UART8_SEL, 0U),
|
||||
CLK_UART9_SRC = CLK(CLK_UART9_SRC_SEL, CLK_UART9_SRC_DIV),
|
||||
CLK_UART9_FRAC = CLK(0U, CLK_UART9_FRAC_DIV),
|
||||
CLK_UART9 = CLK(SCLK_UART9_SEL, 0U),
|
||||
CLK_CAN0 = CLK(CLK_CAN0_SEL, CLK_CAN0_DIV),
|
||||
CLK_CAN1 = CLK(CLK_CAN1_SEL, CLK_CAN1_DIV),
|
||||
CLK_CAN2 = CLK(CLK_CAN2_SEL, CLK_CAN2_DIV),
|
||||
CLK_TSADC_TSEN = CLK(CLK_TSADC_TSEN_SEL, CLK_TSADC_TSEN_DIV),
|
||||
CLK_TSADC = CLK(0, CLK_TSADC_DIV),
|
||||
SCLK_SFC = CLK(SCLK_SFC_SEL, 0U),
|
||||
CLK_MAC0_2TOP = CLK(CLK_MAC0_2TOP_SEL, 0U),
|
||||
CLK_MAC1_2TOP = CLK(CLK_MAC1_2TOP_SEL, 0U),
|
||||
CLK_MAC0_OUT = CLK(CLK_MAC0_OUT_SEL, 0U),
|
||||
CLK_MAC1_OUT = CLK(CLK_MAC1_OUT_SEL, 0U),
|
||||
CLK_GMAC0_PTP_REF = CLK(CLK_GMAC0_PTP_REF_SEL, 0U),
|
||||
CLK_GMAC1_PTP_REF = CLK(CLK_GMAC1_PTP_REF_SEL, 0U),
|
||||
SCLK_GMAC0 = CLK(RMII0_EXTCLK_SEL, 0U),
|
||||
SCLK_GMAC1 = CLK(RMII1_EXTCLK_SEL, 0U),
|
||||
SCLK_GMAC0_RGMII_SPEED = CLK(RGMII0_CLK_SEL, 0U),
|
||||
SCLK_GMAC1_RGMII_SPEED = CLK(RGMII1_CLK_SEL, 0U),
|
||||
SCLK_GMAC0_RMII_SPEED = CLK(RMII0_CLK_SEL, 0U),
|
||||
SCLK_GMAC1_RMII_SPEED = CLK(RMII1_CLK_SEL, 0U),
|
||||
SCLK_GMAC0_RX_TX = CLK(CLK_GMAC0_RX_TX_SEL, 0U),
|
||||
SCLK_GMAC1_RX_TX = CLK(CLK_GMAC1_RX_TX_SEL, 0U),
|
||||
ACLK_PHP = CLK(ACLK_PHP_SEL, 0U),
|
||||
HCLK_PHP = CLK(HCLK_PHP_SEL, 0U),
|
||||
PCLK_PHP = CLK(0U, PCLK_PHP_DIV),
|
||||
ACLK_USB = CLK(ACLK_USB_SEL, 0U),
|
||||
HCLK_USB = CLK(HCLK_USB_SEL, 0U),
|
||||
PCLK_USB = CLK(0U, PCLK_USB_DIV),
|
||||
} eCLOCK_Name;
|
||||
#endif
|
||||
/****************************************MBOX********************************************/
|
||||
#define MBOX_CNT 2
|
||||
#define MBOX_CHAN_CNT 4
|
||||
/****************************************GRF*********************************************/
|
||||
#define GRF_IOMUX_BIT_PER_PIN (4)
|
||||
#define GRF_DS_BIT_PER_PIN (8)
|
||||
#define GRF_PULL_BIT_PER_PIN (2)
|
||||
/****************************************GPIO********************************************/
|
||||
#ifdef GPIO_VER_ID
|
||||
#undef GPIO_VER_ID
|
||||
#define GPIO_VER_ID (0x01000C2BU)
|
||||
#endif
|
||||
/****************************************PMU*********************************************/
|
||||
#ifndef __ASSEMBLY__
|
||||
typedef enum PD_Id {
|
||||
PD_INVALID = 0U,
|
||||
} ePD_Id;
|
||||
#endif
|
||||
/****************************************FSPI********************************************/
|
||||
#define FSPI_CHIP_CNT (2)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __SOC_H */
|
||||
@@ -0,0 +1,29 @@
|
||||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#ifndef __SYSTEM_RK3568_H_
|
||||
#define __SYSTEM_RK3568_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief Update SystemCoreClock variable.
|
||||
|
||||
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SYSTEM_RK3568_H_ */
|
||||
Reference in New Issue
Block a user