add cache module for XiZI_AIOT
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sivip
parent
779444f998
commit
19967930ff
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@ -4,5 +4,6 @@ ifeq ($(CONFIG_BOARD_IMX6Q_SABRELITE_EVB),y)
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SRC_DIR := cortex-a9
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endif
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SRC_FILES := cache.c
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include $(KERNEL_ROOT)/compiler.mk
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@ -0,0 +1,2 @@
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#include "cortex-a9/cortex_a9.h"
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#include "cortex-a9/arm_cp_registers.h"
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@ -0,0 +1,316 @@
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#include "arm_v7.h"
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////////////////////////////////////////////////////////////////////////////////
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// Code
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////////////////////////////////////////////////////////////////////////////////
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//! @brief Check if dcache is enabled or disabled
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int arm_dcache_state_query()
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{
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uint32_t sctlr; // System Control Register
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// read sctlr
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_ARM_MRC(15, 0, sctlr, 1, 0, 0);
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if (sctlr & BM_SCTLR_C)
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{
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return 1;
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} else {
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return 0;
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}
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}
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void arm_dcache_enable()
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{
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uint32_t sctlr; // System Control Register
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// read sctlr
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_ARM_MRC(15, 0, sctlr, 1, 0, 0);
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if (!(sctlr & BM_SCTLR_C))
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{
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// set C bit (data caching enable)
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sctlr |= BM_SCTLR_C;
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// write modified sctlr
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_ARM_MCR(15, 0, sctlr, 1, 0, 0);
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// All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
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_ARM_DSB();
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}
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}
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void arm_dcache_disable()
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{
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uint32_t sctlr; // System Control Register
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// read sctlr
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_ARM_MRC(15, 0, sctlr, 1, 0, 0);
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// set C bit (data caching enable)
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sctlr &= ~BM_SCTLR_C;
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// write modified sctlr
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_ARM_MCR(15, 0, sctlr, 1, 0, 0);
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// All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
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_ARM_DSB();
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}
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void arm_dcache_invalidate()
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{
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uint32_t csid; // Cache Size ID
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uint32_t wayset; // wayset parameter
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int num_sets; // number of sets
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int num_ways; // number of ways
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_ARM_MRC(15, 1, csid, 0, 0, 0); // Read Cache Size ID
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// Fill number of sets and number of ways from csid register This walues are decremented by 1
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num_ways = (csid >> 0x03) & 0x3FFu; //((csid& csid_ASSOCIATIVITY_MASK) >> csid_ASSOCIATIVITY_SHIFT)
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// Invalidation all lines (all Sets in all ways)
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while (num_ways >= 0)
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{
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num_sets = (csid >> 0x0D) & 0x7FFFu; //((csid & csid_NUMSETS_MASK) >> csid_NUMSETS_SHIFT)
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while (num_sets >= 0 )
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{
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wayset = (num_sets << 5u) | (num_ways << 30u); //(num_sets << SETWAY_SET_SHIFT) | (num_sets << 3SETWAY_WAY_SHIFT)
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// invalidate line if we know set and way
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_ARM_MCR(15, 0, wayset, 7, 6, 2);
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num_sets--;
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}
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num_ways--;
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}
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// All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
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_ARM_DSB();
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}
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void arm_dcache_invalidate_line(const void * addr)
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{
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uint32_t csidr = 0, line_size = 0;
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uint32_t va;
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// get the cache line size
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_ARM_MRC(15, 1, csidr, 0, 0, 0);
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line_size = 1 << ((csidr & 0x7) + 4);
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va = (uint32_t) addr & (~(line_size - 1)); //addr & va_VIRTUAL_ADDRESS_MASK
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// Invalidate data cache line by va to PoC (Point of Coherency).
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_ARM_MCR(15, 0, va, 7, 6, 1);
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// All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
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_ARM_DSB();
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}
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void arm_dcache_invalidate_mlines(const void * addr, size_t length)
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{
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uint32_t va;
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uint32_t csidr = 0, line_size = 0;
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// get the cache line size
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_ARM_MRC(15, 1, csidr, 0, 0, 0);
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line_size = 1 << ((csidr & 0x7) + 4);
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// align the address with line
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const void * end_addr = (const void *)((uint32_t)addr + length);
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do
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{
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// Clean data cache line to PoC (Point of Coherence) by va.
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va = (uint32_t) ((uint32_t)addr & (~(line_size - 1))); //addr & va_VIRTUAL_ADDRESS_MASK
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_ARM_MCR(15, 0, va, 7, 6, 1);
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// increment addres to next line and decrement lenght
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addr = (const void *) ((uint32_t)addr + line_size);
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} while (addr < end_addr);
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// All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
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_ARM_DSB();
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}
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void arm_dcache_flush()
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{
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uint32_t csid; // Cache Size ID
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uint32_t wayset; // wayset parameter
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int num_sets; // number of sets
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int num_ways; // number of ways
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_ARM_MRC(15, 1, csid, 0, 0, 0); // Read Cache Size ID
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// Fill number of sets and number of ways from csid register This walues are decremented by 1
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num_ways = (csid >> 0x03) & 0x3FFu; //((csid& csid_ASSOCIATIVITY_MASK) >> csid_ASSOCIATIVITY_SHIFT`)
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while (num_ways >= 0)
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{
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num_sets = (csid >> 0x0D) & 0x7FFFu; //((csid & csid_NUMSETS_MASK) >> csid_NUMSETS_SHIFT )
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while (num_sets >= 0 )
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{
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wayset = (num_sets << 5u) | (num_ways << 30u); //(num_sets << SETWAY_SET_SHIFT) | (num_ways << 3SETWAY_WAY_SHIFT)
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// FLUSH (clean) line if we know set and way
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_ARM_MCR(15, 0, wayset, 7, 10, 2);
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num_sets--;
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}
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num_ways--;
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}
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// All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
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_ARM_DSB();
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}
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void arm_dcache_flush_line(const void * addr)
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{
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uint32_t csidr = 0, line_size = 0;
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uint32_t va;
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// get the cache line size
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_ARM_MRC(15, 1, csidr, 0, 0, 0);
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line_size = 1 << ((csidr & 0x7) + 4);
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va = (uint32_t) addr & (~(line_size - 1)); //addr & va_VIRTUAL_ADDRESS_MASK
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// Clean data cache line to PoC (Point of Coherence) by va.
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_ARM_MCR(15, 0, va, 7, 10, 1);
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// All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
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_ARM_DSB();
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}
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void arm_dcache_flush_mlines(const void * addr, size_t length)
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{
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uint32_t va;
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uint32_t csidr = 0, line_size = 0;
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const void * end_addr = (const void *)((uint32_t)addr + length);
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// get the cache line size
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_ARM_MRC(15, 1, csidr, 0, 0, 0);
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line_size = 1 << ((csidr & 0x7) + 4);
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do
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{
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// Clean data cache line to PoC (Point of Coherence) by va.
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va = (uint32_t) ((uint32_t)addr & (~(line_size - 1))); //addr & va_VIRTUAL_ADDRESS_MASK
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_ARM_MCR(15, 0, va, 7, 10, 1);
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// increment addres to next line and decrement lenght
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addr = (const void *) ((uint32_t)addr + line_size);
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} while (addr < end_addr);
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// All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
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_ARM_DSB();
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}
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int arm_icache_state_query()
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{
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uint32_t sctlr; // System Control Register
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// read sctlr
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_ARM_MRC(15, 0, sctlr, 1, 0, 0);
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if (sctlr & BM_SCTLR_I)
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{
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return 1;
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} else {
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return 0;
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}
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}
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void arm_icache_enable()
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{
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uint32_t sctlr ;// System Control Register
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// read sctlr
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_ARM_MRC(15, 0, sctlr, 1, 0, 0);
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// ignore the operation if I is enabled already
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if(!(sctlr & BM_SCTLR_I))
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{
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// set I bit (instruction caching enable)
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sctlr |= BM_SCTLR_I;
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// write modified sctlr
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_ARM_MCR(15, 0, sctlr, 1, 0, 0);
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// synchronize context on this processor
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_ARM_ISB();
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}
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}
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void arm_icache_disable()
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{
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uint32_t sctlr ;// System Control Register
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// read sctlr
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_ARM_MRC(15, 0, sctlr, 1, 0, 0);
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// Clear I bit (instruction caching enable)
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sctlr &= ~BM_SCTLR_I;
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// write modified sctlr
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_ARM_MCR(15, 0, sctlr, 1, 0, 0);
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// synchronize context on this processor
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_ARM_ISB();
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}
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void arm_icache_invalidate()
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{
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uint32_t SBZ = 0x0u;
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_ARM_MCR(15, 0, SBZ, 7, 5, 0);
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// synchronize context on this processor
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_ARM_ISB();
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}
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void arm_icache_invalidate_is()
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{
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uint32_t SBZ = 0x0u;
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_ARM_MCR(15, 0, SBZ, 7, 1, 0);
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// synchronize context on this processor
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_ARM_ISB();
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}
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void arm_icache_invalidate_line(const void * addr)
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{
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uint32_t csidr = 0, line_size = 0;
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uint32_t va;
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// get the cache line size
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_ARM_MRC(15, 1, csidr, 0, 0, 0);
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line_size = 1 << ((csidr & 0x7) + 4);
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va = (uint32_t) addr & (~(line_size - 1)); //addr & va_VIRTUAL_ADDRESS_MASK
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// Invalidate instruction cache by va to PoU (Point of unification).
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_ARM_MCR(15, 0, va, 7, 5, 1);
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// synchronize context on this processor
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_ARM_ISB();
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}
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void arm_icache_invalidate_mlines(const void * addr, size_t length)
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{
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uint32_t va;
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uint32_t csidr = 0, line_size = 0;
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const void * end_addr = (const void *)((uint32_t)addr + length);
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// get the cache line size
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_ARM_MRC(15, 1, csidr, 0, 0, 0);
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line_size = 1 << ((csidr & 0x7) + 4);
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do
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{
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// Clean data cache line to PoC (Point of Coherence) by va.
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va = (uint32_t) ((uint32_t)addr & (~(line_size - 1))); //addr & va_VIRTUAL_ADDRESS_MASK
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_ARM_MCR(15, 0, va, 7, 5, 1);
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// increment addres to next line and decrement lenght
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addr = (const void *) ((uint32_t)addr + line_size);
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} while (addr < end_addr);
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// synchronize context on this processor
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_ARM_ISB();
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}
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////////////////////////////////////////////////////////////////////////////////
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// EOF
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////////////////////////////////////////////////////////////////////////////////
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@ -0,0 +1,52 @@
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/*!
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* @file arm_cp_registers.h
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* @brief Definitions for ARM coprocessor registers.
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*/
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#ifndef __ARM_CP_REGISTERS_H__
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#define __ARM_CP_REGISTERS_H__
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////////////////////////////////////////////////////////////////////////////////
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// Definitions
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////////////////////////////////////////////////////////////////////////////////
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//! @name ACTLR
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//@{
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#define BM_ACTLR_SMP (1 << 6)
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//@}
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//! @name DFSR
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//@{
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#define BM_DFSR_WNR (1 << 11) //!< Write not Read bit. 0=read, 1=write.
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#define BM_DFSR_FS4 (0x400) //!< Fault status bit 4..
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#define BP_DFSR_FS4 (10) //!< Bit position for FS[4].
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#define BM_DFSR_FS (0xf) //!< Fault status bits [3:0].
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//@}
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//! @name SCTLR
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//@{
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#define BM_SCTLR_TE (1 << 30) //!< Thumb exception enable.
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#define BM_SCTLR_AFE (1 << 29) //!< Access flag enable.
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#define BM_SCTLR_TRE (1 << 28) //!< TEX remap enable.
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#define BM_SCTLR_NMFI (1 << 27) //!< Non-maskable FIQ support.
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#define BM_SCTLR_EE (1 << 25) //!< Exception endianess.
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#define BM_SCTLR_VE (1 << 24) //!< Interrupt vectors enable.
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#define BM_SCTLR_FI (1 << 21) //!< Fast interrupt configurable enable.
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#define BM_SCTLR_RR (1 << 14) //!< Round Robin
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#define BM_SCTLR_V (1 << 13) //!< Vectors
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#define BM_SCTLR_I (1 << 12) //!< Instruction cache enable
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#define BM_SCTLR_Z (1 << 11) //!< Branch prediction enable
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#define BM_SCTLR_SW (1 << 10) //!< SWP and SWPB enable
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#define BM_SCTLR_CP15BEN (1 << 5) //!< CP15 barrier enable
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#define BM_SCTLR_C (1 << 2) //!< Data cache enable
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#define BM_SCTLR_A (1 << 1) //!< Alignment check enable
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#define BM_SCTLR_M (1 << 0) //!< MMU enable
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//@}
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//! @}
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#endif // __ARM_CP_REGISTERS_H__
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////////////////////////////////////////////////////////////////////////////////
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// EOF
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////////////////////////////////////////////////////////////////////////////////
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