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Support rk3568.(TODO: fix userland)

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This commit is contained in:
TXuian
2024-06-07 16:47:03 +08:00
parent 872a2df6ff
commit 148b422006
35 changed files with 108 additions and 123 deletions
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Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/bootmmu.c
+5 -41
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@@ -33,8 +33,6 @@ Modification:
#include "pagetable.h"
#include "registers.h"
#include "ns16550.h"
#include <stdint.h>
#include <string.h>
@@ -69,15 +67,6 @@ uint64_t boot_kern_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = {
uint64_t boot_dev_l4pgdirs[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 };
uint64_t boot_kern_l4pgdirs[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 };
static inline int cpu_id()
{
int x = -1;
__asm__ volatile("mrs %0, mpidr_el1" : "=r"(x));
return x & 0x3;
}
extern int debug_printf_(const char* format, ...);
static void build_boot_pgdir()
{
static bool built = false;
@@ -86,9 +75,7 @@ static void build_boot_pgdir()
// dev mem
boot_l2pgdir[(dev_phy_mem_base >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
// boot_l2pgdir[(dev_phy_mem_base >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)0xEFFF1000ULL | L2_TYPE_TAB | L2_PTE_VALID;
boot_l2pgdir[(MMIO_P2V_WO(dev_phy_mem_base) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
// boot_l2pgdir[(MMIO_P2V_WO(dev_phy_mem_base) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)0xEFFF1000ULL | L2_TYPE_TAB | L2_PTE_VALID;
uint64_t cur_mem_paddr = ALIGNDOWN((uint64_t)DEV_PHYMEM_BASE, LEVEL2_PDE_SIZE);
for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) {
@@ -134,28 +121,22 @@ static void build_boot_pgdir()
}
}
extern void el2_setup(void);
#include "log.h"
static void load_boot_pgdir()
{
// debug_printf_("Loading TTBR0 %x.\r\n", boot_l2pgdir);
TTBR0_W((uintptr_t)boot_l2pgdir);
// TTBR0_W((uintptr_t)0xEFFF0000);
// TTBR1_W(0);
TTBR1_W(0);
#define TCR_TRUE_VALUE (0x0000000080813519ULL)
uint64_t tcr = 0;
TCR_W(TCR_TRUE_VALUE);
TCR_R(tcr);
uint64_t mair = 0;
MAIR_R(mair);
// MAIR_W((MT_DEVICE_nGnRnE << (8 * AI_DEVICE_nGnRnE_IDX)) | (MT_NORMAL_NC << (8 * AI_NORMAL_NC_IDX)));
// debug_printf_("TCR: %016lx(0x%016lx)\r\n", tcr, TCR_VALUE);
// debug_printf_("MAIR: %016lx\r\n", mair);
tcr &= (uint64_t)~0xFF;
tcr |= 0x19;
TCR_W(tcr);
// Enable paging using read/modify/write
// debug_printf_("Loading SCTLR.\r\n");
// uint32_t val = 0;
// SCTLR_R(val);
// debug_printf_("Old SCTLR: %016lx\r\n", val);
@@ -177,8 +158,6 @@ static void load_boot_pgdir()
DSB();
CLEARTLB(0);
ISB();
// debug_printf_("Alive after TLB.\r\n");
}
static inline unsigned int current_el(void)
@@ -192,27 +171,12 @@ extern void main(void);
static bool _bss_inited = false;
void bootmain()
{
// debug_printf_("building pgdir.\r\n");
build_boot_pgdir();
// debug_printf_("l2[0]: %p\r\n", boot_l2pgdir[0]);
// debug_printf_("l2[1]: %p\r\n", boot_l2pgdir[1]);
// debug_printf_("l2[2]: %p\r\n", boot_l2pgdir[2]);
// debug_printf_("l2[3]: %p\r\n", boot_l2pgdir[3]);
// debug_printf_("loading pgdir, current el: %d\r\n", current_el());
load_boot_pgdir();
// debug_printf_("loading pgdir, current el: %d\r\n", current_el());
// debug_printf_("test upper address: %x\r\n", *(uintptr_t*)P2V(boot_l2pgdir));
// el2_setup();
// unsigned int el = current_el();
// debug_printf_("loading pgdir, current el: %d\r\n", el);
// debug_printf_("Fix stack.\r\n");
__asm__ __volatile__("add sp, sp, %0" ::"r"(KERN_OFFSET));
// debug_printf_("Alive after fix stack.\r\n");
if (!_bss_inited) {
// debug_printf_("Clear bss.\r\n");
memset(&kernel_data_begin, 0x00, (size_t)((uint64_t)kernel_data_end - (uint64_t)kernel_data_begin));
_bss_inited = true;
}
// debug_printf_("Going main.\r\n");
main();
}
Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/mmu.c
-2
View File
@@ -35,8 +35,6 @@ Modification:
#include "mmu_common.h"
#include "trap_common.h"
#include "log.h"
// extern struct MmuCommonDone mmu_common_done;
static struct MmuDriverRightGroup right_group;
Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/ok1028a-c/memlayout.h
+4 -4
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@@ -61,14 +61,14 @@ Modification:
#define MAX_NR_FREE_PAGES ((PHY_MEM_STOP - PHY_MEM_BASE) >> LEVEL4_PTE_SHIFT)
/* Deivce memory layout */
#define DEV_PHYMEM_BASE (0x00000000C0000000ULL)
#define DEV_VRTMEM_BASE (0x00000040C0000000ULL)
#define DEV_MEM_SIZE (0x0000000040000000ULL)
#define DEV_PHYMEM_BASE (0x00000000F0000000ULL)
#define DEV_VRTMEM_BASE (0x00000040F0000000ULL)
#define DEV_MEM_SIZE (0x0000000010000000ULL)
/* User memory layout */
#define USER_STACK_SIZE PAGE_SIZE
#define USER_MEM_BASE (0x0000000000000000ULL)
#define USER_MEM_TOP DEV_VRTMEM_BASE
#define USER_MEM_TOP (0x0000004000000000ULL)
#define USER_IPC_SPACE_BASE (0x0000003000000000ULL)
#define USER_IPC_USE_ALLOCATOR_WATERMARK (0x0000003000010000ULL)
#define USER_IPC_SPACE_TOP (USER_IPC_SPACE_BASE + 0x10000000ULL)
Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/pagetable_attr.c
+2 -3
View File
@@ -53,20 +53,19 @@ Modification:
void GetUsrPteAttr(uintptr_t* attr)
{
// *attr = ARMV8_PTE_AP_U | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_NORMAL | ARMV8_PTE_VALID;
*attr = 0x753;
*attr = 0x713 | ARMV8_PTE_AP_U;
}
void GetUsrDevPteAttr(uintptr_t* attr)
{
// *attr = ARMV8_PTE_AP_U | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_DEVICE | ARMV8_PTE_XN | ARMV8_PTE_VALID;
*attr = 0x443;
*attr = 0x403 | ARMV8_PTE_AP_U;
}
void GetDevPteAttr(uintptr_t* attr)
{
// *attr = ARMV8_PTE_AP_K | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_DEVICE | ARMV8_PTE_XN | ARMV8_PTE_VALID;
*attr = 0x403ULL;
// *attr = 0x711;
}
void GetKernPteAttr(uintptr_t* attr)