177 lines
4.8 KiB
C
177 lines
4.8 KiB
C
/*----------------------------------------------------------------------------
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* Tencent is pleased to support the open source community by making TencentOS
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* available.
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*
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* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
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* If you have downloaded a copy of the TencentOS binary from Tencent, please
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* note that the TencentOS binary is licensed under the BSD 3-Clause License.
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*
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* If you have downloaded a copy of the TencentOS source code from Tencent,
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* please note that TencentOS source code is licensed under the BSD 3-Clause
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* License, except for the third-party components listed below which are
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* subject to different license terms. Your integration of TencentOS into your
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* own projects may require compliance with the BSD 3-Clause License, as well
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* as the other licenses applicable to the third-party components included
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* within TencentOS.
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*---------------------------------------------------------------------------*/
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#include "tos_k.h"
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#include "core_cm0plus.h"
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extern __KNL__ void knl_sched(void);
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__PORT__ void port_cpu_reset(void)
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{
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NVIC_SystemReset();
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}
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__PORT__ void port_systick_config(uint32_t cycle_per_tick)
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{
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(void)SysTick_Config(cycle_per_tick);
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}
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__PORT__ void port_systick_priority_set(uint32_t prio)
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{
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NVIC_SetPriority(SysTick_IRQn, prio);
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}
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#if TOS_CFG_TICKLESS_EN > 0u
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__PORT__ k_time_t port_systick_max_delay_millisecond(void)
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{
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k_time_t max_millisecond;
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uint32_t max_cycle;
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max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
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max_millisecond = (k_time_t)((uint64_t)max_cycle * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_CLOCK); // CLOCK: cycle per second
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return max_millisecond;
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}
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__PORT__ void port_systick_resume(void)
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{
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SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
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SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
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}
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__PORT__ void port_systick_suspend(void)
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{
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SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
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SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
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}
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__PORT__ void port_systick_reload(uint32_t cycle_per_tick)
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{
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port_systick_config(cycle_per_tick);
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}
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__PORT__ void port_systick_pending_reset(void)
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{
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SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
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}
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#endif
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#if TOS_CFG_PWR_MGR_EN > 0u
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__PORT__ void port_sleep_mode_enter(void)
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{
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#if 1
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HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
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#else
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HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
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#endif
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}
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__PORT__ void port_stop_mode_enter(void)
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{
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HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
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}
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__PORT__ void port_standby_mode_enter(void)
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{
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HAL_PWR_EnterSTANDBYMode();
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}
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#endif
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#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
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__PORT__ void port_fault_diagnosis(void)
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{
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k_fault_log_writer("fault diagnosis is not supported in CORTEX M0+\n");
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}
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/*------------------ RealView Compiler -----------------*/
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/* V5 */
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#if defined(__CC_ARM)
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__PORT__ __ASM__ void HardFault_Handler(void)
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{
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IMPORT fault_backtrace
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MOV r0, lr
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TST lr, #0x04
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ITE EQ
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MRSEQ r1, MSP
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MRSNE r1, PSP
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BL fault_backtrace
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}
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/*------------------ ARM Compiler V6 -------------------*/
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#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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__PORT__ void __NAKED__ HardFault_Handler(void)
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{
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__ASM__ __VOLATILE__ (
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"MOV r0, lr\n\t"
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"TST lr, #0x04\n\t"
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"ITE EQ\n\t"
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"MRSEQ r1, MSP\n\t"
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"MRSNE r1, PSP\n\t"
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"BL fault_backtrace\n\t"
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);
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}
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#endif /* ARMCC VERSION */
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#endif /* TOS_CFG_FAULT_BACKTRACE_EN */
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#if USE_SMP ==1u
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#define INVALID_PRIMARY_CORE_NUM 0xffu
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uint8_t ucPrimaryCoreNum = INVALID_PRIMARY_CORE_NUM;
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__PORT__ void portSCHED_CORE (int xCoreID ){
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assert(xCoreID != port_GET_CORE_ID());
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#if USE_SMP>0u
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/* Non blocking, will cause interrupt on other core if the queue isn't already full,
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in which case an IRQ must be pending */
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sio_hw->fifo_wr = 0;
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#endif
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}
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__PORT__ __STATIC__ void prvFIFOInterruptHandler(void)
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{
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/* We must remove the contents (which we don't care about)
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* to clear the IRQ */
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multicore_fifo_drain();
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/* And explicitly clear any other IRQ flags */
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multicore_fifo_clear_irq();
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#if (USE_SMP == 1u)
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knl_sched();
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#endif /* portRUNNING_ON_BOTH_CORES */
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}
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__PORT__ void port_smp_init_kernel(void){
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//设置PENDSV_EXCEPTION中断处理函数，用于切换上下文
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//exception_set_exclusive_handler( PENDSV_EXCEPTION, PendSV_smp_Handler);
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/* Install FIFO handler to receive interrupt from other core */
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multicore_fifo_clear_irq();
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multicore_fifo_drain();
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uint32_t ulIRQNum = SIO_IRQ_PROC0 + get_core_num();
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irq_set_priority( ulIRQNum, portMIN_INTERRUPT_PRIORITY );
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irq_set_exclusive_handler( ulIRQNum, prvFIFOInterruptHandler );
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irq_set_enabled( ulIRQNum, 1 );
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}
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uint8_t ucOwnedByCore[ portMAX_CORE_COUNT ]={0};
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uint8_t ucRecursionCountByLock[ portRTOS_SPINLOCK_COUNT ]={0};
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#endif
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